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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "arm7tdmi.h"
  31
  32 #include "arm7_9_common.h"
  33 #include "register.h"
  34 #include "target.h"
  35 #include "armv4_5.h"
  36 #include "embeddedice.h"
  37 #include "etm.h"
  38 #include "log.h"
  39 #include "jtag.h"
  40 #include "arm_jtag.h"
  41
  42 #include <stdlib.h>
  43 #include <string.h>
  44
  45 #if 0
  46 #define _DEBUG_INSTRUCTION_EXECUTION_
  47 #endif
  48
  49 /* forward declarations */
  50
  51 int arm7tdmi_target_create(struct target_s *target,Jim_Interp *interp);
  52 int arm7tdmi_quit(void);
  53
  54 /* target function declarations */
  55 int arm7tdmi_poll(struct target_s *target);
  56 int arm7tdmi_halt(target_t *target);
  57
  58 target_type_t arm7tdmi_target =
  59 {
  60         .name = "arm7tdmi",
  61
  62         .poll = arm7_9_poll,
  63         .arch_state = armv4_5_arch_state,
  64
  65         .target_request_data = arm7_9_target_request_data,
  66
  67         .halt = arm7_9_halt,
  68         .resume = arm7_9_resume,
  69         .step = arm7_9_step,
  70
  71         .assert_reset = arm7_9_assert_reset,
  72         .deassert_reset = arm7_9_deassert_reset,
  73         .soft_reset_halt = arm7_9_soft_reset_halt,
  74
  75         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  76
  77         .read_memory = arm7_9_read_memory,
  78         .write_memory = arm7_9_write_memory,
  79         .bulk_write_memory = arm7_9_bulk_write_memory,
  80         .checksum_memory = arm7_9_checksum_memory,
  81         .blank_check_memory = arm7_9_blank_check_memory,
  82
  83         .run_algorithm = armv4_5_run_algorithm,
  84
  85         .add_breakpoint = arm7_9_add_breakpoint,
  86         .remove_breakpoint = arm7_9_remove_breakpoint,
  87         .add_watchpoint = arm7_9_add_watchpoint,
  88         .remove_watchpoint = arm7_9_remove_watchpoint,
  89
  90         .register_commands  = arm7tdmi_register_commands,
  91         .target_create  = arm7tdmi_target_create,
  92         .init_target = arm7tdmi_init_target,
  93         .examine = arm7tdmi_examine,
  94         .quit = arm7tdmi_quit
  95 };
  96
  97 int arm7tdmi_examine_debug_reason(target_t *target)
  98 {
  99         int retval = ERROR_OK;
 100         /* get pointers to arch-specific information */
 101         armv4_5_common_t *armv4_5 = target->arch_info;
 102         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 103
 104         /* only check the debug reason if we don't know it already */
 105         if ((target->debug_reason != DBG_REASON_DBGRQ)
 106                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 107         {
 108                 scan_field_t fields[2];
 109                 u8 databus[4];
 110                 u8 breakpoint;
 111
 112                 jtag_add_end_state(TAP_DRPAUSE);
 113
 114                 fields[0].tap = arm7_9->jtag_info.tap;
 115                 fields[0].num_bits = 1;
 116                 fields[0].out_value = NULL;
 117                 fields[0].in_value = &breakpoint;
 118                 fields[0].in_handler = NULL;
 119
 120                 fields[1].tap = arm7_9->jtag_info.tap;
 121                 fields[1].num_bits = 32;
 122                 fields[1].out_value = NULL;
 123                 fields[1].in_value = databus;
 124                 fields[1].in_handler = NULL;
 125
 126                 if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 127                 {
 128                         return retval;
 129                 }
 130                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 131
 132                 jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
 133                 if((retval = jtag_execute_queue()) != ERROR_OK)
 134                 {
 135                         return retval;
 136                 }
 137
 138                 fields[0].in_value = NULL;
 139                 fields[0].out_value = &breakpoint;
 140                 fields[1].in_value = NULL;
 141                 fields[1].out_value = databus;
 142
 143                 jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
 144
 145                 if (breakpoint & 1)
 146                         target->debug_reason = DBG_REASON_WATCHPOINT;
 147                 else
 148                         target->debug_reason = DBG_REASON_BREAKPOINT;
 149         }
 150
 151         return ERROR_OK;
 152 }
 153
 154 static int arm7tdmi_num_bits[]={1, 32};
 155 static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
 156 {
 157         u32 values[2]={breakpoint, flip_u32(out, 32)};
 158
 159         jtag_add_dr_out(jtag_info->tap,
 160                         2,
 161                         arm7tdmi_num_bits,
 162                         values,
 163                         TAP_INVALID);
 164
 165         jtag_add_runtest(0, TAP_INVALID);
 166
 167         return ERROR_OK;
 168 }
 169
 170 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
 171 static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
 172 {
 173         jtag_add_end_state(TAP_DRPAUSE);
 174         arm_jtag_scann(jtag_info, 0x1);
 175         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 176
 177         return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
 178 }
 179
 180 /* clock the target, reading the databus */
 181 int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 182 {
 183         int retval = ERROR_OK;
 184         scan_field_t fields[2];
 185
 186         jtag_add_end_state(TAP_DRPAUSE);
 187         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 188         {
 189                 return retval;
 190         }
 191         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 192
 193         fields[0].tap = jtag_info->tap;
 194         fields[0].num_bits = 1;
 195         fields[0].out_value = NULL;
 196         fields[0].in_value = NULL;
 197         fields[0].in_handler = NULL;
 198
 199
 200         fields[1].tap = jtag_info->tap;
 201         fields[1].num_bits = 32;
 202         fields[1].out_value = NULL;
 203         u8 tmp[4];
 204         fields[1].in_value = tmp;
 205         fields[1].in_handler = NULL;
 206
 207         jtag_add_dr_scan_now(2, fields, TAP_INVALID);
 208
 209         if (jtag_error==ERROR_OK)
 210         {
 211                 *in=flip_u32(le_to_h_u32(tmp), 32);
 212         }
 213
 214         jtag_add_runtest(0, TAP_INVALID);
 215
 216 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 217 {
 218                 if((retval = jtag_execute_queue()) != ERROR_OK)
 219                 {
 220                         return retval;
 221                 }
 222
 223                 if (in)
 224                 {
 225                         LOG_DEBUG("in: 0x%8.8x", *in);
 226                 }
 227                 else
 228                 {
 229                         LOG_ERROR("BUG: called with in == NULL");
 230                 }
 231 }
 232 #endif
 233
 234         return ERROR_OK;
 235 }
 236
 237 void arm_endianness(u8 *tmp, void *in, int size, int be)
 238 {
 239         u32 readback=flip_u32(le_to_h_u32(tmp), 32);
 240         switch (size)
 241         {
 242                 case 4:
 243                         if (be)
 244                         {
 245                                 h_u32_to_be(((u8*)in), readback);
 246                         } else
 247                         {
 248                                  h_u32_to_le(((u8*)in), readback);
 249                         }
 250                         break;
 251                 case 2:
 252                         if (be)
 253                         {
 254                                 h_u16_to_be(((u8*)in), readback & 0xffff);
 255                         } else
 256                         {
 257                                 h_u16_to_le(((u8*)in), readback & 0xffff);
 258                         }
 259                         break;
 260                 case 1:
 261                         *((u8 *)in)= readback & 0xff;
 262                         break;
 263         }
 264
 265 }
 266
 267 /* clock the target, and read the databus
 268  * the *in pointer points to a buffer where elements of 'size' bytes
 269  * are stored in big (be==1) or little (be==0) endianness
 270  */
 271 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 272 {
 273         int retval = ERROR_OK;
 274         scan_field_t fields[2];
 275
 276         jtag_add_end_state(TAP_DRPAUSE);
 277         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 278         {
 279                 return retval;
 280         }
 281         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 282
 283         fields[0].tap = jtag_info->tap;
 284         fields[0].num_bits = 1;
 285         fields[0].out_value = NULL;
 286         fields[0].in_value = NULL;
 287         fields[0].in_handler = NULL;
 288
 289         fields[1].tap = jtag_info->tap;
 290         fields[1].num_bits = 32;
 291         fields[1].out_value = NULL;
 292         u8 tmp[4];
 293         fields[1].in_value = tmp;
 294         fields[1].in_handler = NULL;
 295
 296         jtag_add_dr_scan_now(2, fields, TAP_INVALID);
 297
 298         arm_endianness(tmp, in, size, be);
 299
 300         jtag_add_runtest(0, TAP_INVALID);
 301
 302 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 303 {
 304                 if((retval = jtag_execute_queue()) != ERROR_OK)
 305                 {
 306                         return retval;
 307                 }
 308
 309                 if (in)
 310                 {
 311                         LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
 312                 }
 313                 else
 314                 {
 315                         LOG_ERROR("BUG: called with in == NULL");
 316                 }
 317 }
 318 #endif
 319
 320         return ERROR_OK;
 321 }
 322
 323 void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 324 {
 325         /* get pointers to arch-specific information */
 326         armv4_5_common_t *armv4_5 = target->arch_info;
 327         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 328         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 329
 330         /* save r0 before using it and put system in ARM state
 331          * to allow common handling of ARM and THUMB debugging */
 332
 333         /* fetch STR r0, [r0] */
 334         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
 335         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 336         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 337         /* nothing fetched, STR r0, [r0] in Execute (2) */
 338         arm7tdmi_clock_data_in(jtag_info, r0);
 339
 340         /* MOV r0, r15 fetched, STR in Decode */
 341         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
 342         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
 343         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 344         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 345         /* nothing fetched, STR r0, [r0] in Execute (2) */
 346         arm7tdmi_clock_data_in(jtag_info, pc);
 347
 348         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 349         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
 350         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 351         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 352         /* nothing fetched, data for LDR r0, [PC, #0] */
 353         arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
 354         /* nothing fetched, data from previous cycle is written to register */
 355         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 356
 357         /* fetch BX */
 358         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
 359         /* NOP fetched, BX in Decode, MOV in Execute */
 360         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 361         /* NOP fetched, BX in Execute (1) */
 362         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 363
 364         jtag_execute_queue();
 365
 366         /* fix program counter:
 367          * MOV r0, r15 was the 4th instruction (+6)
 368          * reading PC in Thumb state gives address of instruction + 4
 369          */
 370         *pc -= 0xa;
 371 }
 372
 373 void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 374 {
 375         int i;
 376         /* get pointers to arch-specific information */
 377         armv4_5_common_t *armv4_5 = target->arch_info;
 378         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 379         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 380
 381         /* STMIA r0-15, [r0] at debug speed
 382          * register values will start to appear on 4th DCLK
 383          */
 384         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 385
 386         /* fetch NOP, STM in DECODE stage */
 387         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 388         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 389         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 390
 391         for (i = 0; i <= 15; i++)
 392         {
 393                 if (mask & (1 << i))
 394                         /* nothing fetched, STM still in EXECUTE (1+i cycle) */
 395                         arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
 396         }
 397 }
 398
 399 void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 400 {
 401         int i;
 402         /* get pointers to arch-specific information */
 403         armv4_5_common_t *armv4_5 = target->arch_info;
 404         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 405         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 406         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 407         u32 *buf_u32 = buffer;
 408         u16 *buf_u16 = buffer;
 409         u8 *buf_u8 = buffer;
 410
 411         /* STMIA r0-15, [r0] at debug speed
 412          * register values will start to appear on 4th DCLK
 413          */
 414         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 415
 416         /* fetch NOP, STM in DECODE stage */
 417         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 418         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 419         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 420
 421         for (i = 0; i <= 15; i++)
 422         {
 423                 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
 424                 if (mask & (1 << i))
 425                 {
 426                         switch (size)
 427                         {
 428                                 case 4:
 429                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 430                                         break;
 431                                 case 2:
 432                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 433                                         break;
 434                                 case 1:
 435                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 436                                         break;
 437                         }
 438                 }
 439         }
 440 }
 441
 442 void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 443 {
 444         /* get pointers to arch-specific information */
 445         armv4_5_common_t *armv4_5 = target->arch_info;
 446         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 447         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 448
 449         /* MRS r0, cpsr */
 450         arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
 451
 452         /* STR r0, [r15] */
 453         arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
 454         /* fetch NOP, STR in DECODE stage */
 455         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 456         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 457         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 458         /* nothing fetched, STR still in EXECUTE (2nd cycle) */
 459         arm7tdmi_clock_data_in(jtag_info, xpsr);
 460 }
 461
 462 void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 463 {
 464         /* get pointers to arch-specific information */
 465         armv4_5_common_t *armv4_5 = target->arch_info;
 466         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 467         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 468
 469         LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 470
 471         /* MSR1 fetched */
 472         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
 473         /* MSR2 fetched, MSR1 in DECODE */
 474         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), NULL, 0);
 475         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 476         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), NULL, 0);
 477         /* nothing fetched, MSR1 in EXECUTE (2) */
 478         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 479         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 480         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), NULL, 0);
 481         /* nothing fetched, MSR2 in EXECUTE (2) */
 482         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 483         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 484         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 485         /* nothing fetched, MSR3 in EXECUTE (2) */
 486         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 487         /* NOP fetched, MSR4 in EXECUTE (1) */
 488         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 489         /* nothing fetched, MSR4 in EXECUTE (2) */
 490         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 491 }
 492
 493 void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 494 {
 495         /* get pointers to arch-specific information */
 496         armv4_5_common_t *armv4_5 = target->arch_info;
 497         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 498         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 499
 500         LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 501
 502         /* MSR fetched */
 503         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
 504         /* NOP fetched, MSR in DECODE */
 505         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 506         /* NOP fetched, MSR in EXECUTE (1) */
 507         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 508         /* nothing fetched, MSR in EXECUTE (2) */
 509         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 510 }
 511
 512 void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 513 {
 514         int i;
 515         /* get pointers to arch-specific information */
 516         armv4_5_common_t *armv4_5 = target->arch_info;
 517         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 518         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 519
 520         /* LDMIA r0-15, [r0] at debug speed
 521         * register values will start to appear on 4th DCLK
 522         */
 523         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 524
 525         /* fetch NOP, LDM in DECODE stage */
 526         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 527         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 528         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 529
 530         for (i = 0; i <= 15; i++)
 531         {
 532                 if (mask & (1 << i))
 533                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 534                         arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
 535         }
 536         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 537 }
 538
 539 void arm7tdmi_load_word_regs(target_t *target, u32 mask)
 540 {
 541         /* get pointers to arch-specific information */
 542         armv4_5_common_t *armv4_5 = target->arch_info;
 543         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 544         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 545
 546         /* put system-speed load-multiple into the pipeline */
 547         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 548         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 549         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
 550 }
 551
 552 void arm7tdmi_load_hword_reg(target_t *target, int num)
 553 {
 554         /* get pointers to arch-specific information */
 555         armv4_5_common_t *armv4_5 = target->arch_info;
 556         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 557         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 558
 559         /* put system-speed load half-word into the pipeline */
 560         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 561         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 562         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
 563 }
 564
 565 void arm7tdmi_load_byte_reg(target_t *target, int num)
 566 {
 567         /* get pointers to arch-specific information */
 568         armv4_5_common_t *armv4_5 = target->arch_info;
 569         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 570         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 571
 572         /* put system-speed load byte into the pipeline */
 573         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 574         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 575         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
 576 }
 577
 578 void arm7tdmi_store_word_regs(target_t *target, u32 mask)
 579 {
 580         /* get pointers to arch-specific information */
 581         armv4_5_common_t *armv4_5 = target->arch_info;
 582         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 583         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 584
 585         /* put system-speed store-multiple into the pipeline */
 586         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 587         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 588         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
 589 }
 590
 591 void arm7tdmi_store_hword_reg(target_t *target, int num)
 592 {
 593         /* get pointers to arch-specific information */
 594         armv4_5_common_t *armv4_5 = target->arch_info;
 595         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 596         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 597
 598         /* put system-speed store half-word into the pipeline */
 599         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 600         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 601         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
 602 }
 603
 604 void arm7tdmi_store_byte_reg(target_t *target, int num)
 605 {
 606         /* get pointers to arch-specific information */
 607         armv4_5_common_t *armv4_5 = target->arch_info;
 608         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 609         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 610
 611         /* put system-speed store byte into the pipeline */
 612         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 613         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 614         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
 615 }
 616
 617 void arm7tdmi_write_pc(target_t *target, u32 pc)
 618 {
 619         /* get pointers to arch-specific information */
 620         armv4_5_common_t *armv4_5 = target->arch_info;
 621         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 622         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 623
 624         /* LDMIA r0-15, [r0] at debug speed
 625          * register values will start to appear on 4th DCLK
 626          */
 627         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0);
 628         /* fetch NOP, LDM in DECODE stage */
 629         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 630         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 631         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 632         /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
 633         arm7tdmi_clock_out_inner(jtag_info, pc, 0);
 634         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
 635         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 636         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
 637         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 638         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 639         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 640         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 641         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 642 }
 643
 644 void arm7tdmi_branch_resume(target_t *target)
 645 {
 646         /* get pointers to arch-specific information */
 647         armv4_5_common_t *armv4_5 = target->arch_info;
 648         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 649         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 650
 651         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 652         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
 653 }
 654
 655 void arm7tdmi_branch_resume_thumb(target_t *target)
 656 {
 657         LOG_DEBUG("-");
 658
 659         /* get pointers to arch-specific information */
 660         armv4_5_common_t *armv4_5 = target->arch_info;
 661         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 662         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 663         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 664
 665         /* LDMIA r0, [r0] at debug speed
 666          * register values will start to appear on 4th DCLK
 667          */
 668         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL, 0);
 669
 670         /* fetch NOP, LDM in DECODE stage */
 671         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 672         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 673         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 674         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 675         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 676         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 677         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 678
 679         /* Branch and eXchange */
 680         arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
 681
 682         embeddedice_read_reg(dbg_stat);
 683
 684         /* fetch NOP, BX in DECODE stage */
 685         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 686
 687         /* target is now in Thumb state */
 688         embeddedice_read_reg(dbg_stat);
 689
 690         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 691         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 692
 693         /* target is now in Thumb state */
 694         embeddedice_read_reg(dbg_stat);
 695
 696         /* load r0 value */
 697         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
 698         /* fetch NOP, LDR in Decode */
 699         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 700         /* fetch NOP, LDR in Execute */
 701         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 702         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 703         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 704         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 705         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 706
 707         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 708         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 709
 710         embeddedice_read_reg(dbg_stat);
 711
 712         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
 713         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
 714 }
 715
 716 void arm7tdmi_build_reg_cache(target_t *target)
 717 {
 718         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 719         /* get pointers to arch-specific information */
 720         armv4_5_common_t *armv4_5 = target->arch_info;
 721
 722         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 723         armv4_5->core_cache = (*cache_p);
 724 }
 725
 726 int arm7tdmi_examine(struct target_s *target)
 727 {
 728         int retval;
 729         armv4_5_common_t *armv4_5 = target->arch_info;
 730         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 731         if (!target->type->examined)
 732         {
 733                 /* get pointers to arch-specific information */
 734                 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 735                 reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
 736                 if (t==NULL)
 737                         return ERROR_FAIL;
 738
 739                 (*cache_p) = t;
 740                 arm7_9->eice_cache = (*cache_p);
 741
 742                 if (arm7_9->etm_ctx)
 743                 {
 744                         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 745                         (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 746                         arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
 747                 }
 748                 target->type->examined = 1;
 749         }
 750         if ((retval=embeddedice_setup(target))!=ERROR_OK)
 751                 return retval;
 752         if ((retval=arm7_9_setup(target))!=ERROR_OK)
 753                 return retval;
 754         if (arm7_9->etm_ctx)
 755         {
 756                 if ((retval=etm_setup(target))!=ERROR_OK)
 757                         return retval;
 758         }
 759         return ERROR_OK;
 760 }
 761
 762 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 763 {
 764         arm7tdmi_build_reg_cache(target);
 765
 766         return ERROR_OK;
 767 }
 768
 769 int arm7tdmi_quit(void)
 770 {
 771         return ERROR_OK;
 772 }
 773
 774 int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap)
 775 {
 776         armv4_5_common_t *armv4_5;
 777         arm7_9_common_t *arm7_9;
 778
 779         arm7_9 = &arm7tdmi->arm7_9_common;
 780         armv4_5 = &arm7_9->armv4_5_common;
 781
 782         /* prepare JTAG information for the new target */
 783         arm7_9->jtag_info.tap = tap;
 784         arm7_9->jtag_info.scann_size = 4;
 785
 786         /* register arch-specific functions */
 787         arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
 788         arm7_9->change_to_arm = arm7tdmi_change_to_arm;
 789         arm7_9->read_core_regs = arm7tdmi_read_core_regs;
 790         arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
 791         arm7_9->read_xpsr = arm7tdmi_read_xpsr;
 792
 793         arm7_9->write_xpsr = arm7tdmi_write_xpsr;
 794         arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
 795         arm7_9->write_core_regs = arm7tdmi_write_core_regs;
 796
 797         arm7_9->load_word_regs = arm7tdmi_load_word_regs;
 798         arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
 799         arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
 800
 801         arm7_9->store_word_regs = arm7tdmi_store_word_regs;
 802         arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
 803         arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
 804
 805         arm7_9->write_pc = arm7tdmi_write_pc;
 806         arm7_9->branch_resume = arm7tdmi_branch_resume;
 807         arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
 808
 809         arm7_9->enable_single_step = arm7_9_enable_eice_step;
 810         arm7_9->disable_single_step = arm7_9_disable_eice_step;
 811
 812         arm7_9->pre_debug_entry = NULL;
 813         arm7_9->post_debug_entry = NULL;
 814
 815         arm7_9->pre_restore_context = NULL;
 816         arm7_9->post_restore_context = NULL;
 817
 818         /* initialize arch-specific breakpoint handling */
 819         arm7_9->arm_bkpt = 0xdeeedeee;
 820         arm7_9->thumb_bkpt = 0xdeee;
 821
 822         arm7_9->dbgreq_adjust_pc = 2;
 823         arm7_9->arch_info = arm7tdmi;
 824
 825         arm7tdmi->arch_info = NULL;
 826         arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
 827
 828         arm7_9_init_arch_info(target, arm7_9);
 829
 830         return ERROR_OK;
 831 }
 832
 833 int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
 834 {
 835         arm7tdmi_common_t *arm7tdmi;
 836
 837         arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
 838         arm7tdmi_init_arch_info(target, arm7tdmi, target->tap);
 839
 840         return ERROR_OK;
 841 }
 842
 843 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
 844 {
 845         int retval;
 846
 847         retval = arm7_9_register_commands(cmd_ctx);
 848
 849         return retval;
 850 }