git.gag.com Git - fw/openocd/blob - src/target/arm7tdmi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "arm7tdmi.h"
  30 #include "target_type.h"
  31 #include "register.h"
  32 #include "arm_opcodes.h"
  33 #include "arm_semihosting.h"
  34
  35 /*
  36  * For information about ARM7TDMI, see ARM DDI 0210C (r4p1)
  37  * or ARM DDI 0029G (r3).  "Debug In Depth", Appendix B,
  38  * covers JTAG support.
  39  */
  40
  41 #if 0
  42 #define _DEBUG_INSTRUCTION_EXECUTION_
  43 #endif
  44
  45 static int arm7tdmi_examine_debug_reason(struct target *target)
  46 {
  47         int retval = ERROR_OK;
  48         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
  49
  50         /* only check the debug reason if we don't know it already */
  51         if ((target->debug_reason != DBG_REASON_DBGRQ)
  52                         && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
  53                 struct scan_field fields[2];
  54                 uint8_t databus[4];
  55                 uint8_t breakpoint;
  56
  57                 fields[0].num_bits = 1;
  58                 fields[0].out_value = NULL;
  59                 fields[0].in_value = &breakpoint;
  60
  61                 fields[1].num_bits = 32;
  62                 fields[1].out_value = NULL;
  63                 fields[1].in_value = databus;
  64
  65                 retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE);
  66                 if (retval != ERROR_OK)
  67                         return retval;
  68                 retval = arm_jtag_set_instr(arm7_9->jtag_info.tap, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
  69                 if (retval != ERROR_OK)
  70                         return retval;
  71
  72                 jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE);
  73                 retval = jtag_execute_queue();
  74                 if (retval != ERROR_OK)
  75                         return retval;
  76
  77                 fields[0].in_value = NULL;
  78                 fields[0].out_value = &breakpoint;
  79                 fields[1].in_value = NULL;
  80                 fields[1].out_value = databus;
  81
  82                 jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE);
  83
  84                 if (breakpoint & 1)
  85                         target->debug_reason = DBG_REASON_WATCHPOINT;
  86                 else
  87                         target->debug_reason = DBG_REASON_BREAKPOINT;
  88         }
  89
  90         return ERROR_OK;
  91 }
  92
  93 static const int arm7tdmi_num_bits[] = {1, 32};
  94
  95 static inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint)
  96 {
  97         uint8_t bp = breakpoint ? 1 : 0;
  98         uint8_t out_value[4];
  99         buf_set_u32(out_value, 0, 32, flip_u32(out, 32));
 100
 101         struct scan_field fields[2] = {
 102                         { .num_bits = arm7tdmi_num_bits[0], .out_value = &bp },
 103                         { .num_bits = arm7tdmi_num_bits[1], .out_value = out_value },
 104         };
 105
 106         jtag_add_dr_scan(jtag_info->tap,
 107                         2,
 108                         fields,
 109                         TAP_DRPAUSE);
 110
 111         jtag_add_runtest(0, TAP_DRPAUSE);
 112
 113         return ERROR_OK;
 114 }
 115
 116 /* put an instruction in the ARM7TDMI pipeline or write the data bus,
 117  * and optionally read data
 118  */
 119 static inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
 120                 uint32_t out, int breakpoint)
 121 {
 122         int retval;
 123         retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 124         if (retval != ERROR_OK)
 125                 return retval;
 126         retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 127         if (retval != ERROR_OK)
 128                 return retval;
 129
 130         return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
 131 }
 132
 133 /* clock the target, reading the databus */
 134 static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 135 {
 136         int retval = ERROR_OK;
 137         struct scan_field fields[2];
 138
 139         retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 140         if (retval != ERROR_OK)
 141                 return retval;
 142         retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 143         if (retval != ERROR_OK)
 144                 return retval;
 145
 146         fields[0].num_bits = 1;
 147         fields[0].out_value = NULL;
 148         fields[0].in_value = NULL;
 149
 150         fields[1].num_bits = 32;
 151         fields[1].out_value = NULL;
 152         fields[1].in_value = (uint8_t *)in;
 153
 154         jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
 155
 156         jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
 157
 158         jtag_add_runtest(0, TAP_DRPAUSE);
 159
 160 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 161         retval = jtag_execute_queue();
 162         if (retval != ERROR_OK)
 163                 return retval;
 164
 165         if (in)
 166                 LOG_DEBUG("in: 0x%8.8x", *in);
 167         else
 168                 LOG_ERROR("BUG: called with in == NULL");
 169 #endif
 170
 171         return ERROR_OK;
 172 }
 173
 174 /* clock the target, and read the databus
 175  * the *in pointer points to a buffer where elements of 'size' bytes
 176  * are stored in big (be == 1) or little (be == 0) endianness
 177  */
 178 static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
 179                 void *in, int size, int be)
 180 {
 181         int retval = ERROR_OK;
 182         struct scan_field fields[3];
 183
 184         retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 185         if (retval != ERROR_OK)
 186                 return retval;
 187         retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 188         if (retval != ERROR_OK)
 189                 return retval;
 190
 191         fields[0].num_bits = 1;
 192         fields[0].out_value = NULL;
 193         fields[0].in_value = NULL;
 194
 195         if (size == 4) {
 196                 fields[1].num_bits = 32;
 197                 fields[1].out_value = NULL;
 198                 fields[1].in_value = in;
 199         } else {
 200                 /* Discard irrelevant bits of the scan, making sure we don't write more
 201                  * than size bytes to in */
 202                 fields[1].num_bits = 32 - size * 8;
 203                 fields[1].out_value = NULL;
 204                 fields[1].in_value = NULL;
 205
 206                 fields[2].num_bits = size * 8;
 207                 fields[2].out_value = NULL;
 208                 fields[2].in_value = in;
 209         }
 210
 211         jtag_add_dr_scan(jtag_info->tap, size == 4 ? 2 : 3, fields, TAP_DRPAUSE);
 212
 213         jtag_add_callback4(arm7_9_endianness_callback,
 214                 (jtag_callback_data_t)in,
 215                 (jtag_callback_data_t)size,
 216                 (jtag_callback_data_t)be,
 217                 (jtag_callback_data_t)1);
 218
 219         jtag_add_runtest(0, TAP_DRPAUSE);
 220
 221 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 222 {
 223                 retval = jtag_execute_queue();
 224                 if (retval != ERROR_OK)
 225                         return retval;
 226
 227                 if (in)
 228                         LOG_DEBUG("in: 0x%8.8x", *(uint32_t *)in);
 229                 else
 230                         LOG_ERROR("BUG: called with in == NULL");
 231 }
 232 #endif
 233
 234         return ERROR_OK;
 235 }
 236
 237 static void arm7tdmi_change_to_arm(struct target *target,
 238                 uint32_t *r0, uint32_t *pc)
 239 {
 240         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 241         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 242
 243         /* save r0 before using it and put system in ARM state
 244          * to allow common handling of ARM and THUMB debugging */
 245
 246         /* fetch STR r0, [r0] */
 247         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0);
 248         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 249         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 250         /* nothing fetched, STR r0, [r0] in Execute (2) */
 251         arm7tdmi_clock_data_in(jtag_info, r0);
 252
 253         /* MOV r0, r15 fetched, STR in Decode */
 254         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0);
 255         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0);
 256         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 257         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 258         /* nothing fetched, STR r0, [r0] in Execute (2) */
 259         arm7tdmi_clock_data_in(jtag_info, pc);
 260
 261         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 262         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0);
 263         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 264         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 265         /* nothing fetched, data for LDR r0, [PC, #0] */
 266         arm7tdmi_clock_out(jtag_info, 0x0, 0);
 267         /* nothing fetched, data from previous cycle is written to register */
 268         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 269
 270         /* fetch BX */
 271         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0);
 272         /* NOP fetched, BX in Decode, MOV in Execute */
 273         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 274         /* NOP fetched, BX in Execute (1) */
 275         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 276
 277         jtag_execute_queue();
 278
 279         /* fix program counter:
 280          * MOV r0, r15 was the 4th instruction (+6)
 281          * reading PC in Thumb state gives address of instruction + 4
 282          */
 283         *pc -= 0xa;
 284 }
 285
 286 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 287  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 288  *
 289  * The solution is to arrange for a large out/in scan in this loop and
 290  * and convert data afterwards.
 291  */
 292 static void arm7tdmi_read_core_regs(struct target *target,
 293                 uint32_t mask, uint32_t *core_regs[16])
 294 {
 295         int i;
 296         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 297         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 298
 299         /* STMIA r0-15, [r0] at debug speed
 300          * register values will start to appear on 4th DCLK
 301          */
 302         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0);
 303
 304         /* fetch NOP, STM in DECODE stage */
 305         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 306         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 307         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 308
 309         for (i = 0; i <= 15; i++) {
 310                 if (mask & (1 << i))
 311                         /* nothing fetched, STM still in EXECUTE (1 + i cycle) */
 312                         arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
 313         }
 314 }
 315
 316 static void arm7tdmi_read_core_regs_target_buffer(struct target *target,
 317                 uint32_t mask, void *buffer, int size)
 318 {
 319         int i;
 320         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 321         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 322         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 323         uint32_t *buf_u32 = buffer;
 324         uint16_t *buf_u16 = buffer;
 325         uint8_t *buf_u8 = buffer;
 326
 327         /* STMIA r0-15, [r0] at debug speed
 328          * register values will start to appear on 4th DCLK
 329          */
 330         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0);
 331
 332         /* fetch NOP, STM in DECODE stage */
 333         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 334         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 335         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 336
 337         for (i = 0; i <= 15; i++) {
 338                 /* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */
 339                 if (mask & (1 << i)) {
 340                         switch (size) {
 341                                 case 4:
 342                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 343                                         break;
 344                                 case 2:
 345                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 346                                         break;
 347                                 case 1:
 348                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 349                                         break;
 350                         }
 351                 }
 352         }
 353 }
 354
 355 static void arm7tdmi_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
 356 {
 357         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 358         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 359
 360         /* MRS r0, cpsr */
 361         arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0);
 362
 363         /* STR r0, [r15] */
 364         arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0);
 365         /* fetch NOP, STR in DECODE stage */
 366         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 367         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 368         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 369         /* nothing fetched, STR still in EXECUTE (2nd cycle) */
 370         arm7tdmi_clock_data_in(jtag_info, xpsr);
 371 }
 372
 373 static void arm7tdmi_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
 374 {
 375         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 376         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 377
 378         LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 379
 380         /* MSR1 fetched */
 381         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0);
 382         /* MSR2 fetched, MSR1 in DECODE */
 383         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0);
 384         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 385         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0);
 386         /* nothing fetched, MSR1 in EXECUTE (2) */
 387         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 388         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 389         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0);
 390         /* nothing fetched, MSR2 in EXECUTE (2) */
 391         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 392         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 393         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 394         /* nothing fetched, MSR3 in EXECUTE (2) */
 395         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 396         /* NOP fetched, MSR4 in EXECUTE (1) */
 397         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 398         /* nothing fetched, MSR4 in EXECUTE (2) */
 399         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 400 }
 401
 402 static void arm7tdmi_write_xpsr_im8(struct target *target,
 403                 uint8_t xpsr_im, int rot, int spsr)
 404 {
 405         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 406         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 407
 408         LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 409
 410         /* MSR fetched */
 411         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0);
 412         /* NOP fetched, MSR in DECODE */
 413         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 414         /* NOP fetched, MSR in EXECUTE (1) */
 415         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 416         /* nothing fetched, MSR in EXECUTE (2) */
 417         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 418 }
 419
 420 static void arm7tdmi_write_core_regs(struct target *target,
 421                 uint32_t mask, uint32_t core_regs[16])
 422 {
 423         int i;
 424         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 425         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 426
 427         /* LDMIA r0-15, [r0] at debug speed
 428         * register values will start to appear on 4th DCLK
 429         */
 430         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0);
 431
 432         /* fetch NOP, LDM in DECODE stage */
 433         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 434         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 435         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 436
 437         for (i = 0; i <= 15; i++) {
 438                 if (mask & (1 << i))
 439                         /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
 440                         arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
 441         }
 442         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 443 }
 444
 445 static void arm7tdmi_load_word_regs(struct target *target, uint32_t mask)
 446 {
 447         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 448         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 449
 450         /* put system-speed load-multiple into the pipeline */
 451         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 452         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
 453         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0);
 454 }
 455
 456 static void arm7tdmi_load_hword_reg(struct target *target, int num)
 457 {
 458         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 459         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 460
 461         /* put system-speed load half-word into the pipeline */
 462         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 463         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
 464         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0);
 465 }
 466
 467 static void arm7tdmi_load_byte_reg(struct target *target, int num)
 468 {
 469         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 470         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 471
 472         /* put system-speed load byte into the pipeline */
 473         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 474         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
 475         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0);
 476 }
 477
 478 static void arm7tdmi_store_word_regs(struct target *target, uint32_t mask)
 479 {
 480         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 481         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 482
 483         /* put system-speed store-multiple into the pipeline */
 484         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 485         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
 486         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0);
 487 }
 488
 489 static void arm7tdmi_store_hword_reg(struct target *target, int num)
 490 {
 491         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 492         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 493
 494         /* put system-speed store half-word into the pipeline */
 495         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 496         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
 497         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0);
 498 }
 499
 500 static void arm7tdmi_store_byte_reg(struct target *target, int num)
 501 {
 502         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 503         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 504
 505         /* put system-speed store byte into the pipeline */
 506         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 507         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
 508         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0);
 509 }
 510
 511 static void arm7tdmi_write_pc(struct target *target, uint32_t pc)
 512 {
 513         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 514         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 515
 516         /* LDMIA r0-15, [r0] at debug speed
 517          * register values will start to appear on 4th DCLK
 518          */
 519         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0);
 520         /* fetch NOP, LDM in DECODE stage */
 521         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 522         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 523         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 524         /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
 525         arm7tdmi_clock_out_inner(jtag_info, pc, 0);
 526         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
 527         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 528         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
 529         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 530         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 531         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 532         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 533         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 534 }
 535
 536 static void arm7tdmi_branch_resume(struct target *target)
 537 {
 538         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 539         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 540
 541         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
 542         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
 543 }
 544
 545 static void arm7tdmi_branch_resume_thumb(struct target *target)
 546 {
 547         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 548         struct arm *arm = &arm7_9->arm;
 549         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 550         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 551
 552         LOG_DEBUG("-");
 553
 554         /* LDMIA r0, [r0] at debug speed
 555          * register values will start to appear on 4th DCLK
 556          */
 557         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0);
 558
 559         /* fetch NOP, LDM in DECODE stage */
 560         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 561         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 562         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 563         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 564         arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->pc->value, 0, 32) | 1, 0);
 565         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 566         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 567
 568         /* Branch and eXchange */
 569         arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0);
 570
 571         embeddedice_read_reg(dbg_stat);
 572
 573         /* fetch NOP, BX in DECODE stage */
 574         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 575
 576         /* target is now in Thumb state */
 577         embeddedice_read_reg(dbg_stat);
 578
 579         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 580         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
 581
 582         /* target is now in Thumb state */
 583         embeddedice_read_reg(dbg_stat);
 584
 585         /* load r0 value */
 586         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0);
 587         /* fetch NOP, LDR in Decode */
 588         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 589         /* fetch NOP, LDR in Execute */
 590         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 591         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 592         arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), 0);
 593         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 594         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 595
 596         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 597         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
 598
 599         embeddedice_read_reg(dbg_stat);
 600
 601         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 1);
 602         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), 0);
 603 }
 604
 605 static void arm7tdmi_build_reg_cache(struct target *target)
 606 {
 607         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 608         struct arm *arm = target_to_arm(target);
 609
 610         (*cache_p) = arm_build_reg_cache(target, arm);
 611 }
 612
 613 static void arm7tdmi_free_reg_cache(struct target *target)
 614 {
 615         struct arm *arm = target_to_arm(target);
 616
 617         arm_free_reg_cache(arm);
 618 }
 619
 620 int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
 621 {
 622         arm7tdmi_build_reg_cache(target);
 623         arm_semihosting_init(target);
 624         return ERROR_OK;
 625 }
 626
 627 void arm7tdmi_deinit_target(struct target *target)
 628 {
 629         arm7tdmi_free_reg_cache(target);
 630 }
 631
 632 int arm7tdmi_init_arch_info(struct target *target,
 633                 struct arm7_9_common *arm7_9, struct jtag_tap *tap)
 634 {
 635         /* prepare JTAG information for the new target */
 636         arm7_9->jtag_info.tap = tap;
 637         arm7_9->jtag_info.scann_size = 4;
 638
 639         /* register arch-specific functions */
 640         arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
 641         arm7_9->change_to_arm = arm7tdmi_change_to_arm;
 642         arm7_9->read_core_regs = arm7tdmi_read_core_regs;
 643         arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
 644         arm7_9->read_xpsr = arm7tdmi_read_xpsr;
 645
 646         arm7_9->write_xpsr = arm7tdmi_write_xpsr;
 647         arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
 648         arm7_9->write_core_regs = arm7tdmi_write_core_regs;
 649
 650         arm7_9->load_word_regs = arm7tdmi_load_word_regs;
 651         arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
 652         arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
 653
 654         arm7_9->store_word_regs = arm7tdmi_store_word_regs;
 655         arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
 656         arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
 657
 658         arm7_9->write_pc = arm7tdmi_write_pc;
 659         arm7_9->branch_resume = arm7tdmi_branch_resume;
 660         arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
 661
 662         arm7_9->enable_single_step = arm7_9_enable_eice_step;
 663         arm7_9->disable_single_step = arm7_9_disable_eice_step;
 664
 665         arm7_9->write_memory = arm7_9_write_memory;
 666         arm7_9->bulk_write_memory = arm7_9_bulk_write_memory;
 667
 668         arm7_9->post_debug_entry = NULL;
 669
 670         arm7_9->pre_restore_context = NULL;
 671
 672         /* initialize arch-specific breakpoint handling */
 673         arm7_9->arm_bkpt = 0xdeeedeee;
 674         arm7_9->thumb_bkpt = 0xdeee;
 675
 676         arm7_9->dbgreq_adjust_pc = 2;
 677
 678         arm7_9_init_arch_info(target, arm7_9);
 679
 680         return ERROR_OK;
 681 }
 682
 683 static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp)
 684 {
 685         struct arm7_9_common *arm7_9;
 686
 687         arm7_9 = calloc(1, sizeof(struct arm7_9_common));
 688         arm7tdmi_init_arch_info(target, arm7_9, target->tap);
 689         arm7_9->arm.arch = ARM_ARCH_V4;
 690
 691         return ERROR_OK;
 692 }
 693
 694 /** Holds methods for ARM7TDMI targets. */
 695 struct target_type arm7tdmi_target = {
 696         .name = "arm7tdmi",
 697
 698         .poll = arm7_9_poll,
 699         .arch_state = arm_arch_state,
 700
 701         .target_request_data = arm7_9_target_request_data,
 702
 703         .halt = arm7_9_halt,
 704         .resume = arm7_9_resume,
 705         .step = arm7_9_step,
 706
 707         .assert_reset = arm7_9_assert_reset,
 708         .deassert_reset = arm7_9_deassert_reset,
 709         .soft_reset_halt = arm7_9_soft_reset_halt,
 710
 711         .get_gdb_arch = arm_get_gdb_arch,
 712         .get_gdb_reg_list = arm_get_gdb_reg_list,
 713
 714         .read_memory = arm7_9_read_memory,
 715         .write_memory = arm7_9_write_memory_opt,
 716
 717         .checksum_memory = arm_checksum_memory,
 718         .blank_check_memory = arm_blank_check_memory,
 719
 720         .run_algorithm = armv4_5_run_algorithm,
 721
 722         .add_breakpoint = arm7_9_add_breakpoint,
 723         .remove_breakpoint = arm7_9_remove_breakpoint,
 724         .add_watchpoint = arm7_9_add_watchpoint,
 725         .remove_watchpoint = arm7_9_remove_watchpoint,
 726
 727         .commands  = arm7_9_command_handlers,
 728         .target_create  = arm7tdmi_target_create,
 729         .init_target = arm7tdmi_init_target,
 730         .deinit_target = arm7tdmi_deinit_target,
 731         .examine = arm7_9_examine,
 732         .check_reset = arm7_9_check_reset,
 733 };