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   1 /***************************************************************************\r
   2  *   Copyright (C) 2005 by Dominic Rath                                    *\r
   3  *   Dominic.Rath@gmx.de                                                   *\r
   4  *                                                                         *\r
   5  *   This program is free software; you can redistribute it and/or modify  *\r
   6  *   it under the terms of the GNU General Public License as published by  *\r
   7  *   the Free Software Foundation; either version 2 of the License, or     *\r
   8  *   (at your option) any later version.                                   *\r
   9  *                                                                         *\r
  10  *   This program is distributed in the hope that it will be useful,       *\r
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
  13  *   GNU General Public License for more details.                          *\r
  14  *                                                                         *\r
  15  *   You should have received a copy of the GNU General Public License     *\r
  16  *   along with this program; if not, write to the                         *\r
  17  *   Free Software Foundation, Inc.,                                       *\r
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
  19  ***************************************************************************/\r
  20 #ifdef HAVE_CONFIG_H\r
  21 #include "config.h"\r
  22 #endif\r
  23 \r
  24 #include "arm7tdmi.h"\r
  25 \r
  26 #include "arm7_9_common.h"\r
  27 #include "register.h"\r
  28 #include "target.h"\r
  29 #include "armv4_5.h"\r
  30 #include "embeddedice.h"\r
  31 #include "etm.h"\r
  32 #include "log.h"\r
  33 #include "jtag.h"\r
  34 #include "arm_jtag.h"\r
  35 \r
  36 #include <stdlib.h>\r
  37 #include <string.h>\r
  38 \r
  39 #if 0\r
  40 #define _DEBUG_INSTRUCTION_EXECUTION_\r
  41 #endif\r
  42 \r
  43 /* cli handling */\r
  44 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);\r
  45 \r
  46 /* forward declarations */\r
  47 int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);\r
  48 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);\r
  49 int arm7tdmi_quit();\r
  50 \r
  51 /* target function declarations */\r
  52 int arm7tdmi_poll(struct target_s *target);\r
  53 int arm7tdmi_halt(target_t *target);\r
  54                 \r
  55 target_type_t arm7tdmi_target =\r
  56 {\r
  57         .name = "arm7tdmi",\r
  58 \r
  59         .poll = arm7_9_poll,\r
  60         .arch_state = armv4_5_arch_state,\r
  61 \r
  62         .target_request_data = arm7_9_target_request_data,\r
  63 \r
  64         .halt = arm7_9_halt,\r
  65         .resume = arm7_9_resume,\r
  66         .step = arm7_9_step,\r
  67 \r
  68         .assert_reset = arm7_9_assert_reset,\r
  69         .deassert_reset = arm7_9_deassert_reset,\r
  70         .soft_reset_halt = arm7_9_soft_reset_halt,\r
  71         .prepare_reset_halt = arm7_9_prepare_reset_halt,\r
  72 \r
  73         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,\r
  74         \r
  75         .read_memory = arm7_9_read_memory,\r
  76         .write_memory = arm7_9_write_memory,\r
  77         .bulk_write_memory = arm7_9_bulk_write_memory,\r
  78         .checksum_memory = arm7_9_checksum_memory,\r
  79         \r
  80         .run_algorithm = armv4_5_run_algorithm,\r
  81         \r
  82         .add_breakpoint = arm7_9_add_breakpoint,\r
  83         .remove_breakpoint = arm7_9_remove_breakpoint,\r
  84         .add_watchpoint = arm7_9_add_watchpoint,\r
  85         .remove_watchpoint = arm7_9_remove_watchpoint,\r
  86 \r
  87         .register_commands = arm7tdmi_register_commands,\r
  88         .target_command = arm7tdmi_target_command,\r
  89         .init_target = arm7tdmi_init_target,\r
  90         .quit = arm7tdmi_quit\r
  91 };\r
  92 \r
  93 int arm7tdmi_examine_debug_reason(target_t *target)\r
  94 {\r
  95         /* get pointers to arch-specific information */\r
  96         armv4_5_common_t *armv4_5 = target->arch_info;\r
  97         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
  98         \r
  99         /* only check the debug reason if we don't know it already */\r
 100         if ((target->debug_reason != DBG_REASON_DBGRQ)\r
 101                         && (target->debug_reason != DBG_REASON_SINGLESTEP))\r
 102         {\r
 103                 scan_field_t fields[2];\r
 104                 u8 databus[4];\r
 105                 u8 breakpoint;\r
 106                 \r
 107                 jtag_add_end_state(TAP_PD);\r
 108 \r
 109                 fields[0].device = arm7_9->jtag_info.chain_pos;\r
 110                 fields[0].num_bits = 1;\r
 111                 fields[0].out_value = NULL;\r
 112                 fields[0].out_mask = NULL;\r
 113                 fields[0].in_value = &breakpoint;\r
 114                 fields[0].in_check_value = NULL;\r
 115                 fields[0].in_check_mask = NULL;\r
 116                 fields[0].in_handler = NULL;\r
 117                 fields[0].in_handler_priv = NULL;\r
 118                 \r
 119                 fields[1].device = arm7_9->jtag_info.chain_pos;\r
 120                 fields[1].num_bits = 32;\r
 121                 fields[1].out_value = NULL;\r
 122                 fields[1].out_mask = NULL;\r
 123                 fields[1].in_value = databus;\r
 124                 fields[1].in_check_value = NULL;\r
 125                 fields[1].in_check_mask = NULL;\r
 126                 fields[1].in_handler = NULL;\r
 127                 fields[1].in_handler_priv = NULL;\r
 128                 \r
 129                 arm_jtag_scann(&arm7_9->jtag_info, 0x1);\r
 130                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);\r
 131 \r
 132                 jtag_add_dr_scan(2, fields, TAP_PD);\r
 133                 jtag_execute_queue();\r
 134                 \r
 135                 fields[0].in_value = NULL;\r
 136                 fields[0].out_value = &breakpoint;\r
 137                 fields[1].in_value = NULL;\r
 138                 fields[1].out_value = databus;\r
 139                 \r
 140                 jtag_add_dr_scan(2, fields, TAP_PD);\r
 141 \r
 142                 if (breakpoint & 1)\r
 143                         target->debug_reason = DBG_REASON_WATCHPOINT; \r
 144                 else\r
 145                         target->debug_reason = DBG_REASON_BREAKPOINT; \r
 146         }\r
 147 \r
 148         return ERROR_OK;\r
 149 }\r
 150 \r
 151 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */\r
 152 int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *in, int breakpoint)\r
 153 {\r
 154         scan_field_t fields[2];\r
 155         u8 out_buf[4];\r
 156         u8 breakpoint_buf;\r
 157         \r
 158         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));\r
 159         buf_set_u32(&breakpoint_buf, 0, 1, breakpoint);\r
 160 \r
 161         jtag_add_end_state(TAP_PD);\r
 162         arm_jtag_scann(jtag_info, 0x1);\r
 163         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
 164         \r
 165         fields[0].device = jtag_info->chain_pos;\r
 166         fields[0].num_bits = 1;\r
 167         fields[0].out_value = &breakpoint_buf;\r
 168         fields[0].out_mask = NULL;\r
 169         fields[0].in_value = NULL;\r
 170         fields[0].in_check_value = NULL;\r
 171         fields[0].in_check_mask = NULL;\r
 172         fields[0].in_handler = NULL;\r
 173         fields[0].in_handler_priv = NULL;\r
 174                 \r
 175         fields[1].device = jtag_info->chain_pos;\r
 176         fields[1].num_bits = 32;\r
 177         fields[1].out_value = out_buf;\r
 178         fields[1].out_mask = NULL;\r
 179         fields[1].in_value = NULL;\r
 180         if (in)\r
 181         {\r
 182                 fields[1].in_handler = arm_jtag_buf_to_u32_flip;\r
 183                 fields[1].in_handler_priv = in;\r
 184         }\r
 185         else\r
 186         {\r
 187                 fields[1].in_handler = NULL;\r
 188                 fields[1].in_handler_priv = NULL;\r
 189         }\r
 190         fields[1].in_check_value = NULL;\r
 191         fields[1].in_check_mask = NULL;\r
 192 \r
 193         jtag_add_dr_scan(2, fields, -1);\r
 194 \r
 195         jtag_add_runtest(0, -1);\r
 196         \r
 197 #ifdef _DEBUG_INSTRUCTION_EXECUTION_\r
 198 {\r
 199                 jtag_execute_queue();\r
 200                 \r
 201                 if (in)\r
 202                 {\r
 203                         DEBUG("out: 0x%8.8x, in: 0x%8.8x", out, *in);\r
 204                 }\r
 205                 else\r
 206                         DEBUG("out: 0x%8.8x", out);\r
 207 }\r
 208 #endif\r
 209 \r
 210         return ERROR_OK;\r
 211 }\r
 212 \r
 213 /* clock the target, reading the databus */\r
 214 int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)\r
 215 {\r
 216         scan_field_t fields[2];\r
 217 \r
 218         jtag_add_end_state(TAP_PD);\r
 219         arm_jtag_scann(jtag_info, 0x1);\r
 220         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
 221         \r
 222         fields[0].device = jtag_info->chain_pos;\r
 223         fields[0].num_bits = 1;\r
 224         fields[0].out_value = NULL;\r
 225         fields[0].out_mask = NULL;\r
 226         fields[0].in_value = NULL;\r
 227         fields[0].in_check_value = NULL;\r
 228         fields[0].in_check_mask = NULL;\r
 229         fields[0].in_handler = NULL;\r
 230         fields[0].in_handler_priv = NULL;\r
 231                 \r
 232         fields[1].device = jtag_info->chain_pos;\r
 233         fields[1].num_bits = 32;\r
 234         fields[1].out_value = NULL;\r
 235         fields[1].out_mask = NULL;\r
 236         fields[1].in_value = NULL;\r
 237         fields[1].in_handler = arm_jtag_buf_to_u32_flip;\r
 238         fields[1].in_handler_priv = in;\r
 239         fields[1].in_check_value = NULL;\r
 240         fields[1].in_check_mask = NULL;\r
 241 \r
 242         jtag_add_dr_scan(2, fields, -1);\r
 243 \r
 244         jtag_add_runtest(0, -1);\r
 245         \r
 246 #ifdef _DEBUG_INSTRUCTION_EXECUTION_\r
 247 {\r
 248                 jtag_execute_queue();\r
 249                         \r
 250                 if (in)\r
 251                 {\r
 252                         DEBUG("in: 0x%8.8x", *in);\r
 253                 }\r
 254                 else\r
 255                 {\r
 256                         ERROR("BUG: called with in == NULL");\r
 257                 }\r
 258 }\r
 259 #endif\r
 260 \r
 261         return ERROR_OK;\r
 262 }\r
 263 \r
 264 /* clock the target, and read the databus\r
 265  * the *in pointer points to a buffer where elements of 'size' bytes\r
 266  * are stored in big (be==1) or little (be==0) endianness\r
 267  */ \r
 268 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)\r
 269 {\r
 270         scan_field_t fields[2];\r
 271 \r
 272         jtag_add_end_state(TAP_PD);\r
 273         arm_jtag_scann(jtag_info, 0x1);\r
 274         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
 275         \r
 276         fields[0].device = jtag_info->chain_pos;\r
 277         fields[0].num_bits = 1;\r
 278         fields[0].out_value = NULL;\r
 279         fields[0].out_mask = NULL;\r
 280         fields[0].in_value = NULL;\r
 281         fields[0].in_check_value = NULL;\r
 282         fields[0].in_check_mask = NULL;\r
 283         fields[0].in_handler = NULL;\r
 284         fields[0].in_handler_priv = NULL;\r
 285                 \r
 286         fields[1].device = jtag_info->chain_pos;\r
 287         fields[1].num_bits = 32;\r
 288         fields[1].out_value = NULL;\r
 289         fields[1].out_mask = NULL;\r
 290         fields[1].in_value = NULL;\r
 291         switch (size)\r
 292         {\r
 293                 case 4:\r
 294                         fields[1].in_handler = (be) ? arm_jtag_buf_to_be32_flip : arm_jtag_buf_to_le32_flip;\r
 295                         break;\r
 296                 case 2:\r
 297                         fields[1].in_handler = (be) ? arm_jtag_buf_to_be16_flip : arm_jtag_buf_to_le16_flip;\r
 298                         break;\r
 299                 case 1:\r
 300                         fields[1].in_handler = arm_jtag_buf_to_8_flip;\r
 301                         break;\r
 302         }\r
 303         fields[1].in_handler_priv = in;\r
 304         fields[1].in_check_value = NULL;\r
 305         fields[1].in_check_mask = NULL;\r
 306 \r
 307         jtag_add_dr_scan(2, fields, -1);\r
 308 \r
 309         jtag_add_runtest(0, -1);\r
 310         \r
 311 #ifdef _DEBUG_INSTRUCTION_EXECUTION_\r
 312 {\r
 313                 jtag_execute_queue();\r
 314                         \r
 315                 if (in)\r
 316                 {\r
 317                         DEBUG("in: 0x%8.8x", *in);\r
 318                 }\r
 319                 else\r
 320                 {\r
 321                         ERROR("BUG: called with in == NULL");\r
 322                 }\r
 323 }\r
 324 #endif\r
 325 \r
 326         return ERROR_OK;\r
 327 }\r
 328 \r
 329 void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)\r
 330 {\r
 331         /* get pointers to arch-specific information */\r
 332         armv4_5_common_t *armv4_5 = target->arch_info;\r
 333         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 334         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 335         \r
 336         /* save r0 before using it and put system in ARM state \r
 337          * to allow common handling of ARM and THUMB debugging */\r
 338         \r
 339         /* fetch STR r0, [r0] */\r
 340         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);\r
 341         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 342         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 343         /* nothing fetched, STR r0, [r0] in Execute (2) */\r
 344         arm7tdmi_clock_data_in(jtag_info, r0);\r
 345 \r
 346         /* MOV r0, r15 fetched, STR in Decode */        \r
 347         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);\r
 348         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);\r
 349         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 350         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 351         /* nothing fetched, STR r0, [r0] in Execute (2) */\r
 352         arm7tdmi_clock_data_in(jtag_info, pc);\r
 353 \r
 354         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */\r
 355         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);\r
 356         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 357         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 358         /* nothing fetched, data for LDR r0, [PC, #0] */\r
 359         arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);\r
 360         /* nothing fetched, data from previous cycle is written to register */\r
 361         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 362         \r
 363         /* fetch BX */\r
 364         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);\r
 365         /* NOP fetched, BX in Decode, MOV in Execute */\r
 366         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 367         /* NOP fetched, BX in Execute (1) */\r
 368         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 369         \r
 370         jtag_execute_queue();\r
 371         \r
 372         /* fix program counter:\r
 373          * MOV r0, r15 was the 4th instruction (+6)\r
 374          * reading PC in Thumb state gives address of instruction + 4\r
 375          */\r
 376         *pc -= 0xa;\r
 377         \r
 378 }\r
 379 \r
 380 void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])\r
 381 {\r
 382         int i;\r
 383         /* get pointers to arch-specific information */\r
 384         armv4_5_common_t *armv4_5 = target->arch_info;\r
 385         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 386         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 387                 \r
 388         /* STMIA r0-15, [r0] at debug speed\r
 389          * register values will start to appear on 4th DCLK\r
 390          */\r
 391         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);\r
 392 \r
 393         /* fetch NOP, STM in DECODE stage */\r
 394         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 395         /* fetch NOP, STM in EXECUTE stage (1st cycle) */\r
 396         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 397 \r
 398         for (i = 0; i <= 15; i++)\r
 399         {\r
 400                 if (mask & (1 << i))\r
 401                         /* nothing fetched, STM still in EXECUTE (1+i cycle) */\r
 402                         arm7tdmi_clock_data_in(jtag_info, core_regs[i]);\r
 403         }\r
 404 \r
 405 }\r
 406 \r
 407 void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)\r
 408 {\r
 409         int i;\r
 410         /* get pointers to arch-specific information */\r
 411         armv4_5_common_t *armv4_5 = target->arch_info;\r
 412         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 413         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 414         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;\r
 415         u32 *buf_u32 = buffer;\r
 416         u16 *buf_u16 = buffer;\r
 417         u8 *buf_u8 = buffer;\r
 418                 \r
 419         /* STMIA r0-15, [r0] at debug speed\r
 420          * register values will start to appear on 4th DCLK\r
 421          */\r
 422         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);\r
 423 \r
 424         /* fetch NOP, STM in DECODE stage */\r
 425         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 426         /* fetch NOP, STM in EXECUTE stage (1st cycle) */\r
 427         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 428 \r
 429         for (i = 0; i <= 15; i++)\r
 430         {\r
 431                 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */\r
 432                 if (mask & (1 << i))\r
 433                 {\r
 434                         switch (size)\r
 435                         {\r
 436                                 case 4:\r
 437                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);\r
 438                                         break;\r
 439                                 case 2:\r
 440                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);\r
 441                                         break;\r
 442                                 case 1:\r
 443                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);\r
 444                                         break;\r
 445                         }\r
 446                 }\r
 447         }\r
 448         \r
 449 }\r
 450 \r
 451 void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)\r
 452 {\r
 453         /* get pointers to arch-specific information */\r
 454         armv4_5_common_t *armv4_5 = target->arch_info;\r
 455         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 456         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 457                 \r
 458         /* MRS r0, cpsr */\r
 459         arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);\r
 460         \r
 461         /* STR r0, [r15] */\r
 462         arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);\r
 463         /* fetch NOP, STR in DECODE stage */\r
 464         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 465         /* fetch NOP, STR in EXECUTE stage (1st cycle) */\r
 466         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 467         /* nothing fetched, STR still in EXECUTE (2nd cycle) */\r
 468         arm7tdmi_clock_data_in(jtag_info, xpsr);\r
 469 \r
 470 }\r
 471 \r
 472 void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)\r
 473 {\r
 474         /* get pointers to arch-specific information */\r
 475         armv4_5_common_t *armv4_5 = target->arch_info;\r
 476         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 477         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 478                 \r
 479         DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);\r
 480 \r
 481         /* MSR1 fetched */\r
 482         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);\r
 483         /* MSR2 fetched, MSR1 in DECODE */\r
 484         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), NULL, 0);\r
 485         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */\r
 486         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), NULL, 0);\r
 487         /* nothing fetched, MSR1 in EXECUTE (2) */\r
 488         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 489         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */\r
 490         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), NULL, 0);\r
 491         /* nothing fetched, MSR2 in EXECUTE (2) */\r
 492         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 493         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */\r
 494         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 495         /* nothing fetched, MSR3 in EXECUTE (2) */\r
 496         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 497         /* NOP fetched, MSR4 in EXECUTE (1) */\r
 498         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 499         /* nothing fetched, MSR4 in EXECUTE (2) */\r
 500         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 501 }\r
 502 \r
 503 void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)\r
 504 {\r
 505         /* get pointers to arch-specific information */\r
 506         armv4_5_common_t *armv4_5 = target->arch_info;\r
 507         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 508         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 509                 \r
 510         DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);\r
 511         \r
 512         /* MSR fetched */\r
 513         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);\r
 514         /* NOP fetched, MSR in DECODE */\r
 515         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 516         /* NOP fetched, MSR in EXECUTE (1) */\r
 517         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 518         /* nothing fetched, MSR in EXECUTE (2) */\r
 519         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 520         \r
 521 }\r
 522 \r
 523 void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])\r
 524 {\r
 525         int i;\r
 526         /* get pointers to arch-specific information */\r
 527         armv4_5_common_t *armv4_5 = target->arch_info;\r
 528         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 529         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 530                 \r
 531         /* LDMIA r0-15, [r0] at debug speed\r
 532         * register values will start to appear on 4th DCLK\r
 533         */\r
 534         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0);\r
 535 \r
 536         /* fetch NOP, LDM in DECODE stage */\r
 537         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 538         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */\r
 539         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 540 \r
 541         for (i = 0; i <= 15; i++)\r
 542         {\r
 543                 if (mask & (1 << i))\r
 544                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */\r
 545                         arm7tdmi_clock_out(jtag_info, core_regs[i], NULL, 0);\r
 546         }\r
 547         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 548         \r
 549 }\r
 550 \r
 551 void arm7tdmi_load_word_regs(target_t *target, u32 mask)\r
 552 {\r
 553         /* get pointers to arch-specific information */\r
 554         armv4_5_common_t *armv4_5 = target->arch_info;\r
 555         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 556         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 557 \r
 558         /* put system-speed load-multiple into the pipeline */\r
 559         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 560         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);\r
 561         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);\r
 562 \r
 563 }\r
 564 \r
 565 void arm7tdmi_load_hword_reg(target_t *target, int num)\r
 566 {\r
 567         /* get pointers to arch-specific information */\r
 568         armv4_5_common_t *armv4_5 = target->arch_info;\r
 569         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 570         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 571         \r
 572         /* put system-speed load half-word into the pipeline */\r
 573         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 574         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);\r
 575         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);\r
 576 \r
 577 }\r
 578 \r
 579 void arm7tdmi_load_byte_reg(target_t *target, int num)\r
 580 {\r
 581         /* get pointers to arch-specific information */\r
 582         armv4_5_common_t *armv4_5 = target->arch_info;\r
 583         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 584         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 585 \r
 586         /* put system-speed load byte into the pipeline */\r
 587         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 588         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);\r
 589         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);\r
 590 \r
 591 }\r
 592 \r
 593 void arm7tdmi_store_word_regs(target_t *target, u32 mask)\r
 594 {\r
 595         /* get pointers to arch-specific information */\r
 596         armv4_5_common_t *armv4_5 = target->arch_info;\r
 597         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 598         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 599 \r
 600         /* put system-speed store-multiple into the pipeline */\r
 601         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 602         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);\r
 603         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);\r
 604         \r
 605 }\r
 606 \r
 607 void arm7tdmi_store_hword_reg(target_t *target, int num)\r
 608 {\r
 609         /* get pointers to arch-specific information */\r
 610         armv4_5_common_t *armv4_5 = target->arch_info;\r
 611         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 612         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 613 \r
 614         /* put system-speed store half-word into the pipeline */\r
 615         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 616         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);\r
 617         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);\r
 618 \r
 619 }\r
 620 \r
 621 void arm7tdmi_store_byte_reg(target_t *target, int num)\r
 622 {\r
 623         /* get pointers to arch-specific information */\r
 624         armv4_5_common_t *armv4_5 = target->arch_info;\r
 625         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 626         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 627 \r
 628         /* put system-speed store byte into the pipeline */\r
 629         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 630         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);\r
 631         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);\r
 632 \r
 633 }\r
 634 \r
 635 void arm7tdmi_write_pc(target_t *target, u32 pc)\r
 636 {\r
 637         /* get pointers to arch-specific information */\r
 638         armv4_5_common_t *armv4_5 = target->arch_info;\r
 639         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 640         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 641         \r
 642         /* LDMIA r0-15, [r0] at debug speed\r
 643          * register values will start to appear on 4th DCLK\r
 644          */\r
 645         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0);\r
 646         /* fetch NOP, LDM in DECODE stage */\r
 647         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 648         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */\r
 649         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 650         /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */\r
 651         arm7tdmi_clock_out(jtag_info, pc, NULL, 0);\r
 652         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */\r
 653         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 654         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */\r
 655         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 656         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */\r
 657         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 658         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */\r
 659         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 660 }\r
 661 \r
 662 void arm7tdmi_branch_resume(target_t *target)\r
 663 {\r
 664         /* get pointers to arch-specific information */\r
 665         armv4_5_common_t *armv4_5 = target->arch_info;\r
 666         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 667         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 668         \r
 669         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);\r
 670         arm7tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffa, 0), NULL, 0);\r
 671 \r
 672 }\r
 673 \r
 674 void arm7tdmi_branch_resume_thumb(target_t *target)\r
 675 {\r
 676         DEBUG("-");\r
 677         \r
 678         /* get pointers to arch-specific information */\r
 679         armv4_5_common_t *armv4_5 = target->arch_info;\r
 680         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 681         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 682         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];\r
 683 \r
 684         /* LDMIA r0, [r0] at debug speed\r
 685          * register values will start to appear on 4th DCLK\r
 686          */\r
 687         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL, 0);\r
 688 \r
 689         /* fetch NOP, LDM in DECODE stage */\r
 690         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 691         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */\r
 692         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 693         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */\r
 694         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);\r
 695         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */\r
 696         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 697 \r
 698         /* Branch and eXchange */\r
 699         arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);\r
 700         \r
 701         embeddedice_read_reg(dbg_stat);\r
 702         \r
 703         /* fetch NOP, BX in DECODE stage */\r
 704         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 705         \r
 706         /* target is now in Thumb state */\r
 707         embeddedice_read_reg(dbg_stat);\r
 708         \r
 709         /* fetch NOP, BX in EXECUTE stage (1st cycle) */\r
 710         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);\r
 711 \r
 712         /* target is now in Thumb state */\r
 713         embeddedice_read_reg(dbg_stat);\r
 714 \r
 715         /* load r0 value */\r
 716         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);\r
 717         /* fetch NOP, LDR in Decode */\r
 718         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 719         /* fetch NOP, LDR in Execute */\r
 720         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 721         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */\r
 722         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);\r
 723         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */\r
 724         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 725         \r
 726         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 727         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);\r
 728 \r
 729         embeddedice_read_reg(dbg_stat);\r
 730         \r
 731         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);\r
 732         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);\r
 733 \r
 734 }\r
 735                 \r
 736 void arm7tdmi_build_reg_cache(target_t *target)\r
 737 {\r
 738         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);\r
 739         /* get pointers to arch-specific information */\r
 740         armv4_5_common_t *armv4_5 = target->arch_info;\r
 741         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 742         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 743 \r
 744         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);\r
 745         armv4_5->core_cache = (*cache_p);\r
 746         \r
 747         (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);\r
 748         arm7_9->eice_cache = (*cache_p)->next;\r
 749         \r
 750         if (arm7_9->etm_ctx)\r
 751         {\r
 752                 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);\r
 753                 arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;\r
 754         }\r
 755 }\r
 756 \r
 757 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)\r
 758 {\r
 759         \r
 760         arm7tdmi_build_reg_cache(target);\r
 761         \r
 762         return ERROR_OK;\r
 763         \r
 764 }\r
 765 \r
 766 int arm7tdmi_quit()\r
 767 {\r
 768         \r
 769         return ERROR_OK;\r
 770 }\r
 771 \r
 772 int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, char *variant)\r
 773 {\r
 774         armv4_5_common_t *armv4_5;\r
 775         arm7_9_common_t *arm7_9;\r
 776         \r
 777         arm7_9 = &arm7tdmi->arm7_9_common;\r
 778         armv4_5 = &arm7_9->armv4_5_common;\r
 779         \r
 780         /* prepare JTAG information for the new target */\r
 781         arm7_9->jtag_info.chain_pos = chain_pos;\r
 782         arm7_9->jtag_info.scann_size = 4;\r
 783         \r
 784         /* register arch-specific functions */\r
 785         arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;\r
 786         arm7_9->change_to_arm = arm7tdmi_change_to_arm;\r
 787         arm7_9->read_core_regs = arm7tdmi_read_core_regs;\r
 788         arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;\r
 789         arm7_9->read_xpsr = arm7tdmi_read_xpsr;\r
 790         \r
 791         arm7_9->write_xpsr = arm7tdmi_write_xpsr;\r
 792         arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;\r
 793         arm7_9->write_core_regs = arm7tdmi_write_core_regs;\r
 794         \r
 795         arm7_9->load_word_regs = arm7tdmi_load_word_regs;\r
 796         arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;\r
 797         arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;\r
 798         \r
 799         arm7_9->store_word_regs = arm7tdmi_store_word_regs;\r
 800         arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;\r
 801         arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;\r
 802         \r
 803         arm7_9->write_pc = arm7tdmi_write_pc;\r
 804         arm7_9->branch_resume = arm7tdmi_branch_resume;\r
 805         arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;\r
 806         \r
 807         arm7_9->enable_single_step = arm7_9_enable_eice_step;\r
 808         arm7_9->disable_single_step = arm7_9_disable_eice_step;\r
 809                 \r
 810         arm7_9->pre_debug_entry = NULL;\r
 811         arm7_9->post_debug_entry = NULL;\r
 812         \r
 813         arm7_9->pre_restore_context = NULL;\r
 814         arm7_9->post_restore_context = NULL;\r
 815         \r
 816         /* initialize arch-specific breakpoint handling */\r
 817         arm7_9->arm_bkpt = 0xdeeedeee;\r
 818         arm7_9->thumb_bkpt = 0xdeee;\r
 819         \r
 820         arm7_9->sw_bkpts_use_wp = 1;\r
 821         arm7_9->sw_bkpts_enabled = 0;\r
 822         arm7_9->dbgreq_adjust_pc = 2;\r
 823         arm7_9->arch_info = arm7tdmi;\r
 824 \r
 825         arm7tdmi->arch_info = NULL;\r
 826         arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;\r
 827         \r
 828         if (variant)\r
 829         {\r
 830                 arm7tdmi->variant = strdup(variant);\r
 831         }\r
 832         else\r
 833         {\r
 834                 arm7tdmi->variant = strdup("");\r
 835         }\r
 836         \r
 837         arm7_9_init_arch_info(target, arm7_9);\r
 838 \r
 839         return ERROR_OK;\r
 840 }\r
 841 \r
 842 /* target arm7tdmi <endianess> <startup_mode> <chain_pos> <variant> */\r
 843 int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)\r
 844 {\r
 845         int chain_pos;\r
 846         char *variant = NULL;\r
 847         arm7tdmi_common_t *arm7tdmi = malloc(sizeof(arm7tdmi_common_t));\r
 848 \r
 849         if (argc < 4)\r
 850         {\r
 851                 ERROR("'target arm7tdmi' requires at least one additional argument");\r
 852                 exit(-1);\r
 853         }\r
 854         \r
 855         chain_pos = strtoul(args[3], NULL, 0);\r
 856         \r
 857         if (argc >= 5)\r
 858                 variant = args[4];\r
 859         \r
 860         arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);\r
 861         \r
 862         return ERROR_OK;\r
 863 }\r
 864 \r
 865 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)\r
 866 {\r
 867         int retval;\r
 868         \r
 869         retval = arm7_9_register_commands(cmd_ctx);\r
 870         \r
 871         return ERROR_OK;\r
 872 \r
 873 }\r
 874 \r