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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm7tdmi.h"
  25
  26 #include "arm7_9_common.h"
  27 #include "register.h"
  28 #include "target.h"
  29 #include "armv4_5.h"
  30 #include "embeddedice.h"
  31 #include "etm.h"
  32 #include "log.h"
  33 #include "jtag.h"
  34 #include "arm_jtag.h"
  35
  36 #include <stdlib.h>
  37 #include <string.h>
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 /* cli handling */
  44 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
  45
  46 /* forward declarations */
  47 int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  48 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  49 int arm7tdmi_quit();
  50
  51 /* target function declarations */
  52 int arm7tdmi_poll(struct target_s *target);
  53 int arm7tdmi_halt(target_t *target);
  54
  55 target_type_t arm7tdmi_target =
  56 {
  57         .name = "arm7tdmi",
  58
  59         .poll = arm7_9_poll,
  60         .arch_state = armv4_5_arch_state,
  61
  62         .target_request_data = arm7_9_target_request_data,
  63
  64         .halt = arm7_9_halt,
  65         .resume = arm7_9_resume,
  66         .step = arm7_9_step,
  67
  68         .assert_reset = arm7_9_assert_reset,
  69         .deassert_reset = arm7_9_deassert_reset,
  70         .soft_reset_halt = arm7_9_soft_reset_halt,
  71
  72         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  73
  74         .read_memory = arm7_9_read_memory,
  75         .write_memory = arm7_9_write_memory,
  76         .bulk_write_memory = arm7_9_bulk_write_memory,
  77         .checksum_memory = arm7_9_checksum_memory,
  78
  79         .run_algorithm = armv4_5_run_algorithm,
  80
  81         .add_breakpoint = arm7_9_add_breakpoint,
  82         .remove_breakpoint = arm7_9_remove_breakpoint,
  83         .add_watchpoint = arm7_9_add_watchpoint,
  84         .remove_watchpoint = arm7_9_remove_watchpoint,
  85
  86         .register_commands = arm7tdmi_register_commands,
  87         .target_command = arm7tdmi_target_command,
  88         .init_target = arm7tdmi_init_target,
  89         .examine = arm7tdmi_examine,
  90         .quit = arm7tdmi_quit
  91 };
  92
  93 int arm7tdmi_examine_debug_reason(target_t *target)
  94 {
  95         /* get pointers to arch-specific information */
  96         armv4_5_common_t *armv4_5 = target->arch_info;
  97         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  98
  99         /* only check the debug reason if we don't know it already */
 100         if ((target->debug_reason != DBG_REASON_DBGRQ)
 101                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 102         {
 103                 scan_field_t fields[2];
 104                 u8 databus[4];
 105                 u8 breakpoint;
 106
 107                 jtag_add_end_state(TAP_PD);
 108
 109                 fields[0].device = arm7_9->jtag_info.chain_pos;
 110                 fields[0].num_bits = 1;
 111                 fields[0].out_value = NULL;
 112                 fields[0].out_mask = NULL;
 113                 fields[0].in_value = &breakpoint;
 114                 fields[0].in_check_value = NULL;
 115                 fields[0].in_check_mask = NULL;
 116                 fields[0].in_handler = NULL;
 117                 fields[0].in_handler_priv = NULL;
 118
 119                 fields[1].device = arm7_9->jtag_info.chain_pos;
 120                 fields[1].num_bits = 32;
 121                 fields[1].out_value = NULL;
 122                 fields[1].out_mask = NULL;
 123                 fields[1].in_value = databus;
 124                 fields[1].in_check_value = NULL;
 125                 fields[1].in_check_mask = NULL;
 126                 fields[1].in_handler = NULL;
 127                 fields[1].in_handler_priv = NULL;
 128
 129                 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
 130                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 131
 132                 jtag_add_dr_scan(2, fields, TAP_PD);
 133                 jtag_execute_queue();
 134
 135                 fields[0].in_value = NULL;
 136                 fields[0].out_value = &breakpoint;
 137                 fields[1].in_value = NULL;
 138                 fields[1].out_value = databus;
 139
 140                 jtag_add_dr_scan(2, fields, TAP_PD);
 141
 142                 if (breakpoint & 1)
 143                         target->debug_reason = DBG_REASON_WATCHPOINT;
 144                 else
 145                         target->debug_reason = DBG_REASON_BREAKPOINT;
 146         }
 147
 148         return ERROR_OK;
 149 }
 150
 151 static int arm7tdmi_num_bits[]={1, 32};
 152 static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
 153 {
 154         u32 values[2]={breakpoint, flip_u32(out, 32)};
 155
 156         jtag_add_dr_out(jtag_info->chain_pos,
 157                         2,
 158                         arm7tdmi_num_bits,
 159                         values,
 160                         -1);
 161
 162         jtag_add_runtest(0, -1);
 163
 164         return ERROR_OK;
 165 }
 166
 167 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
 168 static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
 169 {
 170         jtag_add_end_state(TAP_PD);
 171         arm_jtag_scann(jtag_info, 0x1);
 172         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 173
 174         return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
 175 }
 176
 177 /* clock the target, reading the databus */
 178 int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 179 {
 180         scan_field_t fields[2];
 181
 182         jtag_add_end_state(TAP_PD);
 183         arm_jtag_scann(jtag_info, 0x1);
 184         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 185
 186         fields[0].device = jtag_info->chain_pos;
 187         fields[0].num_bits = 1;
 188         fields[0].out_value = NULL;
 189         fields[0].out_mask = NULL;
 190         fields[0].in_value = NULL;
 191         fields[0].in_check_value = NULL;
 192         fields[0].in_check_mask = NULL;
 193         fields[0].in_handler = NULL;
 194         fields[0].in_handler_priv = NULL;
 195
 196         fields[1].device = jtag_info->chain_pos;
 197         fields[1].num_bits = 32;
 198         fields[1].out_value = NULL;
 199         fields[1].out_mask = NULL;
 200         fields[1].in_value = NULL;
 201         fields[1].in_handler = arm_jtag_buf_to_u32_flip;
 202         fields[1].in_handler_priv = in;
 203         fields[1].in_check_value = NULL;
 204         fields[1].in_check_mask = NULL;
 205
 206         jtag_add_dr_scan(2, fields, -1);
 207
 208         jtag_add_runtest(0, -1);
 209
 210 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 211 {
 212                 jtag_execute_queue();
 213
 214                 if (in)
 215                 {
 216                         LOG_DEBUG("in: 0x%8.8x", *in);
 217                 }
 218                 else
 219                 {
 220                         LOG_ERROR("BUG: called with in == NULL");
 221                 }
 222 }
 223 #endif
 224
 225         return ERROR_OK;
 226 }
 227
 228 /* clock the target, and read the databus
 229  * the *in pointer points to a buffer where elements of 'size' bytes
 230  * are stored in big (be==1) or little (be==0) endianness
 231  */
 232 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 233 {
 234         scan_field_t fields[2];
 235
 236         jtag_add_end_state(TAP_PD);
 237         arm_jtag_scann(jtag_info, 0x1);
 238         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 239
 240         fields[0].device = jtag_info->chain_pos;
 241         fields[0].num_bits = 1;
 242         fields[0].out_value = NULL;
 243         fields[0].out_mask = NULL;
 244         fields[0].in_value = NULL;
 245         fields[0].in_check_value = NULL;
 246         fields[0].in_check_mask = NULL;
 247         fields[0].in_handler = NULL;
 248         fields[0].in_handler_priv = NULL;
 249
 250         fields[1].device = jtag_info->chain_pos;
 251         fields[1].num_bits = 32;
 252         fields[1].out_value = NULL;
 253         fields[1].out_mask = NULL;
 254         fields[1].in_value = NULL;
 255         switch (size)
 256         {
 257                 case 4:
 258                         fields[1].in_handler = (be) ? arm_jtag_buf_to_be32_flip : arm_jtag_buf_to_le32_flip;
 259                         break;
 260                 case 2:
 261                         fields[1].in_handler = (be) ? arm_jtag_buf_to_be16_flip : arm_jtag_buf_to_le16_flip;
 262                         break;
 263                 case 1:
 264                         fields[1].in_handler = arm_jtag_buf_to_8_flip;
 265                         break;
 266         }
 267         fields[1].in_handler_priv = in;
 268         fields[1].in_check_value = NULL;
 269         fields[1].in_check_mask = NULL;
 270
 271         jtag_add_dr_scan(2, fields, -1);
 272
 273         jtag_add_runtest(0, -1);
 274
 275 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 276 {
 277                 jtag_execute_queue();
 278
 279                 if (in)
 280                 {
 281                         LOG_DEBUG("in: 0x%8.8x", *in);
 282                 }
 283                 else
 284                 {
 285                         LOG_ERROR("BUG: called with in == NULL");
 286                 }
 287 }
 288 #endif
 289
 290         return ERROR_OK;
 291 }
 292
 293 void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 294 {
 295         /* get pointers to arch-specific information */
 296         armv4_5_common_t *armv4_5 = target->arch_info;
 297         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 298         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 299
 300         /* save r0 before using it and put system in ARM state
 301          * to allow common handling of ARM and THUMB debugging */
 302
 303         /* fetch STR r0, [r0] */
 304         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
 305         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 306         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 307         /* nothing fetched, STR r0, [r0] in Execute (2) */
 308         arm7tdmi_clock_data_in(jtag_info, r0);
 309
 310         /* MOV r0, r15 fetched, STR in Decode */
 311         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
 312         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
 313         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 314         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 315         /* nothing fetched, STR r0, [r0] in Execute (2) */
 316         arm7tdmi_clock_data_in(jtag_info, pc);
 317
 318         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 319         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
 320         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 321         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 322         /* nothing fetched, data for LDR r0, [PC, #0] */
 323         arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
 324         /* nothing fetched, data from previous cycle is written to register */
 325         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 326
 327         /* fetch BX */
 328         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
 329         /* NOP fetched, BX in Decode, MOV in Execute */
 330         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 331         /* NOP fetched, BX in Execute (1) */
 332         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 333
 334         jtag_execute_queue();
 335
 336         /* fix program counter:
 337          * MOV r0, r15 was the 4th instruction (+6)
 338          * reading PC in Thumb state gives address of instruction + 4
 339          */
 340         *pc -= 0xa;
 341
 342 }
 343
 344 void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 345 {
 346         int i;
 347         /* get pointers to arch-specific information */
 348         armv4_5_common_t *armv4_5 = target->arch_info;
 349         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 350         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 351
 352         /* STMIA r0-15, [r0] at debug speed
 353          * register values will start to appear on 4th DCLK
 354          */
 355         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 356
 357         /* fetch NOP, STM in DECODE stage */
 358         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 359         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 360         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 361
 362         for (i = 0; i <= 15; i++)
 363         {
 364                 if (mask & (1 << i))
 365                         /* nothing fetched, STM still in EXECUTE (1+i cycle) */
 366                         arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
 367         }
 368
 369 }
 370
 371 void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 372 {
 373         int i;
 374         /* get pointers to arch-specific information */
 375         armv4_5_common_t *armv4_5 = target->arch_info;
 376         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 377         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 378         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 379         u32 *buf_u32 = buffer;
 380         u16 *buf_u16 = buffer;
 381         u8 *buf_u8 = buffer;
 382
 383         /* STMIA r0-15, [r0] at debug speed
 384          * register values will start to appear on 4th DCLK
 385          */
 386         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 387
 388         /* fetch NOP, STM in DECODE stage */
 389         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 390         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 391         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 392
 393         for (i = 0; i <= 15; i++)
 394         {
 395                 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
 396                 if (mask & (1 << i))
 397                 {
 398                         switch (size)
 399                         {
 400                                 case 4:
 401                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 402                                         break;
 403                                 case 2:
 404                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 405                                         break;
 406                                 case 1:
 407                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 408                                         break;
 409                         }
 410                 }
 411         }
 412
 413 }
 414
 415 void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 416 {
 417         /* get pointers to arch-specific information */
 418         armv4_5_common_t *armv4_5 = target->arch_info;
 419         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 420         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 421
 422         /* MRS r0, cpsr */
 423         arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
 424
 425         /* STR r0, [r15] */
 426         arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
 427         /* fetch NOP, STR in DECODE stage */
 428         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 429         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 430         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 431         /* nothing fetched, STR still in EXECUTE (2nd cycle) */
 432         arm7tdmi_clock_data_in(jtag_info, xpsr);
 433
 434 }
 435
 436 void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 437 {
 438         /* get pointers to arch-specific information */
 439         armv4_5_common_t *armv4_5 = target->arch_info;
 440         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 441         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 442
 443         LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 444
 445         /* MSR1 fetched */
 446         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
 447         /* MSR2 fetched, MSR1 in DECODE */
 448         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), NULL, 0);
 449         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 450         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), NULL, 0);
 451         /* nothing fetched, MSR1 in EXECUTE (2) */
 452         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 453         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 454         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), NULL, 0);
 455         /* nothing fetched, MSR2 in EXECUTE (2) */
 456         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 457         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 458         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 459         /* nothing fetched, MSR3 in EXECUTE (2) */
 460         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 461         /* NOP fetched, MSR4 in EXECUTE (1) */
 462         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 463         /* nothing fetched, MSR4 in EXECUTE (2) */
 464         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 465 }
 466
 467 void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 468 {
 469         /* get pointers to arch-specific information */
 470         armv4_5_common_t *armv4_5 = target->arch_info;
 471         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 472         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 473
 474         LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 475
 476         /* MSR fetched */
 477         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
 478         /* NOP fetched, MSR in DECODE */
 479         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 480         /* NOP fetched, MSR in EXECUTE (1) */
 481         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 482         /* nothing fetched, MSR in EXECUTE (2) */
 483         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 484
 485 }
 486
 487 void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 488 {
 489         int i;
 490         /* get pointers to arch-specific information */
 491         armv4_5_common_t *armv4_5 = target->arch_info;
 492         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 493         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 494
 495         /* LDMIA r0-15, [r0] at debug speed
 496         * register values will start to appear on 4th DCLK
 497         */
 498         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 499
 500         /* fetch NOP, LDM in DECODE stage */
 501         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 502         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 503         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 504
 505         for (i = 0; i <= 15; i++)
 506         {
 507                 if (mask & (1 << i))
 508                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 509                         arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
 510         }
 511         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 512
 513 }
 514
 515 void arm7tdmi_load_word_regs(target_t *target, u32 mask)
 516 {
 517         /* get pointers to arch-specific information */
 518         armv4_5_common_t *armv4_5 = target->arch_info;
 519         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 520         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 521
 522         /* put system-speed load-multiple into the pipeline */
 523         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 524         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 525         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
 526
 527 }
 528
 529 void arm7tdmi_load_hword_reg(target_t *target, int num)
 530 {
 531         /* get pointers to arch-specific information */
 532         armv4_5_common_t *armv4_5 = target->arch_info;
 533         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 534         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 535
 536         /* put system-speed load half-word into the pipeline */
 537         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 538         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 539         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
 540
 541 }
 542
 543 void arm7tdmi_load_byte_reg(target_t *target, int num)
 544 {
 545         /* get pointers to arch-specific information */
 546         armv4_5_common_t *armv4_5 = target->arch_info;
 547         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 548         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 549
 550         /* put system-speed load byte into the pipeline */
 551         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 552         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 553         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
 554
 555 }
 556
 557 void arm7tdmi_store_word_regs(target_t *target, u32 mask)
 558 {
 559         /* get pointers to arch-specific information */
 560         armv4_5_common_t *armv4_5 = target->arch_info;
 561         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 562         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 563
 564         /* put system-speed store-multiple into the pipeline */
 565         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 566         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 567         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
 568
 569 }
 570
 571 void arm7tdmi_store_hword_reg(target_t *target, int num)
 572 {
 573         /* get pointers to arch-specific information */
 574         armv4_5_common_t *armv4_5 = target->arch_info;
 575         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 576         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 577
 578         /* put system-speed store half-word into the pipeline */
 579         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 580         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 581         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
 582
 583 }
 584
 585 void arm7tdmi_store_byte_reg(target_t *target, int num)
 586 {
 587         /* get pointers to arch-specific information */
 588         armv4_5_common_t *armv4_5 = target->arch_info;
 589         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 590         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 591
 592         /* put system-speed store byte into the pipeline */
 593         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 594         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 595         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
 596
 597 }
 598
 599 void arm7tdmi_write_pc(target_t *target, u32 pc)
 600 {
 601         /* get pointers to arch-specific information */
 602         armv4_5_common_t *armv4_5 = target->arch_info;
 603         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 604         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 605
 606         /* LDMIA r0-15, [r0] at debug speed
 607          * register values will start to appear on 4th DCLK
 608          */
 609         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0);
 610         /* fetch NOP, LDM in DECODE stage */
 611         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 612         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 613         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 614         /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
 615         arm7tdmi_clock_out_inner(jtag_info, pc, 0);
 616         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
 617         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 618         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
 619         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 620         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 621         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 622         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 623         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 624 }
 625
 626 void arm7tdmi_branch_resume(target_t *target)
 627 {
 628         /* get pointers to arch-specific information */
 629         armv4_5_common_t *armv4_5 = target->arch_info;
 630         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 631         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 632
 633         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 634         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
 635
 636 }
 637
 638 void arm7tdmi_branch_resume_thumb(target_t *target)
 639 {
 640         LOG_DEBUG("-");
 641
 642         /* get pointers to arch-specific information */
 643         armv4_5_common_t *armv4_5 = target->arch_info;
 644         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 645         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 646         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 647
 648         /* LDMIA r0, [r0] at debug speed
 649          * register values will start to appear on 4th DCLK
 650          */
 651         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL, 0);
 652
 653         /* fetch NOP, LDM in DECODE stage */
 654         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 655         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 656         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 657         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 658         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 659         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 660         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 661
 662         /* Branch and eXchange */
 663         arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
 664
 665         embeddedice_read_reg(dbg_stat);
 666
 667         /* fetch NOP, BX in DECODE stage */
 668         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 669
 670         /* target is now in Thumb state */
 671         embeddedice_read_reg(dbg_stat);
 672
 673         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 674         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 675
 676         /* target is now in Thumb state */
 677         embeddedice_read_reg(dbg_stat);
 678
 679         /* load r0 value */
 680         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
 681         /* fetch NOP, LDR in Decode */
 682         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 683         /* fetch NOP, LDR in Execute */
 684         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 685         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 686         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 687         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 688         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 689
 690         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 691         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 692
 693         embeddedice_read_reg(dbg_stat);
 694
 695         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
 696         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
 697
 698 }
 699
 700 void arm7tdmi_build_reg_cache(target_t *target)
 701 {
 702         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 703         /* get pointers to arch-specific information */
 704         armv4_5_common_t *armv4_5 = target->arch_info;
 705
 706         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 707         armv4_5->core_cache = (*cache_p);
 708 }
 709
 710 int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target)
 711 {
 712         int retval;
 713         armv4_5_common_t *armv4_5 = target->arch_info;
 714         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 715         if (!target->type->examined)
 716         {
 717                 /* get pointers to arch-specific information */
 718                 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 719                 reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
 720                 if (t==NULL)
 721                         return ERROR_FAIL;
 722
 723                 (*cache_p) = t;
 724                 arm7_9->eice_cache = (*cache_p);
 725
 726                 if (arm7_9->etm_ctx)
 727                 {
 728                         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 729                         (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 730                         arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
 731                 }
 732                 target->type->examined = 1;
 733         }
 734         if ((retval=embeddedice_setup(target))!=ERROR_OK)
 735                 return retval;
 736         if ((retval=arm7_9_setup(target))!=ERROR_OK)
 737                 return retval;
 738         if (arm7_9->etm_ctx)
 739         {
 740                 if ((retval=etm_setup(target))!=ERROR_OK)
 741                         return retval;
 742         }
 743         return ERROR_OK;
 744 }
 745
 746 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 747 {
 748
 749         arm7tdmi_build_reg_cache(target);
 750
 751         return ERROR_OK;
 752
 753 }
 754
 755 int arm7tdmi_quit()
 756 {
 757
 758         return ERROR_OK;
 759 }
 760
 761 int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, char *variant)
 762 {
 763         armv4_5_common_t *armv4_5;
 764         arm7_9_common_t *arm7_9;
 765
 766         arm7_9 = &arm7tdmi->arm7_9_common;
 767         armv4_5 = &arm7_9->armv4_5_common;
 768
 769         /* prepare JTAG information for the new target */
 770         arm7_9->jtag_info.chain_pos = chain_pos;
 771         arm7_9->jtag_info.scann_size = 4;
 772
 773         /* register arch-specific functions */
 774         arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
 775         arm7_9->change_to_arm = arm7tdmi_change_to_arm;
 776         arm7_9->read_core_regs = arm7tdmi_read_core_regs;
 777         arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
 778         arm7_9->read_xpsr = arm7tdmi_read_xpsr;
 779
 780         arm7_9->write_xpsr = arm7tdmi_write_xpsr;
 781         arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
 782         arm7_9->write_core_regs = arm7tdmi_write_core_regs;
 783
 784         arm7_9->load_word_regs = arm7tdmi_load_word_regs;
 785         arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
 786         arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
 787
 788         arm7_9->store_word_regs = arm7tdmi_store_word_regs;
 789         arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
 790         arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
 791
 792         arm7_9->write_pc = arm7tdmi_write_pc;
 793         arm7_9->branch_resume = arm7tdmi_branch_resume;
 794         arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
 795
 796         arm7_9->enable_single_step = arm7_9_enable_eice_step;
 797         arm7_9->disable_single_step = arm7_9_disable_eice_step;
 798
 799         arm7_9->pre_debug_entry = NULL;
 800         arm7_9->post_debug_entry = NULL;
 801
 802         arm7_9->pre_restore_context = NULL;
 803         arm7_9->post_restore_context = NULL;
 804
 805         /* initialize arch-specific breakpoint handling */
 806         arm7_9->arm_bkpt = 0xdeeedeee;
 807         arm7_9->thumb_bkpt = 0xdeee;
 808
 809         arm7_9->sw_bkpts_use_wp = 1;
 810         arm7_9->sw_bkpts_enabled = 0;
 811         arm7_9->dbgreq_adjust_pc = 2;
 812         arm7_9->arch_info = arm7tdmi;
 813
 814         arm7tdmi->arch_info = NULL;
 815         arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
 816
 817         if (variant)
 818         {
 819                 arm7tdmi->variant = strdup(variant);
 820         }
 821         else
 822         {
 823                 arm7tdmi->variant = strdup("");
 824         }
 825
 826         arm7_9_init_arch_info(target, arm7_9);
 827
 828         return ERROR_OK;
 829 }
 830
 831 /* target arm7tdmi <endianess> <startup_mode> <chain_pos> <variant> */
 832 int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 833 {
 834         int chain_pos;
 835         char *variant = NULL;
 836         arm7tdmi_common_t *arm7tdmi = malloc(sizeof(arm7tdmi_common_t));
 837         memset(arm7tdmi, 0, sizeof(*arm7tdmi));
 838
 839         if (argc < 4)
 840         {
 841                 LOG_ERROR("'target arm7tdmi' requires at least one additional argument");
 842                 exit(-1);
 843         }
 844
 845         chain_pos = strtoul(args[3], NULL, 0);
 846
 847         if (argc >= 5)
 848                 variant = args[4];
 849
 850         arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);
 851
 852         return ERROR_OK;
 853 }
 854
 855 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
 856 {
 857         int retval;
 858
 859         retval = arm7_9_register_commands(cmd_ctx);
 860
 861         return ERROR_OK;
 862
 863 }
 864