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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                      *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ARM7_9_COMMON_H
  24 #define ARM7_9_COMMON_H
  25
  26 #include "armv4_5.h"
  27 #include "arm_jtag.h"
  28 #include "breakpoints.h"
  29 #include "target.h"
  30
  31 #include "etm.h"
  32
  33 #define ARM7_9_COMMON_MAGIC 0x0a790a79
  34
  35 typedef struct arm7_9_common_s
  36 {
  37         int common_magic;
  38
  39         arm_jtag_t jtag_info;
  40         reg_cache_t *eice_cache;
  41
  42         u32 arm_bkpt;
  43         u16 thumb_bkpt;
  44         int sw_breakpoints_added;
  45         int breakpoint_count;
  46         int wp_available;
  47         int wp0_used;
  48         int wp1_used;
  49         int force_hw_bkpts;
  50         int dbgreq_adjust_pc;
  51         int use_dbgrq;
  52         int need_bypass_before_restart;
  53
  54         etm_context_t *etm_ctx;
  55
  56         int has_single_step;
  57         int has_monitor_mode;
  58         int has_vector_catch;
  59
  60         int debug_entry_from_reset;
  61
  62         struct working_area_s *dcc_working_area;
  63
  64         int fast_memory_access;
  65         int dcc_downloads;
  66
  67         int (*examine_debug_reason)(target_t *target);
  68
  69         void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
  70
  71         void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
  72         void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
  73         void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr);
  74
  75         void (*write_xpsr)(target_t *target, u32 xpsr, int spsr);
  76         void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
  77         void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
  78
  79         void (*load_word_regs)(target_t *target, u32 mask);
  80         void (*load_hword_reg)(target_t *target, int num);
  81         void (*load_byte_reg)(target_t *target, int num);
  82
  83         void (*store_word_regs)(target_t *target, u32 mask);
  84         void (*store_hword_reg)(target_t *target, int num);
  85         void (*store_byte_reg)(target_t *target, int num);
  86
  87         void (*write_pc)(target_t *target, u32 pc);
  88         void (*branch_resume)(target_t *target);
  89         void (*branch_resume_thumb)(target_t *target);
  90
  91         void (*enable_single_step)(target_t *target);
  92         void (*disable_single_step)(target_t *target);
  93
  94         void (*set_special_dbgrq)(target_t *target);
  95
  96         void (*pre_debug_entry)(target_t *target);
  97         void (*post_debug_entry)(target_t *target);
  98
  99         void (*pre_restore_context)(target_t *target);
 100         void (*post_restore_context)(target_t *target);
 101
 102         armv4_5_common_t armv4_5_common;
 103         void *arch_info;
 104
 105 } arm7_9_common_t;
 106
 107 int arm7_9_register_commands(struct command_context_s *cmd_ctx);
 108
 109 int arm7_9_poll(target_t *target);
 110
 111 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer);
 112
 113 int arm7_9_setup(target_t *target);
 114 int arm7_9_assert_reset(target_t *target);
 115 int arm7_9_deassert_reset(target_t *target);
 116 int arm7_9_reset_request_halt(target_t *target);
 117 int arm7_9_early_halt(target_t *target);
 118 int arm7_9_soft_reset_halt(struct target_s *target);
 119 int arm7_9_prepare_reset_halt(struct target_s *target);
 120
 121 int arm7_9_halt(target_t *target);
 122 int arm7_9_debug_entry(target_t *target);
 123 int arm7_9_full_context(target_t *target);
 124 int arm7_9_restore_context(target_t *target);
 125 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
 126 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
 127 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
 128 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 129 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 130 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
 131 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
 132 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank);
 133
 134 int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, u32 entry_point, void *arch_info);
 135
 136 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 137 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 138 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 139 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 140
 141 void arm7_9_enable_eice_step(target_t *target);
 142 void arm7_9_disable_eice_step(target_t *target);
 143
 144 int arm7_9_execute_sys_speed(struct target_s *target);
 145
 146 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
 147 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
 148
 149
 150 #endif /* ARM7_9_COMMON_H */