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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2008 by Hongtao Zheng                                   *
  12  *   hontor@126.com                                                        *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  ***************************************************************************/
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include "breakpoints.h"
  34 #include "embeddedice.h"
  35 #include "target_request.h"
  36 #include "etm.h"
  37 #include "time_support.h"
  38 #include "arm_simulator.h"
  39 #include "algorithm.h"
  40 #include "register.h"
  41
  42
  43 /**
  44  * @file
  45  * Hold common code supporting the ARM7 and ARM9 core generations.
  46  *
  47  * While the ARM core implementations evolved substantially during these
  48  * two generations, they look quite similar from the JTAG perspective.
  49  * Both have similar debug facilities, based on the same two scan chains
  50  * providing access to the core and to an EmbeddedICE module.  Both can
  51  * support similar ETM and ETB modules, for tracing.  And both expose
  52  * what could be viewed as "ARM Classic", with multiple processor modes,
  53  * shadowed registers, and support for the Thumb instruction set.
  54  *
  55  * Processor differences include things like presence or absence of MMU
  56  * and cache, pipeline sizes, use of a modified Harvard Architecure
  57  * (with separate instruction and data busses from the CPU), support
  58  * for cpu clock gating during idle, and more.
  59  */
  60
  61 static int arm7_9_debug_entry(struct target *target);
  62
  63 /**
  64  * Clear watchpoints for an ARM7/9 target.
  65  *
  66  * @param arm7_9 Pointer to the common struct for an ARM7/9 target
  67  * @return JTAG error status after executing queue
  68  */
  69 static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
  70 {
  71         LOG_DEBUG("-");
  72         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
  73         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  74         arm7_9->sw_breakpoint_count = 0;
  75         arm7_9->sw_breakpoints_added = 0;
  76         arm7_9->wp0_used = 0;
  77         arm7_9->wp1_used = arm7_9->wp1_used_default;
  78         arm7_9->wp_available = arm7_9->wp_available_max;
  79
  80         return jtag_execute_queue();
  81 }
  82
  83 /**
  84  * Assign a watchpoint to one of the two available hardware comparators in an
  85  * ARM7 or ARM9 target.
  86  *
  87  * @param arm7_9 Pointer to the common struct for an ARM7/9 target
  88  * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
  89  */
  90 static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
  91 {
  92         if (!arm7_9->wp0_used)
  93         {
  94                 arm7_9->wp0_used = 1;
  95                 breakpoint->set = 1;
  96                 arm7_9->wp_available--;
  97         }
  98         else if (!arm7_9->wp1_used)
  99         {
 100                 arm7_9->wp1_used = 1;
 101                 breakpoint->set = 2;
 102                 arm7_9->wp_available--;
 103         }
 104         else
 105         {
 106                 LOG_ERROR("BUG: no hardware comparator available");
 107         }
 108         LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
 109                           breakpoint->unique_id,
 110                           breakpoint->address,
 111                           breakpoint->set );
 112 }
 113
 114 /**
 115  * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
 116  *
 117  * @param arm7_9 Pointer to common struct for ARM7/9 targets
 118  * @return Error codes if there is a problem finding a watchpoint or the result
 119  *         of executing the JTAG queue
 120  */
 121 static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
 122 {
 123         if (arm7_9->sw_breakpoints_added)
 124         {
 125                 return ERROR_OK;
 126         }
 127         if (arm7_9->wp_available < 1)
 128         {
 129                 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
 130                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 131         }
 132         arm7_9->wp_available--;
 133
 134         /* pick a breakpoint unit */
 135         if (!arm7_9->wp0_used)
 136         {
 137                 arm7_9->sw_breakpoints_added = 1;
 138                 arm7_9->wp0_used = 3;
 139         } else if (!arm7_9->wp1_used)
 140         {
 141                 arm7_9->sw_breakpoints_added = 2;
 142                 arm7_9->wp1_used = 3;
 143         }
 144         else
 145         {
 146                 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
 147                 return ERROR_FAIL;
 148         }
 149
 150         if (arm7_9->sw_breakpoints_added == 1)
 151         {
 152                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
 153                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
 154                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
 155                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 156                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 157         }
 158         else if (arm7_9->sw_breakpoints_added == 2)
 159         {
 160                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
 161                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
 162                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
 163                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 164                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 165         }
 166         else
 167         {
 168                 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
 169                 return ERROR_FAIL;
 170         }
 171         LOG_DEBUG("SW BP using hw wp: %d",
 172                           arm7_9->sw_breakpoints_added );
 173
 174         return jtag_execute_queue();
 175 }
 176
 177 /**
 178  * Setup the common pieces for an ARM7/9 target after reset or on startup.
 179  *
 180  * @param target Pointer to an ARM7/9 target to setup
 181  * @return Result of clearing the watchpoints on the target
 182  */
 183 int arm7_9_setup(struct target *target)
 184 {
 185         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 186
 187         return arm7_9_clear_watchpoints(arm7_9);
 188 }
 189
 190 /**
 191  * Set either a hardware or software breakpoint on an ARM7/9 target.  The
 192  * breakpoint is set up even if it is already set.  Some actions, e.g. reset,
 193  * might have erased the values in Embedded ICE.
 194  *
 195  * @param target Pointer to the target device to set the breakpoints on
 196  * @param breakpoint Pointer to the breakpoint to be set
 197  * @return For hardware breakpoints, this is the result of executing the JTAG
 198  *         queue.  For software breakpoints, this will be the status of the
 199  *         required memory reads and writes
 200  */
 201 int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 202 {
 203         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 204         int retval = ERROR_OK;
 205
 206         LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
 207                           breakpoint->unique_id,
 208                           breakpoint->address,
 209                           breakpoint->type);
 210
 211         if (target->state != TARGET_HALTED)
 212         {
 213                 LOG_WARNING("target not halted");
 214                 return ERROR_TARGET_NOT_HALTED;
 215         }
 216
 217         if (breakpoint->type == BKPT_HARD)
 218         {
 219                 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
 220                 uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 221
 222                 /* reassign a hw breakpoint */
 223                 if (breakpoint->set == 0)
 224                 {
 225                         arm7_9_assign_wp(arm7_9, breakpoint);
 226                 }
 227
 228                 if (breakpoint->set == 1)
 229                 {
 230                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
 231                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 232                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
 233                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 234                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 235                 }
 236                 else if (breakpoint->set == 2)
 237                 {
 238                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
 239                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 240                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
 241                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 242                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 243                 }
 244                 else
 245                 {
 246                         LOG_ERROR("BUG: no hardware comparator available");
 247                         return ERROR_OK;
 248                 }
 249
 250                 retval = jtag_execute_queue();
 251         }
 252         else if (breakpoint->type == BKPT_SOFT)
 253         {
 254                 /* did we already set this breakpoint? */
 255                 if (breakpoint->set)
 256                         return ERROR_OK;
 257
 258                 if (breakpoint->length == 4)
 259                 {
 260                         uint32_t verify = 0xffffffff;
 261                         /* keep the original instruction in target endianness */
 262                         if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 263                         {
 264                                 return retval;
 265                         }
 266                         /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 267                         if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
 268                         {
 269                                 return retval;
 270                         }
 271
 272                         if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
 273                         {
 274                                 return retval;
 275                         }
 276                         if (verify != arm7_9->arm_bkpt)
 277                         {
 278                                 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 279                                 return ERROR_OK;
 280                         }
 281                 }
 282                 else
 283                 {
 284                         uint16_t verify = 0xffff;
 285                         /* keep the original instruction in target endianness */
 286                         if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 287                         {
 288                                 return retval;
 289                         }
 290                         /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
 291                         if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
 292                         {
 293                                 return retval;
 294                         }
 295
 296                         if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
 297                         {
 298                                 return retval;
 299                         }
 300                         if (verify != arm7_9->thumb_bkpt)
 301                         {
 302                                 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 303                                 return ERROR_OK;
 304                         }
 305                 }
 306
 307                 if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
 308                         return retval;
 309
 310                 arm7_9->sw_breakpoint_count++;
 311
 312                 breakpoint->set = 1;
 313         }
 314
 315         return retval;
 316 }
 317
 318 /**
 319  * Unsets an existing breakpoint on an ARM7/9 target.  If it is a hardware
 320  * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
 321  * will be updated.  Otherwise, the software breakpoint will be restored to its
 322  * original instruction if it hasn't already been modified.
 323  *
 324  * @param target Pointer to ARM7/9 target to unset the breakpoint from
 325  * @param breakpoint Pointer to breakpoint to be unset
 326  * @return For hardware breakpoints, this is the result of executing the JTAG
 327  *         queue.  For software breakpoints, this will be the status of the
 328  *         required memory reads and writes
 329  */
 330 int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 331 {
 332         int retval = ERROR_OK;
 333         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 334
 335         LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
 336                           breakpoint->unique_id,
 337                           breakpoint->address );
 338
 339         if (!breakpoint->set)
 340         {
 341                 LOG_WARNING("breakpoint not set");
 342                 return ERROR_OK;
 343         }
 344
 345         if (breakpoint->type == BKPT_HARD)
 346         {
 347                 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
 348                                   breakpoint->unique_id,
 349                                   breakpoint->set );
 350                 if (breakpoint->set == 1)
 351                 {
 352                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 353                         arm7_9->wp0_used = 0;
 354                         arm7_9->wp_available++;
 355                 }
 356                 else if (breakpoint->set == 2)
 357                 {
 358                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 359                         arm7_9->wp1_used = 0;
 360                         arm7_9->wp_available++;
 361                 }
 362                 retval = jtag_execute_queue();
 363                 breakpoint->set = 0;
 364         }
 365         else
 366         {
 367                 /* restore original instruction (kept in target endianness) */
 368                 if (breakpoint->length == 4)
 369                 {
 370                         uint32_t current_instr;
 371                         /* check that user program as not modified breakpoint instruction */
 372                         if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
 373                         {
 374                                 return retval;
 375                         }
 376                         if (current_instr == arm7_9->arm_bkpt)
 377                                 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 378                                 {
 379                                         return retval;
 380                                 }
 381                 }
 382                 else
 383                 {
 384                         uint16_t current_instr;
 385                         /* check that user program as not modified breakpoint instruction */
 386                         if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
 387                         {
 388                                 return retval;
 389                         }
 390                         if (current_instr == arm7_9->thumb_bkpt)
 391                                 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 392                                 {
 393                                         return retval;
 394                                 }
 395                 }
 396
 397                 if (--arm7_9->sw_breakpoint_count==0)
 398                 {
 399                         /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
 400                         if (arm7_9->sw_breakpoints_added == 1)
 401                         {
 402                                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
 403                         }
 404                         else if (arm7_9->sw_breakpoints_added == 2)
 405                         {
 406                                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
 407                         }
 408                 }
 409
 410                 breakpoint->set = 0;
 411         }
 412
 413         return retval;
 414 }
 415
 416 /**
 417  * Add a breakpoint to an ARM7/9 target.  This makes sure that there are no
 418  * dangling breakpoints and that the desired breakpoint can be added.
 419  *
 420  * @param target Pointer to the target ARM7/9 device to add a breakpoint to
 421  * @param breakpoint Pointer to the breakpoint to be added
 422  * @return An error status if there is a problem adding the breakpoint or the
 423  *         result of setting the breakpoint
 424  */
 425 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 426 {
 427         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 428
 429         if (target->state != TARGET_HALTED)
 430         {
 431                 LOG_WARNING("target not halted");
 432                 return ERROR_TARGET_NOT_HALTED;
 433         }
 434
 435         if (arm7_9->breakpoint_count == 0)
 436         {
 437                 /* make sure we don't have any dangling breakpoints. This is vital upon
 438                  * GDB connect/disconnect
 439                  */
 440                 arm7_9_clear_watchpoints(arm7_9);
 441         }
 442
 443         if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
 444         {
 445                 LOG_INFO("no watchpoint unit available for hardware breakpoint");
 446                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 447         }
 448
 449         if ((breakpoint->length != 2) && (breakpoint->length != 4))
 450         {
 451                 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 452                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 453         }
 454
 455         if (breakpoint->type == BKPT_HARD)
 456         {
 457                 arm7_9_assign_wp(arm7_9, breakpoint);
 458         }
 459
 460         arm7_9->breakpoint_count++;
 461
 462         return arm7_9_set_breakpoint(target, breakpoint);
 463 }
 464
 465 /**
 466  * Removes a breakpoint from an ARM7/9 target.  This will make sure there are no
 467  * dangling breakpoints and updates available watchpoints if it is a hardware
 468  * breakpoint.
 469  *
 470  * @param target Pointer to the target to have a breakpoint removed
 471  * @param breakpoint Pointer to the breakpoint to be removed
 472  * @return Error status if there was a problem unsetting the breakpoint or the
 473  *         watchpoints could not be cleared
 474  */
 475 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 476 {
 477         int retval = ERROR_OK;
 478         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 479
 480         if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
 481         {
 482                 return retval;
 483         }
 484
 485         if (breakpoint->type == BKPT_HARD)
 486                 arm7_9->wp_available++;
 487
 488         arm7_9->breakpoint_count--;
 489         if (arm7_9->breakpoint_count == 0)
 490         {
 491                 /* make sure we don't have any dangling breakpoints */
 492                 if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
 493                 {
 494                         return retval;
 495                 }
 496         }
 497
 498         return ERROR_OK;
 499 }
 500
 501 /**
 502  * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units.  It is
 503  * considered a bug to call this function when there are no available watchpoint
 504  * units.
 505  *
 506  * @param target Pointer to an ARM7/9 target to set a watchpoint on
 507  * @param watchpoint Pointer to the watchpoint to be set
 508  * @return Error status if watchpoint set fails or the result of executing the
 509  *         JTAG queue
 510  */
 511 int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
 512 {
 513         int retval = ERROR_OK;
 514         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 515         int rw_mask = 1;
 516         uint32_t mask;
 517
 518         mask = watchpoint->length - 1;
 519
 520         if (target->state != TARGET_HALTED)
 521         {
 522                 LOG_WARNING("target not halted");
 523                 return ERROR_TARGET_NOT_HALTED;
 524         }
 525
 526         if (watchpoint->rw == WPT_ACCESS)
 527                 rw_mask = 0;
 528         else
 529                 rw_mask = 1;
 530
 531         if (!arm7_9->wp0_used)
 532         {
 533                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
 534                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 535                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
 536                 if (watchpoint->mask != 0xffffffffu)
 537                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
 538                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 539                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 540
 541                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 542                 {
 543                         return retval;
 544                 }
 545                 watchpoint->set = 1;
 546                 arm7_9->wp0_used = 2;
 547         }
 548         else if (!arm7_9->wp1_used)
 549         {
 550                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
 551                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 552                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
 553                 if (watchpoint->mask != 0xffffffffu)
 554                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
 555                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 556                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 557
 558                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 559                 {
 560                         return retval;
 561                 }
 562                 watchpoint->set = 2;
 563                 arm7_9->wp1_used = 2;
 564         }
 565         else
 566         {
 567                 LOG_ERROR("BUG: no hardware comparator available");
 568                 return ERROR_OK;
 569         }
 570
 571         return ERROR_OK;
 572 }
 573
 574 /**
 575  * Unset an existing watchpoint and clear the used watchpoint unit.
 576  *
 577  * @param target Pointer to the target to have the watchpoint removed
 578  * @param watchpoint Pointer to the watchpoint to be removed
 579  * @return Error status while trying to unset the watchpoint or the result of
 580  *         executing the JTAG queue
 581  */
 582 int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
 583 {
 584         int retval = ERROR_OK;
 585         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 586
 587         if (target->state != TARGET_HALTED)
 588         {
 589                 LOG_WARNING("target not halted");
 590                 return ERROR_TARGET_NOT_HALTED;
 591         }
 592
 593         if (!watchpoint->set)
 594         {
 595                 LOG_WARNING("breakpoint not set");
 596                 return ERROR_OK;
 597         }
 598
 599         if (watchpoint->set == 1)
 600         {
 601                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 602                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 603                 {
 604                         return retval;
 605                 }
 606                 arm7_9->wp0_used = 0;
 607         }
 608         else if (watchpoint->set == 2)
 609         {
 610                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 611                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 612                 {
 613                         return retval;
 614                 }
 615                 arm7_9->wp1_used = 0;
 616         }
 617         watchpoint->set = 0;
 618
 619         return ERROR_OK;
 620 }
 621
 622 /**
 623  * Add a watchpoint to an ARM7/9 target.  If there are no watchpoint units
 624  * available, an error response is returned.
 625  *
 626  * @param target Pointer to the ARM7/9 target to add a watchpoint to
 627  * @param watchpoint Pointer to the watchpoint to be added
 628  * @return Error status while trying to add the watchpoint
 629  */
 630 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 631 {
 632         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 633
 634         if (target->state != TARGET_HALTED)
 635         {
 636                 LOG_WARNING("target not halted");
 637                 return ERROR_TARGET_NOT_HALTED;
 638         }
 639
 640         if (arm7_9->wp_available < 1)
 641         {
 642                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 643         }
 644
 645         if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
 646         {
 647                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 648         }
 649
 650         arm7_9->wp_available--;
 651
 652         return ERROR_OK;
 653 }
 654
 655 /**
 656  * Remove a watchpoint from an ARM7/9 target.  The watchpoint will be unset and
 657  * the used watchpoint unit will be reopened.
 658  *
 659  * @param target Pointer to the target to remove a watchpoint from
 660  * @param watchpoint Pointer to the watchpoint to be removed
 661  * @return Result of trying to unset the watchpoint
 662  */
 663 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
 664 {
 665         int retval = ERROR_OK;
 666         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 667
 668         if (watchpoint->set)
 669         {
 670                 if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
 671                 {
 672                         return retval;
 673                 }
 674         }
 675
 676         arm7_9->wp_available++;
 677
 678         return ERROR_OK;
 679 }
 680
 681 /**
 682  * Restarts the target by sending a RESTART instruction and moving the JTAG
 683  * state to IDLE.  This includes a timeout waiting for DBGACK and SYSCOMP to be
 684  * asserted by the processor.
 685  *
 686  * @param target Pointer to target to issue commands to
 687  * @return Error status if there is a timeout or a problem while executing the
 688  *         JTAG queue
 689  */
 690 int arm7_9_execute_sys_speed(struct target *target)
 691 {
 692         int retval;
 693         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 694         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 695         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 696
 697         /* set RESTART instruction */
 698         jtag_set_end_state(TAP_IDLE);
 699         if (arm7_9->need_bypass_before_restart) {
 700                 arm7_9->need_bypass_before_restart = 0;
 701                 arm_jtag_set_instr(jtag_info, 0xf, NULL);
 702         }
 703         arm_jtag_set_instr(jtag_info, 0x4, NULL);
 704
 705         long long then = timeval_ms();
 706         int timeout;
 707         while (!(timeout = ((timeval_ms()-then) > 1000)))
 708         {
 709                 /* read debug status register */
 710                 embeddedice_read_reg(dbg_stat);
 711                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 712                         return retval;
 713                 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 714                                    && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 715                         break;
 716                 if (debug_level >= 3)
 717                 {
 718                         alive_sleep(100);
 719                 } else
 720                 {
 721                         keep_alive();
 722                 }
 723         }
 724         if (timeout)
 725         {
 726                 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 727                 return ERROR_TARGET_TIMEOUT;
 728         }
 729
 730         return ERROR_OK;
 731 }
 732
 733 /**
 734  * Restarts the target by sending a RESTART instruction and moving the JTAG
 735  * state to IDLE.  This validates that DBGACK and SYSCOMP are set without
 736  * waiting until they are.
 737  *
 738  * @param target Pointer to the target to issue commands to
 739  * @return Always ERROR_OK
 740  */
 741 int arm7_9_execute_fast_sys_speed(struct target *target)
 742 {
 743         static int set = 0;
 744         static uint8_t check_value[4], check_mask[4];
 745
 746         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 747         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 748         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 749
 750         /* set RESTART instruction */
 751         jtag_set_end_state(TAP_IDLE);
 752         if (arm7_9->need_bypass_before_restart) {
 753                 arm7_9->need_bypass_before_restart = 0;
 754                 arm_jtag_set_instr(jtag_info, 0xf, NULL);
 755         }
 756         arm_jtag_set_instr(jtag_info, 0x4, NULL);
 757
 758         if (!set)
 759         {
 760                 /* check for DBGACK and SYSCOMP set (others don't care) */
 761
 762                 /* NB! These are constants that must be available until after next jtag_execute() and
 763                  * we evaluate the values upon first execution in lieu of setting up these constants
 764                  * during early setup.
 765                  * */
 766                 buf_set_u32(check_value, 0, 32, 0x9);
 767                 buf_set_u32(check_mask, 0, 32, 0x9);
 768                 set = 1;
 769         }
 770
 771         /* read debug status register */
 772         embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask);
 773
 774         return ERROR_OK;
 775 }
 776
 777 /**
 778  * Get some data from the ARM7/9 target.
 779  *
 780  * @param target Pointer to the ARM7/9 target to read data from
 781  * @param size The number of 32bit words to be read
 782  * @param buffer Pointer to the buffer that will hold the data
 783  * @return The result of receiving data from the Embedded ICE unit
 784  */
 785 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
 786 {
 787         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 788         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 789         uint32_t *data;
 790         int retval = ERROR_OK;
 791         uint32_t i;
 792
 793         data = malloc(size * (sizeof(uint32_t)));
 794
 795         retval = embeddedice_receive(jtag_info, data, size);
 796
 797         /* return the 32-bit ints in the 8-bit array */
 798         for (i = 0; i < size; i++)
 799         {
 800                 h_u32_to_le(buffer + (i * 4), data[i]);
 801         }
 802
 803         free(data);
 804
 805         return retval;
 806 }
 807
 808 /**
 809  * Handles requests to an ARM7/9 target.  If debug messaging is enabled, the
 810  * target is running and the DCC control register has the W bit high, this will
 811  * execute the request on the target.
 812  *
 813  * @param priv Void pointer expected to be a struct target pointer
 814  * @return ERROR_OK unless there are issues with the JTAG queue or when reading
 815  *                  from the Embedded ICE unit
 816  */
 817 int arm7_9_handle_target_request(void *priv)
 818 {
 819         int retval = ERROR_OK;
 820         struct target *target = priv;
 821         if (!target_was_examined(target))
 822                 return ERROR_OK;
 823         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 824         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 825         struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
 826
 827         if (!target->dbg_msg_enabled)
 828                 return ERROR_OK;
 829
 830         if (target->state == TARGET_RUNNING)
 831         {
 832                 /* read DCC control register */
 833                 embeddedice_read_reg(dcc_control);
 834                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 835                 {
 836                         return retval;
 837                 }
 838
 839                 /* check W bit */
 840                 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
 841                 {
 842                         uint32_t request;
 843
 844                         if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
 845                         {
 846                                 return retval;
 847                         }
 848                         if ((retval = target_request(target, request)) != ERROR_OK)
 849                         {
 850                                 return retval;
 851                         }
 852                 }
 853         }
 854
 855         return ERROR_OK;
 856 }
 857
 858 /**
 859  * Polls an ARM7/9 target for its current status.  If DBGACK is set, the target
 860  * is manipulated to the right halted state based on its current state.  This is
 861  * what happens:
 862  *
 863  * <table>
 864  *              <tr><th > State</th><th > Action</th></tr>
 865  *              <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode.  If TARGET_RESET, pc may be checked</td></tr>
 866  *              <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
 867  *              <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
 868  *              <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
 869  * </table>
 870  *
 871  * If the target does not end up in the halted state, a warning is produced.  If
 872  * DBGACK is cleared, then the target is expected to either be running or
 873  * running in debug.
 874  *
 875  * @param target Pointer to the ARM7/9 target to poll
 876  * @return ERROR_OK or an error status if a command fails
 877  */
 878 int arm7_9_poll(struct target *target)
 879 {
 880         int retval;
 881         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 882         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 883
 884         /* read debug status register */
 885         embeddedice_read_reg(dbg_stat);
 886         if ((retval = jtag_execute_queue()) != ERROR_OK)
 887         {
 888                 return retval;
 889         }
 890
 891         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 892         {
 893 /*              LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
 894                 if (target->state == TARGET_UNKNOWN)
 895                 {
 896                         /* Starting OpenOCD with target in debug-halt */
 897                         target->state = TARGET_RUNNING;
 898                         LOG_DEBUG("DBGACK already set during server startup.");
 899                 }
 900                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 901                 {
 902                         int check_pc = 0;
 903                         if (target->state == TARGET_RESET)
 904                         {
 905                                 if (target->reset_halt)
 906                                 {
 907                                         enum reset_types jtag_reset_config = jtag_get_reset_config();
 908                                         if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
 909                                         {
 910                                                 check_pc = 1;
 911                                         }
 912                                 }
 913                         }
 914
 915                         target->state = TARGET_HALTED;
 916
 917                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 918                                 return retval;
 919
 920                         if (check_pc)
 921                         {
 922                                 struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
 923                                 uint32_t t=*((uint32_t *)reg->value);
 924                                 if (t != 0)
 925                                 {
 926                                         LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
 927                                 }
 928                         }
 929
 930                         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 931                         {
 932                                 return retval;
 933                         }
 934                 }
 935                 if (target->state == TARGET_DEBUG_RUNNING)
 936                 {
 937                         target->state = TARGET_HALTED;
 938                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 939                                 return retval;
 940
 941                         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
 942                         {
 943                                 return retval;
 944                         }
 945                 }
 946                 if (target->state != TARGET_HALTED)
 947                 {
 948                         LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state);
 949                 }
 950         }
 951         else
 952         {
 953                 if (target->state != TARGET_DEBUG_RUNNING)
 954                         target->state = TARGET_RUNNING;
 955         }
 956
 957         return ERROR_OK;
 958 }
 959
 960 /**
 961  * Asserts the reset (SRST) on an ARM7/9 target.  Some -S targets (ARM966E-S in
 962  * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
 963  * affected) completely stop the JTAG clock while the core is held in reset
 964  * (SRST).  It isn't possible to program the halt condition once reset is
 965  * asserted, hence a hook that allows the target to set up its reset-halt
 966  * condition is setup prior to asserting reset.
 967  *
 968  * @param target Pointer to an ARM7/9 target to assert reset on
 969  * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
 970  */
 971 int arm7_9_assert_reset(struct target *target)
 972 {
 973         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 974
 975         LOG_DEBUG("target->state: %s",
 976                   target_state_name(target));
 977
 978         enum reset_types jtag_reset_config = jtag_get_reset_config();
 979         if (!(jtag_reset_config & RESET_HAS_SRST))
 980         {
 981                 LOG_ERROR("Can't assert SRST");
 982                 return ERROR_FAIL;
 983         }
 984
 985         /* At this point trst has been asserted/deasserted once. We would
 986          * like to program EmbeddedICE while SRST is asserted, instead of
 987          * depending on SRST to leave that module alone.  However, many CPUs
 988          * gate the JTAG clock while SRST is asserted; or JTAG may need
 989          * clock stability guarantees (adaptive clocking might help).
 990          *
 991          * So we assume JTAG access during SRST is off the menu unless it's
 992          * been specifically enabled.
 993          */
 994         bool srst_asserted = false;
 995
 996         if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
 997                         && (jtag_reset_config & RESET_SRST_NO_GATING))
 998         {
 999                 jtag_add_reset(0, 1);
1000                 srst_asserted = true;
1001         }
1002
1003         if (target->reset_halt)
1004         {
1005                 /*
1006                  * Some targets do not support communication while SRST is asserted. We need to
1007                  * set up the reset vector catch here.
1008                  *
1009                  * If TRST is asserted, then these settings will be reset anyway, so setting them
1010                  * here is harmless.
1011                  */
1012                 if (arm7_9->has_vector_catch)
1013                 {
1014                         /* program vector catch register to catch reset vector */
1015                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
1016
1017                         /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
1018                         jtag_add_runtest(1, jtag_get_end_state());
1019                 }
1020                 else
1021                 {
1022                         /* program watchpoint unit to match on reset vector address */
1023                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
1024                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
1025                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1026                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1027                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1028                 }
1029         }
1030
1031         /* here we should issue an SRST only, but we may have to assert TRST as well */
1032         if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1033         {
1034                 jtag_add_reset(1, 1);
1035         } else if (!srst_asserted)
1036         {
1037                 jtag_add_reset(0, 1);
1038         }
1039
1040         target->state = TARGET_RESET;
1041         jtag_add_sleep(50000);
1042
1043         register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
1044
1045         if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
1046         {
1047                 /* debug entry was already prepared in arm7_9_assert_reset() */
1048                 target->debug_reason = DBG_REASON_DBGRQ;
1049         }
1050
1051         return ERROR_OK;
1052 }
1053
1054 /**
1055  * Deassert the reset (SRST) signal on an ARM7/9 target.  If SRST pulls TRST
1056  * and the target is being reset into a halt, a warning will be triggered
1057  * because it is not possible to reset into a halted mode in this case.  The
1058  * target is halted using the target's functions.
1059  *
1060  * @param target Pointer to the target to have the reset deasserted
1061  * @return ERROR_OK or an error from polling or halting the target
1062  */
1063 int arm7_9_deassert_reset(struct target *target)
1064 {
1065         int retval = ERROR_OK;
1066         LOG_DEBUG("target->state: %s",
1067                 target_state_name(target));
1068
1069         /* deassert reset lines */
1070         jtag_add_reset(0, 0);
1071
1072         enum reset_types jtag_reset_config = jtag_get_reset_config();
1073         if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
1074         {
1075                 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1076                 /* set up embedded ice registers again */
1077                 if ((retval = target_examine_one(target)) != ERROR_OK)
1078                         return retval;
1079
1080                 if ((retval = target_poll(target)) != ERROR_OK)
1081                 {
1082                         return retval;
1083                 }
1084
1085                 if ((retval = target_halt(target)) != ERROR_OK)
1086                 {
1087                         return retval;
1088                 }
1089
1090         }
1091         return retval;
1092 }
1093
1094 /**
1095  * Clears the halt condition for an ARM7/9 target.  If it isn't coming out of
1096  * reset and if DBGRQ is used, it is progammed to be deasserted.  If the reset
1097  * vector catch was used, it is restored.  Otherwise, the control value is
1098  * restored and the watchpoint unit is restored if it was in use.
1099  *
1100  * @param target Pointer to the ARM7/9 target to have halt cleared
1101  * @return Always ERROR_OK
1102  */
1103 int arm7_9_clear_halt(struct target *target)
1104 {
1105         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1106         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1107
1108         /* we used DBGRQ only if we didn't come out of reset */
1109         if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
1110         {
1111                 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1112                  */
1113                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1114                 embeddedice_store_reg(dbg_ctrl);
1115         }
1116         else
1117         {
1118                 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
1119                 {
1120                         /* if we came out of reset, and vector catch is supported, we used
1121                          * vector catch to enter debug state
1122                          * restore the register in that case
1123                          */
1124                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
1125                 }
1126                 else
1127                 {
1128                         /* restore registers if watchpoint unit 0 was in use
1129                          */
1130                         if (arm7_9->wp0_used)
1131                         {
1132                                 if (arm7_9->debug_entry_from_reset)
1133                                 {
1134                                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
1135                                 }
1136                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1137                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1138                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1139                         }
1140                         /* control value always has to be restored, as it was either disabled,
1141                          * or enabled with possibly different bits
1142                          */
1143                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1144                 }
1145         }
1146
1147         return ERROR_OK;
1148 }
1149
1150 /**
1151  * Issue a software reset and halt to an ARM7/9 target.  The target is halted
1152  * and then there is a wait until the processor shows the halt.  This wait can
1153  * timeout and results in an error being returned.  The software reset involves
1154  * clearing the halt, updating the debug control register, changing to ARM mode,
1155  * reset of the program counter, and reset of all of the registers.
1156  *
1157  * @param target Pointer to the ARM7/9 target to be reset and halted by software
1158  * @return Error status if any of the commands fail, otherwise ERROR_OK
1159  */
1160 int arm7_9_soft_reset_halt(struct target *target)
1161 {
1162         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1163         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1164         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1165         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1166         int i;
1167         int retval;
1168
1169         /* FIX!!! replace some of this code with tcl commands
1170          *
1171          * halt # the halt command is synchronous
1172          * armv4_5 core_state arm
1173          *
1174          */
1175
1176         if ((retval = target_halt(target)) != ERROR_OK)
1177                 return retval;
1178
1179         long long then = timeval_ms();
1180         int timeout;
1181         while (!(timeout = ((timeval_ms()-then) > 1000)))
1182         {
1183                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
1184                         break;
1185                 embeddedice_read_reg(dbg_stat);
1186                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1187                         return retval;
1188                 if (debug_level >= 3)
1189                 {
1190                         alive_sleep(100);
1191                 } else
1192                 {
1193                         keep_alive();
1194                 }
1195         }
1196         if (timeout)
1197         {
1198                 LOG_ERROR("Failed to halt CPU after 1 sec");
1199                 return ERROR_TARGET_TIMEOUT;
1200         }
1201         target->state = TARGET_HALTED;
1202
1203         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1204          * ensure that DBGRQ is cleared
1205          */
1206         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1207         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1208         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1209         embeddedice_store_reg(dbg_ctrl);
1210
1211         if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1212         {
1213                 return retval;
1214         }
1215
1216         /* if the target is in Thumb state, change to ARM state */
1217         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1218         {
1219                 uint32_t r0_thumb, pc_thumb;
1220                 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1221                 /* Entered debug from Thumb mode */
1222                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1223                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1224         }
1225
1226         /* all register content is now invalid */
1227         register_cache_invalidate(armv4_5->core_cache);
1228
1229         /* SVC, ARM state, IRQ and FIQ disabled */
1230         uint32_t cpsr;
1231
1232         cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
1233         cpsr &= ~0xff;
1234         cpsr |= 0xd3;
1235         arm_set_cpsr(armv4_5, cpsr);
1236         armv4_5->cpsr->dirty = 1;
1237         armv4_5->core_state = ARMV4_5_STATE_ARM;
1238
1239         /* start fetching from 0x0 */
1240         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
1241         armv4_5->core_cache->reg_list[15].dirty = 1;
1242         armv4_5->core_cache->reg_list[15].valid = 1;
1243
1244         /* reset registers */
1245         for (i = 0; i <= 14; i++)
1246         {
1247                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
1248                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1249                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1250         }
1251
1252         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1253         {
1254                 return retval;
1255         }
1256
1257         return ERROR_OK;
1258 }
1259
1260 /**
1261  * Halt an ARM7/9 target.  This is accomplished by either asserting the DBGRQ
1262  * line or by programming a watchpoint to trigger on any address.  It is
1263  * considered a bug to call this function while the target is in the
1264  * TARGET_RESET state.
1265  *
1266  * @param target Pointer to the ARM7/9 target to be halted
1267  * @return Always ERROR_OK
1268  */
1269 int arm7_9_halt(struct target *target)
1270 {
1271         if (target->state == TARGET_RESET)
1272         {
1273                 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1274                 return ERROR_OK;
1275         }
1276
1277         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1278         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1279
1280         LOG_DEBUG("target->state: %s",
1281                   target_state_name(target));
1282
1283         if (target->state == TARGET_HALTED)
1284         {
1285                 LOG_DEBUG("target was already halted");
1286                 return ERROR_OK;
1287         }
1288
1289         if (target->state == TARGET_UNKNOWN)
1290         {
1291                 LOG_WARNING("target was in unknown state when halt was requested");
1292         }
1293
1294         if (arm7_9->use_dbgrq)
1295         {
1296                 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1297                  */
1298                 if (arm7_9->set_special_dbgrq) {
1299                         arm7_9->set_special_dbgrq(target);
1300                 } else {
1301                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1302                         embeddedice_store_reg(dbg_ctrl);
1303                 }
1304         }
1305         else
1306         {
1307                 /* program watchpoint unit to match on any address
1308                  */
1309                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1310                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1311                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1312                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1313         }
1314
1315         target->debug_reason = DBG_REASON_DBGRQ;
1316
1317         return ERROR_OK;
1318 }
1319
1320 /**
1321  * Handle an ARM7/9 target's entry into debug mode.  The halt is cleared on the
1322  * ARM.  The JTAG queue is then executed and the reason for debug entry is
1323  * examined.  Once done, the target is verified to be halted and the processor
1324  * is forced into ARM mode.  The core registers are saved for the current core
1325  * mode and the program counter (register 15) is updated as needed.  The core
1326  * registers and CPSR and SPSR are saved for restoration later.
1327  *
1328  * @param target Pointer to target that is entering debug mode
1329  * @return Error code if anything fails, otherwise ERROR_OK
1330  */
1331 static int arm7_9_debug_entry(struct target *target)
1332 {
1333         int i;
1334         uint32_t context[16];
1335         uint32_t* context_p[16];
1336         uint32_t r0_thumb, pc_thumb;
1337         uint32_t cpsr;
1338         int retval;
1339         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1340         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1341         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1342         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1343
1344 #ifdef _DEBUG_ARM7_9_
1345         LOG_DEBUG("-");
1346 #endif
1347
1348         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1349          * ensure that DBGRQ is cleared
1350          */
1351         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1352         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1353         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1354         embeddedice_store_reg(dbg_ctrl);
1355
1356         if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1357         {
1358                 return retval;
1359         }
1360
1361         if ((retval = jtag_execute_queue()) != ERROR_OK)
1362         {
1363                 return retval;
1364         }
1365
1366         if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1367                 return retval;
1368
1369
1370         if (target->state != TARGET_HALTED)
1371         {
1372                 LOG_WARNING("target not halted");
1373                 return ERROR_TARGET_NOT_HALTED;
1374         }
1375
1376         /* if the target is in Thumb state, change to ARM state */
1377         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1378         {
1379                 LOG_DEBUG("target entered debug from Thumb state");
1380                 /* Entered debug from Thumb mode */
1381                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1382                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1383                 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 ", pc_thumb: 0x%8.8" PRIx32 "", r0_thumb, pc_thumb);
1384         }
1385         else
1386         {
1387                 LOG_DEBUG("target entered debug from ARM state");
1388                 /* Entered debug from ARM mode */
1389                 armv4_5->core_state = ARMV4_5_STATE_ARM;
1390         }
1391
1392         for (i = 0; i < 16; i++)
1393                 context_p[i] = &context[i];
1394         /* save core registers (r0 - r15 of current core mode) */
1395         arm7_9->read_core_regs(target, 0xffff, context_p);
1396
1397         arm7_9->read_xpsr(target, &cpsr, 0);
1398
1399         if ((retval = jtag_execute_queue()) != ERROR_OK)
1400                 return retval;
1401
1402         /* if the core has been executing in Thumb state, set the T bit */
1403         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1404                 cpsr |= 0x20;
1405
1406         arm_set_cpsr(armv4_5, cpsr);
1407
1408         if (!is_arm_mode(armv4_5->core_mode))
1409         {
1410                 target->state = TARGET_UNKNOWN;
1411                 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1412                 return ERROR_TARGET_FAILURE;
1413         }
1414
1415         LOG_DEBUG("target entered debug state in %s mode",
1416                          arm_mode_name(armv4_5->core_mode));
1417
1418         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1419         {
1420                 LOG_DEBUG("thumb state, applying fixups");
1421                 context[0] = r0_thumb;
1422                 context[15] = pc_thumb;
1423         } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1424         {
1425                 /* adjust value stored by STM */
1426                 context[15] -= 3 * 4;
1427         }
1428
1429         if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
1430                 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1431         else
1432                 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1433
1434         for (i = 0; i <= 15; i++)
1435         {
1436                 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
1437                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1438                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1439                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1440         }
1441
1442         LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
1443
1444         /* exceptions other than USR & SYS have a saved program status register */
1445         if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1446         {
1447                 uint32_t spsr;
1448                 arm7_9->read_xpsr(target, &spsr, 1);
1449                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1450                 {
1451                         return retval;
1452                 }
1453                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1454                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1455                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1456         }
1457
1458         /* r0 and r15 (pc) have to be restored later */
1459         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1460         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1461
1462         if ((retval = jtag_execute_queue()) != ERROR_OK)
1463                 return retval;
1464
1465         if (arm7_9->post_debug_entry)
1466                 arm7_9->post_debug_entry(target);
1467
1468         return ERROR_OK;
1469 }
1470
1471 /**
1472  * Validate the full context for an ARM7/9 target in all processor modes.  If
1473  * there are any invalid registers for the target, they will all be read.  This
1474  * includes the PSR.
1475  *
1476  * @param target Pointer to the ARM7/9 target to capture the full context from
1477  * @return Error if the target is not halted, has an invalid core mode, or if
1478  *         the JTAG queue fails to execute
1479  */
1480 int arm7_9_full_context(struct target *target)
1481 {
1482         int i;
1483         int retval;
1484         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1485         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1486
1487         LOG_DEBUG("-");
1488
1489         if (target->state != TARGET_HALTED)
1490         {
1491                 LOG_WARNING("target not halted");
1492                 return ERROR_TARGET_NOT_HALTED;
1493         }
1494
1495         if (!is_arm_mode(armv4_5->core_mode))
1496                 return ERROR_FAIL;
1497
1498         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1499          * SYS shares registers with User, so we don't touch SYS
1500          */
1501         for (i = 0; i < 6; i++)
1502         {
1503                 uint32_t mask = 0;
1504                 uint32_t* reg_p[16];
1505                 int j;
1506                 int valid = 1;
1507
1508                 /* check if there are invalid registers in the current mode
1509                  */
1510                 for (j = 0; j <= 16; j++)
1511                 {
1512                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1513                                 valid = 0;
1514                 }
1515
1516                 if (!valid)
1517                 {
1518                         uint32_t tmp_cpsr;
1519
1520                         /* change processor mode (and mask T bit) */
1521                         tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
1522                                         & 0xe0;
1523                         tmp_cpsr |= armv4_5_number_to_mode(i);
1524                         tmp_cpsr &= ~0x20;
1525                         arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1526
1527                         for (j = 0; j < 15; j++)
1528                         {
1529                                 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1530                                 {
1531                                         reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1532                                         mask |= 1 << j;
1533                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1534                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1535                                 }
1536                         }
1537
1538                         /* if only the PSR is invalid, mask is all zeroes */
1539                         if (mask)
1540                                 arm7_9->read_core_regs(target, mask, reg_p);
1541
1542                         /* check if the PSR has to be read */
1543                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1544                         {
1545                                 arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1546                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1547                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1548                         }
1549                 }
1550         }
1551
1552         /* restore processor mode (mask T bit) */
1553         arm7_9->write_xpsr_im8(target,
1554                         buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
1555                         0, 0);
1556
1557         if ((retval = jtag_execute_queue()) != ERROR_OK)
1558         {
1559                 return retval;
1560         }
1561         return ERROR_OK;
1562 }
1563
1564 /**
1565  * Restore the processor context on an ARM7/9 target.  The full processor
1566  * context is analyzed to see if any of the registers are dirty on this end, but
1567  * have a valid new value.  If this is the case, the processor is changed to the
1568  * appropriate mode and the new register values are written out to the
1569  * processor.  If there happens to be a dirty register with an invalid value, an
1570  * error will be logged.
1571  *
1572  * @param target Pointer to the ARM7/9 target to have its context restored
1573  * @return Error status if the target is not halted or the core mode in the
1574  *         armv4_5 struct is invalid.
1575  */
1576 int arm7_9_restore_context(struct target *target)
1577 {
1578         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1579         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1580         struct reg *reg;
1581         struct arm_reg *reg_arch_info;
1582         enum armv4_5_mode current_mode = armv4_5->core_mode;
1583         int i, j;
1584         int dirty;
1585         int mode_change;
1586
1587         LOG_DEBUG("-");
1588
1589         if (target->state != TARGET_HALTED)
1590         {
1591                 LOG_WARNING("target not halted");
1592                 return ERROR_TARGET_NOT_HALTED;
1593         }
1594
1595         if (arm7_9->pre_restore_context)
1596                 arm7_9->pre_restore_context(target);
1597
1598         if (!is_arm_mode(armv4_5->core_mode))
1599                 return ERROR_FAIL;
1600
1601         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1602          * SYS shares registers with User, so we don't touch SYS
1603          */
1604         for (i = 0; i < 6; i++)
1605         {
1606                 LOG_DEBUG("examining %s mode",
1607                                 arm_mode_name(armv4_5->core_mode));
1608                 dirty = 0;
1609                 mode_change = 0;
1610                 /* check if there are dirty registers in the current mode
1611                 */
1612                 for (j = 0; j <= 16; j++)
1613                 {
1614                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1615                         reg_arch_info = reg->arch_info;
1616                         if (reg->dirty == 1)
1617                         {
1618                                 if (reg->valid == 1)
1619                                 {
1620                                         dirty = 1;
1621                                         LOG_DEBUG("examining dirty reg: %s", reg->name);
1622                                         if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1623                                                 && (reg_arch_info->mode != current_mode)
1624                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1625                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1626                                         {
1627                                                 mode_change = 1;
1628                                                 LOG_DEBUG("require mode change");
1629                                         }
1630                                 }
1631                                 else
1632                                 {
1633                                         LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1634                                 }
1635                         }
1636                 }
1637
1638                 if (dirty)
1639                 {
1640                         uint32_t mask = 0x0;
1641                         int num_regs = 0;
1642                         uint32_t regs[16];
1643
1644                         if (mode_change)
1645                         {
1646                                 uint32_t tmp_cpsr;
1647
1648                                 /* change processor mode (mask T bit) */
1649                                 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
1650                                                 0, 8) & 0xe0;
1651                                 tmp_cpsr |= armv4_5_number_to_mode(i);
1652                                 tmp_cpsr &= ~0x20;
1653                                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1654                                 current_mode = armv4_5_number_to_mode(i);
1655                         }
1656
1657                         for (j = 0; j <= 14; j++)
1658                         {
1659                                 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1660                                 reg_arch_info = reg->arch_info;
1661
1662
1663                                 if (reg->dirty == 1)
1664                                 {
1665                                         regs[j] = buf_get_u32(reg->value, 0, 32);
1666                                         mask |= 1 << j;
1667                                         num_regs++;
1668                                         reg->dirty = 0;
1669                                         reg->valid = 1;
1670                                         LOG_DEBUG("writing register %i mode %s "
1671                                                 "with value 0x%8.8" PRIx32, j,
1672                                                 arm_mode_name(armv4_5->core_mode),
1673                                                 regs[j]);
1674                                 }
1675                         }
1676
1677                         if (mask)
1678                         {
1679                                 arm7_9->write_core_regs(target, mask, regs);
1680                         }
1681
1682                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1683                         reg_arch_info = reg->arch_info;
1684                         if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1685                         {
1686                                 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
1687                                 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1688                         }
1689                 }
1690         }
1691
1692         if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
1693         {
1694                 /* restore processor mode (mask T bit) */
1695                 uint32_t tmp_cpsr;
1696
1697                 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
1698                 tmp_cpsr |= armv4_5_number_to_mode(i);
1699                 tmp_cpsr &= ~0x20;
1700                 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
1701                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1702         }
1703         else if (armv4_5->cpsr->dirty)
1704         {
1705                 /* CPSR has been changed, full restore necessary (mask T bit) */
1706                 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1707                                 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1708                 arm7_9->write_xpsr(target,
1709                                 buf_get_u32(armv4_5->cpsr->value, 0, 32)
1710                                         & ~0x20, 0);
1711                 armv4_5->cpsr->dirty = 0;
1712                 armv4_5->cpsr->valid = 1;
1713         }
1714
1715         /* restore PC */
1716         LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1717         arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1718         armv4_5->core_cache->reg_list[15].dirty = 0;
1719
1720         if (arm7_9->post_restore_context)
1721                 arm7_9->post_restore_context(target);
1722
1723         return ERROR_OK;
1724 }
1725
1726 /**
1727  * Restart the core of an ARM7/9 target.  A RESTART command is sent to the
1728  * instruction register and the JTAG state is set to TAP_IDLE causing a core
1729  * restart.
1730  *
1731  * @param target Pointer to the ARM7/9 target to be restarted
1732  * @return Result of executing the JTAG queue
1733  */
1734 int arm7_9_restart_core(struct target *target)
1735 {
1736         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1737         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
1738
1739         /* set RESTART instruction */
1740         jtag_set_end_state(TAP_IDLE);
1741         if (arm7_9->need_bypass_before_restart) {
1742                 arm7_9->need_bypass_before_restart = 0;
1743                 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1744         }
1745         arm_jtag_set_instr(jtag_info, 0x4, NULL);
1746
1747         jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE));
1748         return jtag_execute_queue();
1749 }
1750
1751 /**
1752  * Enable the watchpoints on an ARM7/9 target.  The target's watchpoints are
1753  * iterated through and are set on the target if they aren't already set.
1754  *
1755  * @param target Pointer to the ARM7/9 target to enable watchpoints on
1756  */
1757 void arm7_9_enable_watchpoints(struct target *target)
1758 {
1759         struct watchpoint *watchpoint = target->watchpoints;
1760
1761         while (watchpoint)
1762         {
1763                 if (watchpoint->set == 0)
1764                         arm7_9_set_watchpoint(target, watchpoint);
1765                 watchpoint = watchpoint->next;
1766         }
1767 }
1768
1769 /**
1770  * Enable the breakpoints on an ARM7/9 target.  The target's breakpoints are
1771  * iterated through and are set on the target.
1772  *
1773  * @param target Pointer to the ARM7/9 target to enable breakpoints on
1774  */
1775 void arm7_9_enable_breakpoints(struct target *target)
1776 {
1777         struct breakpoint *breakpoint = target->breakpoints;
1778
1779         /* set any pending breakpoints */
1780         while (breakpoint)
1781         {
1782                 arm7_9_set_breakpoint(target, breakpoint);
1783                 breakpoint = breakpoint->next;
1784         }
1785 }
1786
1787 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
1788 {
1789         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1790         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1791         struct breakpoint *breakpoint = target->breakpoints;
1792         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1793         int err, retval = ERROR_OK;
1794
1795         LOG_DEBUG("-");
1796
1797         if (target->state != TARGET_HALTED)
1798         {
1799                 LOG_WARNING("target not halted");
1800                 return ERROR_TARGET_NOT_HALTED;
1801         }
1802
1803         if (!debug_execution)
1804         {
1805                 target_free_all_working_areas(target);
1806         }
1807
1808         /* current = 1: continue on current pc, otherwise continue at <address> */
1809         if (!current)
1810                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1811
1812         uint32_t current_pc;
1813         current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1814
1815         /* the front-end may request us not to handle breakpoints */
1816         if (handle_breakpoints)
1817         {
1818                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1819                 {
1820                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
1821                         if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1822                         {
1823                                 return retval;
1824                         }
1825
1826                         /* calculate PC of next instruction */
1827                         uint32_t next_pc;
1828                         if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1829                         {
1830                                 uint32_t current_opcode;
1831                                 target_read_u32(target, current_pc, &current_opcode);
1832                                 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1833                                 return retval;
1834                         }
1835
1836                         LOG_DEBUG("enable single-step");
1837                         arm7_9->enable_single_step(target, next_pc);
1838
1839                         target->debug_reason = DBG_REASON_SINGLESTEP;
1840
1841                         if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1842                         {
1843                                 return retval;
1844                         }
1845
1846                         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1847                                 arm7_9->branch_resume(target);
1848                         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1849                         {
1850                                 arm7_9->branch_resume_thumb(target);
1851                         }
1852                         else
1853                         {
1854                                 LOG_ERROR("unhandled core state");
1855                                 return ERROR_FAIL;
1856                         }
1857
1858                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1859                         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1860                         err = arm7_9_execute_sys_speed(target);
1861
1862                         LOG_DEBUG("disable single-step");
1863                         arm7_9->disable_single_step(target);
1864
1865                         if (err != ERROR_OK)
1866                         {
1867                                 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1868                                 {
1869                                         return retval;
1870                                 }
1871                                 target->state = TARGET_UNKNOWN;
1872                                 return err;
1873                         }
1874
1875                         arm7_9_debug_entry(target);
1876                         LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1877
1878                         LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1879                         if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1880                         {
1881                                 return retval;
1882                         }
1883                 }
1884         }
1885
1886         /* enable any pending breakpoints and watchpoints */
1887         arm7_9_enable_breakpoints(target);
1888         arm7_9_enable_watchpoints(target);
1889
1890         if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1891         {
1892                 return retval;
1893         }
1894
1895         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1896         {
1897                 arm7_9->branch_resume(target);
1898         }
1899         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1900         {
1901                 arm7_9->branch_resume_thumb(target);
1902         }
1903         else
1904         {
1905                 LOG_ERROR("unhandled core state");
1906                 return ERROR_FAIL;
1907         }
1908
1909         /* deassert DBGACK and INTDIS */
1910         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1911         /* INTDIS only when we really resume, not during debug execution */
1912         if (!debug_execution)
1913                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1914         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1915
1916         if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1917         {
1918                 return retval;
1919         }
1920
1921         target->debug_reason = DBG_REASON_NOTHALTED;
1922
1923         if (!debug_execution)
1924         {
1925                 /* registers are now invalid */
1926                 register_cache_invalidate(armv4_5->core_cache);
1927                 target->state = TARGET_RUNNING;
1928                 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1929                 {
1930                         return retval;
1931                 }
1932         }
1933         else
1934         {
1935                 target->state = TARGET_DEBUG_RUNNING;
1936                 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1937                 {
1938                         return retval;
1939                 }
1940         }
1941
1942         LOG_DEBUG("target resumed");
1943
1944         return ERROR_OK;
1945 }
1946
1947 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
1948 {
1949         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1950         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1951         uint32_t current_pc;
1952         current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1953
1954         if (next_pc != current_pc)
1955         {
1956                 /* setup an inverse breakpoint on the current PC
1957                 * - comparator 1 matches the current address
1958                 * - rangeout from comparator 1 is connected to comparator 0 rangein
1959                 * - comparator 0 matches any address, as long as rangein is low */
1960                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1961                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1962                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1963                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
1964                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
1965                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1966                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1967                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1968                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1969         }
1970         else
1971         {
1972                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1973                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1974                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
1975                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
1976                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
1977                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1978                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1979                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1980                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1981         }
1982 }
1983
1984 void arm7_9_disable_eice_step(struct target *target)
1985 {
1986         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1987
1988         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1989         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1990         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1991         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1992         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1993         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1994         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1995         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1996         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1997 }
1998
1999 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
2000 {
2001         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2002         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2003         struct breakpoint *breakpoint = NULL;
2004         int err, retval;
2005
2006         if (target->state != TARGET_HALTED)
2007         {
2008                 LOG_WARNING("target not halted");
2009                 return ERROR_TARGET_NOT_HALTED;
2010         }
2011
2012         /* current = 1: continue on current pc, otherwise continue at <address> */
2013         if (!current)
2014                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
2015
2016         uint32_t current_pc;
2017         current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2018
2019         /* the front-end may request us not to handle breakpoints */
2020         if (handle_breakpoints)
2021                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
2022                         if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
2023                         {
2024                                 return retval;
2025                         }
2026
2027         target->debug_reason = DBG_REASON_SINGLESTEP;
2028
2029         /* calculate PC of next instruction */
2030         uint32_t next_pc;
2031         if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
2032         {
2033                 uint32_t current_opcode;
2034                 target_read_u32(target, current_pc, &current_opcode);
2035                 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
2036                 return retval;
2037         }
2038
2039         if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
2040         {
2041                 return retval;
2042         }
2043
2044         arm7_9->enable_single_step(target, next_pc);
2045
2046         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
2047         {
2048                 arm7_9->branch_resume(target);
2049         }
2050         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
2051         {
2052                 arm7_9->branch_resume_thumb(target);
2053         }
2054         else
2055         {
2056                 LOG_ERROR("unhandled core state");
2057                 return ERROR_FAIL;
2058         }
2059
2060         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
2061         {
2062                 return retval;
2063         }
2064
2065         err = arm7_9_execute_sys_speed(target);
2066         arm7_9->disable_single_step(target);
2067
2068         /* registers are now invalid */
2069         register_cache_invalidate(armv4_5->core_cache);
2070
2071         if (err != ERROR_OK)
2072         {
2073                 target->state = TARGET_UNKNOWN;
2074         } else {
2075                 arm7_9_debug_entry(target);
2076                 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
2077                 {
2078                         return retval;
2079                 }
2080                 LOG_DEBUG("target stepped");
2081         }
2082
2083         if (breakpoint)
2084                 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
2085                 {
2086                         return retval;
2087                 }
2088
2089         return err;
2090 }
2091
2092 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
2093                 int num, enum armv4_5_mode mode)
2094 {
2095         uint32_t* reg_p[16];
2096         uint32_t value;
2097         int retval;
2098         struct arm_reg *areg = r->arch_info;
2099         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2100         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2101
2102         if (!is_arm_mode(armv4_5->core_mode))
2103                 return ERROR_FAIL;
2104         if ((num < 0) || (num > 16))
2105                 return ERROR_INVALID_ARGUMENTS;
2106
2107         if ((mode != ARMV4_5_MODE_ANY)
2108                         && (mode != armv4_5->core_mode)
2109                         && (areg->mode != ARMV4_5_MODE_ANY))
2110         {
2111                 uint32_t tmp_cpsr;
2112
2113                 /* change processor mode (mask T bit) */
2114                 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2115                 tmp_cpsr |= mode;
2116                 tmp_cpsr &= ~0x20;
2117                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2118         }
2119
2120         if ((num >= 0) && (num <= 15))
2121         {
2122                 /* read a normal core register */
2123                 reg_p[num] = &value;
2124
2125                 arm7_9->read_core_regs(target, 1 << num, reg_p);
2126         }
2127         else
2128         {
2129                 /* read a program status register
2130                  * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2131                  */
2132                 arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
2133         }
2134
2135         if ((retval = jtag_execute_queue()) != ERROR_OK)
2136         {
2137                 return retval;
2138         }
2139
2140         r->valid = 1;
2141         r->dirty = 0;
2142         buf_set_u32(r->value, 0, 32, value);
2143
2144         if ((mode != ARMV4_5_MODE_ANY)
2145                         && (mode != armv4_5->core_mode)
2146                         && (areg->mode != ARMV4_5_MODE_ANY))    {
2147                 /* restore processor mode (mask T bit) */
2148                 arm7_9->write_xpsr_im8(target,
2149                                 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2150                                         & ~0x20, 0, 0);
2151         }
2152
2153         return ERROR_OK;
2154 }
2155
2156 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
2157                 int num, enum armv4_5_mode mode, uint32_t value)
2158 {
2159         uint32_t reg[16];
2160         struct arm_reg *areg = r->arch_info;
2161         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2162         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2163
2164         if (!is_arm_mode(armv4_5->core_mode))
2165                 return ERROR_FAIL;
2166         if ((num < 0) || (num > 16))
2167                 return ERROR_INVALID_ARGUMENTS;
2168
2169         if ((mode != ARMV4_5_MODE_ANY)
2170                         && (mode != armv4_5->core_mode)
2171                         && (areg->mode != ARMV4_5_MODE_ANY))    {
2172                 uint32_t tmp_cpsr;
2173
2174                 /* change processor mode (mask T bit) */
2175                 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2176                 tmp_cpsr |= mode;
2177                 tmp_cpsr &= ~0x20;
2178                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2179         }
2180
2181         if ((num >= 0) && (num <= 15))
2182         {
2183                 /* write a normal core register */
2184                 reg[num] = value;
2185
2186                 arm7_9->write_core_regs(target, 1 << num, reg);
2187         }
2188         else
2189         {
2190                 /* write a program status register
2191                 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2192                 */
2193                 int spsr = (areg->mode != ARMV4_5_MODE_ANY);
2194
2195                 /* if we're writing the CPSR, mask the T bit */
2196                 if (!spsr)
2197                         value &= ~0x20;
2198
2199                 arm7_9->write_xpsr(target, value, spsr);
2200         }
2201
2202         r->valid = 1;
2203         r->dirty = 0;
2204
2205         if ((mode != ARMV4_5_MODE_ANY)
2206                         && (mode != armv4_5->core_mode)
2207                         && (areg->mode != ARMV4_5_MODE_ANY))    {
2208                 /* restore processor mode (mask T bit) */
2209                 arm7_9->write_xpsr_im8(target,
2210                                 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2211                                         & ~0x20, 0, 0);
2212         }
2213
2214         return jtag_execute_queue();
2215 }
2216
2217 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2218 {
2219         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2220         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2221         uint32_t reg[16];
2222         uint32_t num_accesses = 0;
2223         int thisrun_accesses;
2224         int i;
2225         uint32_t cpsr;
2226         int retval;
2227         int last_reg = 0;
2228
2229         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
2230
2231         if (target->state != TARGET_HALTED)
2232         {
2233                 LOG_WARNING("target not halted");
2234                 return ERROR_TARGET_NOT_HALTED;
2235         }
2236
2237         /* sanitize arguments */
2238         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2239                 return ERROR_INVALID_ARGUMENTS;
2240
2241         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2242                 return ERROR_TARGET_UNALIGNED_ACCESS;
2243
2244         /* load the base register with the address of the first word */
2245         reg[0] = address;
2246         arm7_9->write_core_regs(target, 0x1, reg);
2247
2248         int j = 0;
2249
2250         switch (size)
2251         {
2252                 case 4:
2253                         while (num_accesses < count)
2254                         {
2255                                 uint32_t reg_list;
2256                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2257                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2258
2259                                 if (last_reg <= thisrun_accesses)
2260                                         last_reg = thisrun_accesses;
2261
2262                                 arm7_9->load_word_regs(target, reg_list);
2263
2264                                 /* fast memory reads are only safe when the target is running
2265                                  * from a sufficiently high clock (32 kHz is usually too slow)
2266                                  */
2267                                 if (arm7_9->fast_memory_access)
2268                                         retval = arm7_9_execute_fast_sys_speed(target);
2269                                 else
2270                                         retval = arm7_9_execute_sys_speed(target);
2271                                 if (retval != ERROR_OK)
2272                                         return retval;
2273
2274                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2275
2276                                 /* advance buffer, count number of accesses */
2277                                 buffer += thisrun_accesses * 4;
2278                                 num_accesses += thisrun_accesses;
2279
2280                                 if ((j++%1024) == 0)
2281                                 {
2282                                         keep_alive();
2283                                 }
2284                         }
2285                         break;
2286                 case 2:
2287                         while (num_accesses < count)
2288                         {
2289                                 uint32_t reg_list;
2290                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2291                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2292
2293                                 for (i = 1; i <= thisrun_accesses; i++)
2294                                 {
2295                                         if (i > last_reg)
2296                                                 last_reg = i;
2297                                         arm7_9->load_hword_reg(target, i);
2298                                         /* fast memory reads are only safe when the target is running
2299                                          * from a sufficiently high clock (32 kHz is usually too slow)
2300                                          */
2301                                         if (arm7_9->fast_memory_access)
2302                                                 retval = arm7_9_execute_fast_sys_speed(target);
2303                                         else
2304                                                 retval = arm7_9_execute_sys_speed(target);
2305                                         if (retval != ERROR_OK)
2306                                         {
2307                                                 return retval;
2308                                         }
2309
2310                                 }
2311
2312                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2313
2314                                 /* advance buffer, count number of accesses */
2315                                 buffer += thisrun_accesses * 2;
2316                                 num_accesses += thisrun_accesses;
2317
2318                                 if ((j++%1024) == 0)
2319                                 {
2320                                         keep_alive();
2321                                 }
2322                         }
2323                         break;
2324                 case 1:
2325                         while (num_accesses < count)
2326                         {
2327                                 uint32_t reg_list;
2328                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2329                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2330
2331                                 for (i = 1; i <= thisrun_accesses; i++)
2332                                 {
2333                                         if (i > last_reg)
2334                                                 last_reg = i;
2335                                         arm7_9->load_byte_reg(target, i);
2336                                         /* fast memory reads are only safe when the target is running
2337                                          * from a sufficiently high clock (32 kHz is usually too slow)
2338                                          */
2339                                         if (arm7_9->fast_memory_access)
2340                                                 retval = arm7_9_execute_fast_sys_speed(target);
2341                                         else
2342                                                 retval = arm7_9_execute_sys_speed(target);
2343                                         if (retval != ERROR_OK)
2344                                         {
2345                                                 return retval;
2346                                         }
2347                                 }
2348
2349                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2350
2351                                 /* advance buffer, count number of accesses */
2352                                 buffer += thisrun_accesses * 1;
2353                                 num_accesses += thisrun_accesses;
2354
2355                                 if ((j++%1024) == 0)
2356                                 {
2357                                         keep_alive();
2358                                 }
2359                         }
2360                         break;
2361                 default:
2362                         LOG_ERROR("BUG: we shouldn't get here");
2363                         exit(-1);
2364                         break;
2365         }
2366
2367         if (!is_arm_mode(armv4_5->core_mode))
2368                 return ERROR_FAIL;
2369
2370         for (i = 0; i <= last_reg; i++)
2371                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2372
2373         arm7_9->read_xpsr(target, &cpsr, 0);
2374         if ((retval = jtag_execute_queue()) != ERROR_OK)
2375         {
2376                 LOG_ERROR("JTAG error while reading cpsr");
2377                 return ERROR_TARGET_DATA_ABORT;
2378         }
2379
2380         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2381         {
2382                 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2383
2384                 arm7_9->write_xpsr_im8(target,
2385                                 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2386                                         & ~0x20, 0, 0);
2387
2388                 return ERROR_TARGET_DATA_ABORT;
2389         }
2390
2391         return ERROR_OK;
2392 }
2393
2394 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2395 {
2396         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2397         struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2398         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2399
2400         uint32_t reg[16];
2401         uint32_t num_accesses = 0;
2402         int thisrun_accesses;
2403         int i;
2404         uint32_t cpsr;
2405         int retval;
2406         int last_reg = 0;
2407
2408 #ifdef _DEBUG_ARM7_9_
2409         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2410 #endif
2411
2412         if (target->state != TARGET_HALTED)
2413         {
2414                 LOG_WARNING("target not halted");
2415                 return ERROR_TARGET_NOT_HALTED;
2416         }
2417
2418         /* sanitize arguments */
2419         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2420                 return ERROR_INVALID_ARGUMENTS;
2421
2422         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2423                 return ERROR_TARGET_UNALIGNED_ACCESS;
2424
2425         /* load the base register with the address of the first word */
2426         reg[0] = address;
2427         arm7_9->write_core_regs(target, 0x1, reg);
2428
2429         /* Clear DBGACK, to make sure memory fetches work as expected */
2430         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2431         embeddedice_store_reg(dbg_ctrl);
2432
2433         switch (size)
2434         {
2435                 case 4:
2436                         while (num_accesses < count)
2437                         {
2438                                 uint32_t reg_list;
2439                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2440                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2441
2442                                 for (i = 1; i <= thisrun_accesses; i++)
2443                                 {
2444                                         if (i > last_reg)
2445                                                 last_reg = i;
2446                                         reg[i] = target_buffer_get_u32(target, buffer);
2447                                         buffer += 4;
2448                                 }
2449
2450                                 arm7_9->write_core_regs(target, reg_list, reg);
2451
2452                                 arm7_9->store_word_regs(target, reg_list);
2453
2454                                 /* fast memory writes are only safe when the target is running
2455                                  * from a sufficiently high clock (32 kHz is usually too slow)
2456                                  */
2457                                 if (arm7_9->fast_memory_access)
2458                                         retval = arm7_9_execute_fast_sys_speed(target);
2459                                 else
2460                                         retval = arm7_9_execute_sys_speed(target);
2461                                 if (retval != ERROR_OK)
2462                                 {
2463                                         return retval;
2464                                 }
2465
2466                                 num_accesses += thisrun_accesses;
2467                         }
2468                         break;
2469                 case 2:
2470                         while (num_accesses < count)
2471                         {
2472                                 uint32_t reg_list;
2473                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2474                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2475
2476                                 for (i = 1; i <= thisrun_accesses; i++)
2477                                 {
2478                                         if (i > last_reg)
2479                                                 last_reg = i;
2480                                         reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2481                                         buffer += 2;
2482                                 }
2483
2484                                 arm7_9->write_core_regs(target, reg_list, reg);
2485
2486                                 for (i = 1; i <= thisrun_accesses; i++)
2487                                 {
2488                                         arm7_9->store_hword_reg(target, i);
2489
2490                                         /* fast memory writes are only safe when the target is running
2491                                          * from a sufficiently high clock (32 kHz is usually too slow)
2492                                          */
2493                                         if (arm7_9->fast_memory_access)
2494                                                 retval = arm7_9_execute_fast_sys_speed(target);
2495                                         else
2496                                                 retval = arm7_9_execute_sys_speed(target);
2497                                         if (retval != ERROR_OK)
2498                                         {
2499                                                 return retval;
2500                                         }
2501                                 }
2502
2503                                 num_accesses += thisrun_accesses;
2504                         }
2505                         break;
2506                 case 1:
2507                         while (num_accesses < count)
2508                         {
2509                                 uint32_t reg_list;
2510                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2511                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2512
2513                                 for (i = 1; i <= thisrun_accesses; i++)
2514                                 {
2515                                         if (i > last_reg)
2516                                                 last_reg = i;
2517                                         reg[i] = *buffer++ & 0xff;
2518                                 }
2519
2520                                 arm7_9->write_core_regs(target, reg_list, reg);
2521
2522                                 for (i = 1; i <= thisrun_accesses; i++)
2523                                 {
2524                                         arm7_9->store_byte_reg(target, i);
2525                                         /* fast memory writes are only safe when the target is running
2526                                          * from a sufficiently high clock (32 kHz is usually too slow)
2527                                          */
2528                                         if (arm7_9->fast_memory_access)
2529                                                 retval = arm7_9_execute_fast_sys_speed(target);
2530                                         else
2531                                                 retval = arm7_9_execute_sys_speed(target);
2532                                         if (retval != ERROR_OK)
2533                                         {
2534                                                 return retval;
2535                                         }
2536
2537                                 }
2538
2539                                 num_accesses += thisrun_accesses;
2540                         }
2541                         break;
2542                 default:
2543                         LOG_ERROR("BUG: we shouldn't get here");
2544                         exit(-1);
2545                         break;
2546         }
2547
2548         /* Re-Set DBGACK */
2549         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2550         embeddedice_store_reg(dbg_ctrl);
2551
2552         if (!is_arm_mode(armv4_5->core_mode))
2553                 return ERROR_FAIL;
2554
2555         for (i = 0; i <= last_reg; i++)
2556                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2557
2558         arm7_9->read_xpsr(target, &cpsr, 0);
2559         if ((retval = jtag_execute_queue()) != ERROR_OK)
2560         {
2561                 LOG_ERROR("JTAG error while reading cpsr");
2562                 return ERROR_TARGET_DATA_ABORT;
2563         }
2564
2565         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2566         {
2567                 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2568
2569                 arm7_9->write_xpsr_im8(target,
2570                                 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2571                                         & ~0x20, 0, 0);
2572
2573                 return ERROR_TARGET_DATA_ABORT;
2574         }
2575
2576         return ERROR_OK;
2577 }
2578
2579 static int dcc_count;
2580 static uint8_t *dcc_buffer;
2581
2582 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
2583 {
2584         int retval = ERROR_OK;
2585         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2586
2587         if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
2588                 return retval;
2589
2590         int little = target->endianness == TARGET_LITTLE_ENDIAN;
2591         int count = dcc_count;
2592         uint8_t *buffer = dcc_buffer;
2593         if (count > 2)
2594         {
2595                 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2596                  * core function repeated. */
2597                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2598                 buffer += 4;
2599
2600                 struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2601                 uint8_t reg_addr = ice_reg->addr & 0x1f;
2602                 struct jtag_tap *tap;
2603                 tap = ice_reg->jtag_info->tap;
2604
2605                 embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
2606                 buffer += (count-2)*4;
2607
2608                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2609         } else
2610         {
2611                 int i;
2612                 for (i = 0; i < count; i++)
2613                 {
2614                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2615                         buffer += 4;
2616                 }
2617         }
2618
2619         if ((retval = target_halt(target))!= ERROR_OK)
2620         {
2621                 return retval;
2622         }
2623         return target_wait_state(target, TARGET_HALTED, 500);
2624 }
2625
2626 static const uint32_t dcc_code[] =
2627 {
2628         /* r0 == input, points to memory buffer
2629          * r1 == scratch
2630          */
2631
2632         /* spin until DCC control (c0) reports data arrived */
2633         0xee101e10,     /* w: mrc p14, #0, r1, c0, c0 */
2634         0xe3110001,     /*    tst r1, #1              */
2635         0x0afffffc,     /*    bne w                   */
2636
2637         /* read word from DCC (c1), write to memory */
2638         0xee111e10,     /*    mrc p14, #0, r1, c1, c0 */
2639         0xe4801004,     /*    str r1, [r0], #4        */
2640
2641         /* repeat */
2642         0xeafffff9      /*    b   w                   */
2643 };
2644
2645 int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info));
2646
2647 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
2648 {
2649         int retval;
2650         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2651         int i;
2652
2653         if (!arm7_9->dcc_downloads)
2654                 return target_write_memory(target, address, 4, count, buffer);
2655
2656         /* regrab previously allocated working_area, or allocate a new one */
2657         if (!arm7_9->dcc_working_area)
2658         {
2659                 uint8_t dcc_code_buf[6 * 4];
2660
2661                 /* make sure we have a working area */
2662                 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2663                 {
2664                         LOG_INFO("no working area available, falling back to memory writes");
2665                         return target_write_memory(target, address, 4, count, buffer);
2666                 }
2667
2668                 /* copy target instructions to target endianness */
2669                 for (i = 0; i < 6; i++)
2670                 {
2671                         target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2672                 }
2673
2674                 /* write DCC code to working area */
2675                 if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2676                 {
2677                         return retval;
2678                 }
2679         }
2680
2681         struct armv4_5_algorithm armv4_5_info;
2682         struct reg_param reg_params[1];
2683
2684         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2685         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2686         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2687
2688         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2689
2690         buf_set_u32(reg_params[0].value, 0, 32, address);
2691
2692         dcc_count = count;
2693         dcc_buffer = buffer;
2694         retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2695                         arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
2696
2697         if (retval == ERROR_OK)
2698         {
2699                 uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
2700                 if (endaddress != (address + count*4))
2701                 {
2702                         LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
2703                         retval = ERROR_FAIL;
2704                 }
2705         }
2706
2707         destroy_reg_param(&reg_params[0]);
2708
2709         return retval;
2710 }
2711
2712 /**
2713  * Perform per-target setup that requires JTAG access.
2714  */
2715 int arm7_9_examine(struct target *target)
2716 {
2717         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2718         int retval;
2719
2720         if (!target_was_examined(target)) {
2721                 struct reg_cache *t, **cache_p;
2722
2723                 t = embeddedice_build_reg_cache(target, arm7_9);
2724                 if (t == NULL)
2725                         return ERROR_FAIL;
2726
2727                 cache_p = register_get_last_cache_p(&target->reg_cache);
2728                 (*cache_p) = t;
2729                 arm7_9->eice_cache = (*cache_p);
2730
2731                 if (arm7_9->armv4_5_common.etm)
2732                         (*cache_p)->next = etm_build_reg_cache(target,
2733                                         &arm7_9->jtag_info,
2734                                         arm7_9->armv4_5_common.etm);
2735
2736                 target_set_examined(target);
2737         }
2738
2739         retval = embeddedice_setup(target);
2740         if (retval == ERROR_OK)
2741                 retval = arm7_9_setup(target);
2742         if (retval == ERROR_OK && arm7_9->armv4_5_common.etm)
2743                 retval = etm_setup(target);
2744         return retval;
2745 }
2746
2747 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
2748 {
2749         struct target *target = get_current_target(CMD_CTX);
2750         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2751
2752         if (!is_arm7_9(arm7_9))
2753         {
2754                 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2755                 return ERROR_TARGET_INVALID;
2756         }
2757
2758         if (CMD_ARGC > 0)
2759                 COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
2760
2761         command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2762
2763         return ERROR_OK;
2764 }
2765
2766 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
2767 {
2768         struct target *target = get_current_target(CMD_CTX);
2769         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2770
2771         if (!is_arm7_9(arm7_9))
2772         {
2773                 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2774                 return ERROR_TARGET_INVALID;
2775         }
2776
2777         if (CMD_ARGC > 0)
2778                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
2779
2780         command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2781
2782         return ERROR_OK;
2783 }
2784
2785 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
2786 {
2787         struct target *target = get_current_target(CMD_CTX);
2788         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2789
2790         if (!is_arm7_9(arm7_9))
2791         {
2792                 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2793                 return ERROR_TARGET_INVALID;
2794         }
2795
2796         if (CMD_ARGC > 0)
2797                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
2798
2799         command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2800
2801         return ERROR_OK;
2802 }
2803
2804 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
2805 {
2806         int retval = ERROR_OK;
2807         struct arm *armv4_5 = &arm7_9->armv4_5_common;
2808
2809         arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2810
2811         if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2812                 return retval;
2813
2814         /* caller must have allocated via calloc(), so everything's zeroed */
2815
2816         arm7_9->wp_available_max = 2;
2817
2818         arm7_9->fast_memory_access = false;
2819         arm7_9->dcc_downloads = false;
2820
2821         armv4_5->arch_info = arm7_9;
2822         armv4_5->read_core_reg = arm7_9_read_core_reg;
2823         armv4_5->write_core_reg = arm7_9_write_core_reg;
2824         armv4_5->full_context = arm7_9_full_context;
2825
2826         if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
2827                 return retval;
2828
2829         return target_register_timer_callback(arm7_9_handle_target_request,
2830                         1, 1, target);
2831 }
2832
2833 int arm7_9_register_commands(struct command_context *cmd_ctx)
2834 {
2835         struct command *arm7_9_cmd;
2836
2837         arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9",
2838                         NULL, COMMAND_ANY, "arm7/9 specific commands");
2839
2840         register_command(cmd_ctx, arm7_9_cmd, "dbgrq",
2841                         handle_arm7_9_dbgrq_command, COMMAND_ANY,
2842                         "use EmbeddedICE dbgrq instead of breakpoint "
2843                         "for target halt requests <enable | disable>");
2844         register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access",
2845                         handle_arm7_9_fast_memory_access_command, COMMAND_ANY,
2846                         "use fast memory accesses instead of slower "
2847                         "but potentially safer accesses <enable | disable>");
2848         register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads",
2849                         handle_arm7_9_dcc_downloads_command, COMMAND_ANY,
2850                         "use DCC downloads for larger memory writes <enable | disable>");
2851
2852         armv4_5_register_commands(cmd_ctx);
2853
2854         etm_register_commands(cmd_ctx);
2855
2856         return ERROR_OK;
2857 }