git.gag.com Git - fw/openocd/blob - src/target/arm7_9_common.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "embeddedice.h"
  27 #include "target.h"
  28 #include "target_request.h"
  29 #include "armv4_5.h"
  30 #include "arm_jtag.h"
  31 #include "jtag.h"
  32 #include "log.h"
  33 #include "arm7_9_common.h"
  34 #include "breakpoints.h"
  35
  36 #include <stdlib.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39
  40 #include <sys/types.h>
  41 #include <sys/stat.h>
  42 #include <sys/time.h>
  43 #include <errno.h>
  44
  45 int arm7_9_debug_entry(target_t *target);
  46 int arm7_9_enable_sw_bkpts(struct target_s *target);
  47
  48 /* command handler forward declarations */
  49 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  55 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  56 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  57 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  58 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  59
  60 int arm7_9_reinit_embeddedice(target_t *target)
  61 {
  62         armv4_5_common_t *armv4_5 = target->arch_info;
  63         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  64
  65         breakpoint_t *breakpoint = target->breakpoints;
  66
  67         arm7_9->wp_available = 2;
  68         arm7_9->wp0_used = 0;
  69         arm7_9->wp1_used = 0;
  70
  71         /* mark all hardware breakpoints as unset */
  72         while (breakpoint)
  73         {
  74                 if (breakpoint->type == BKPT_HARD)
  75                 {
  76                         breakpoint->set = 0;
  77                 }
  78                 breakpoint = breakpoint->next;
  79         }
  80
  81         if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
  82         {
  83                 arm7_9->sw_bkpts_enabled = 0;
  84                 arm7_9_enable_sw_bkpts(target);
  85         }
  86
  87         return ERROR_OK;
  88 }
  89
  90 /* set things up after a reset / on startup */
  91 int arm7_9_setup(target_t *target)
  92 {
  93         /* a test-logic reset have occured
  94          * the EmbeddedICE registers have been reset
  95          * hardware breakpoints have been cleared
  96          */
  97         return arm7_9_reinit_embeddedice(target);
  98 }
  99
 100 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
 101 {
 102         armv4_5_common_t *armv4_5 = target->arch_info;
 103         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 104
 105         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 106         {
 107                 return -1;
 108         }
 109
 110         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 111         {
 112                 return -1;
 113         }
 114
 115         *armv4_5_p = armv4_5;
 116         *arm7_9_p = arm7_9;
 117
 118         return ERROR_OK;
 119 }
 120
 121 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 122 {
 123         armv4_5_common_t *armv4_5 = target->arch_info;
 124         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 125
 126         if (target->state != TARGET_HALTED)
 127         {
 128                 LOG_WARNING("target not halted");
 129                 return ERROR_TARGET_NOT_HALTED;
 130         }
 131
 132         if (arm7_9->force_hw_bkpts)
 133                 breakpoint->type = BKPT_HARD;
 134
 135         if (breakpoint->set)
 136         {
 137                 LOG_WARNING("breakpoint already set");
 138                 return ERROR_OK;
 139         }
 140
 141         if (breakpoint->type == BKPT_HARD)
 142         {
 143                 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
 144                 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 145                 if (!arm7_9->wp0_used)
 146                 {
 147                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
 148                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 149                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
 150                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 151                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 152
 153                         jtag_execute_queue();
 154                         arm7_9->wp0_used = 1;
 155                         breakpoint->set = 1;
 156                 }
 157                 else if (!arm7_9->wp1_used)
 158                 {
 159                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
 160                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 161                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
 162                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 163                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 164
 165                         jtag_execute_queue();
 166                         arm7_9->wp1_used = 1;
 167                         breakpoint->set = 2;
 168                 }
 169                 else
 170                 {
 171                         LOG_ERROR("BUG: no hardware comparator available");
 172                         return ERROR_OK;
 173                 }
 174         }
 175         else if (breakpoint->type == BKPT_SOFT)
 176         {
 177                 if (breakpoint->length == 4)
 178                 {
 179                         u32 verify = 0xffffffff;
 180                         /* keep the original instruction in target endianness */
 181                         target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 182                         /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 183                         target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
 184
 185                         target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
 186                         if (verify != arm7_9->arm_bkpt)
 187                         {
 188                                 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
 189                                 return ERROR_OK;
 190                         }
 191                 }
 192                 else
 193                 {
 194                         u16 verify = 0xffff;
 195                         /* keep the original instruction in target endianness */
 196                         target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 197                         /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
 198                         target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
 199
 200                         target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
 201                         if (verify != arm7_9->thumb_bkpt)
 202                         {
 203                                 LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
 204                                 return ERROR_OK;
 205                         }
 206                 }
 207                 breakpoint->set = 1;
 208         }
 209
 210         return ERROR_OK;
 211
 212 }
 213
 214 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 215 {
 216         armv4_5_common_t *armv4_5 = target->arch_info;
 217         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 218
 219         if (target->state != TARGET_HALTED)
 220         {
 221                 LOG_WARNING("target not halted");
 222                 return ERROR_TARGET_NOT_HALTED;
 223         }
 224
 225         if (!breakpoint->set)
 226         {
 227                 LOG_WARNING("breakpoint not set");
 228                 return ERROR_OK;
 229         }
 230
 231         if (breakpoint->type == BKPT_HARD)
 232         {
 233                 if (breakpoint->set == 1)
 234                 {
 235                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 236                         jtag_execute_queue();
 237                         arm7_9->wp0_used = 0;
 238                 }
 239                 else if (breakpoint->set == 2)
 240                 {
 241                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 242                         jtag_execute_queue();
 243                         arm7_9->wp1_used = 0;
 244                 }
 245                 breakpoint->set = 0;
 246         }
 247         else
 248         {
 249                 /* restore original instruction (kept in target endianness) */
 250                 if (breakpoint->length == 4)
 251                 {
 252                         u32 current_instr;
 253                         /* check that user program as not modified breakpoint instruction */
 254                         target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
 255                         if (current_instr==arm7_9->arm_bkpt)
 256                                 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 257                 }
 258                 else
 259                 {
 260                         u16 current_instr;
 261                         /* check that user program as not modified breakpoint instruction */
 262                         target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
 263                         if (current_instr==arm7_9->thumb_bkpt)
 264                                 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 265                 }
 266                 breakpoint->set = 0;
 267         }
 268
 269         return ERROR_OK;
 270 }
 271
 272 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 273 {
 274         armv4_5_common_t *armv4_5 = target->arch_info;
 275         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 276
 277         if (target->state != TARGET_HALTED)
 278         {
 279                 LOG_WARNING("target not halted");
 280                 return ERROR_TARGET_NOT_HALTED;
 281         }
 282
 283         if (arm7_9->force_hw_bkpts)
 284         {
 285                 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
 286                 breakpoint->type = BKPT_HARD;
 287         }
 288
 289         if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
 290         {
 291                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
 292                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 293         }
 294
 295         if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
 296         {
 297                 LOG_INFO("no watchpoint unit available for hardware breakpoint");
 298                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 299         }
 300
 301         if ((breakpoint->length != 2) && (breakpoint->length != 4))
 302         {
 303                 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 304                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 305         }
 306
 307         if (breakpoint->type == BKPT_HARD)
 308                 arm7_9->wp_available--;
 309
 310         return ERROR_OK;
 311 }
 312
 313 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 314 {
 315         armv4_5_common_t *armv4_5 = target->arch_info;
 316         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 317
 318         if (target->state != TARGET_HALTED)
 319         {
 320                 LOG_WARNING("target not halted");
 321                 return ERROR_TARGET_NOT_HALTED;
 322         }
 323
 324         if (breakpoint->set)
 325         {
 326                 arm7_9_unset_breakpoint(target, breakpoint);
 327         }
 328
 329         if (breakpoint->type == BKPT_HARD)
 330                 arm7_9->wp_available++;
 331
 332         return ERROR_OK;
 333 }
 334
 335 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 336 {
 337         armv4_5_common_t *armv4_5 = target->arch_info;
 338         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 339         int rw_mask = 1;
 340         u32 mask;
 341
 342         mask = watchpoint->length - 1;
 343
 344         if (target->state != TARGET_HALTED)
 345         {
 346                 LOG_WARNING("target not halted");
 347                 return ERROR_TARGET_NOT_HALTED;
 348         }
 349
 350         if (watchpoint->rw == WPT_ACCESS)
 351                 rw_mask = 0;
 352         else
 353                 rw_mask = 1;
 354
 355         if (!arm7_9->wp0_used)
 356         {
 357                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
 358                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 359                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
 360                 if( watchpoint->mask != 0xffffffffu )
 361                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
 362                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 363                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 364
 365                 jtag_execute_queue();
 366                 watchpoint->set = 1;
 367                 arm7_9->wp0_used = 2;
 368         }
 369         else if (!arm7_9->wp1_used)
 370         {
 371                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
 372                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 373                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
 374                 if( watchpoint->mask != 0xffffffffu )
 375                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
 376                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 377                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 378
 379                 jtag_execute_queue();
 380                 watchpoint->set = 2;
 381                 arm7_9->wp1_used = 2;
 382         }
 383         else
 384         {
 385                 LOG_ERROR("BUG: no hardware comparator available");
 386                 return ERROR_OK;
 387         }
 388
 389         return ERROR_OK;
 390 }
 391
 392 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 393 {
 394         armv4_5_common_t *armv4_5 = target->arch_info;
 395         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 396
 397         if (target->state != TARGET_HALTED)
 398         {
 399                 LOG_WARNING("target not halted");
 400                 return ERROR_TARGET_NOT_HALTED;
 401         }
 402
 403         if (!watchpoint->set)
 404         {
 405                 LOG_WARNING("breakpoint not set");
 406                 return ERROR_OK;
 407         }
 408
 409         if (watchpoint->set == 1)
 410         {
 411                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 412                 jtag_execute_queue();
 413                 arm7_9->wp0_used = 0;
 414         }
 415         else if (watchpoint->set == 2)
 416         {
 417                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 418                 jtag_execute_queue();
 419                 arm7_9->wp1_used = 0;
 420         }
 421         watchpoint->set = 0;
 422
 423         return ERROR_OK;
 424 }
 425
 426 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 427 {
 428         armv4_5_common_t *armv4_5 = target->arch_info;
 429         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 430
 431         if (target->state != TARGET_HALTED)
 432         {
 433                 LOG_WARNING("target not halted");
 434                 return ERROR_TARGET_NOT_HALTED;
 435         }
 436
 437         if (arm7_9->wp_available < 1)
 438         {
 439                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 440         }
 441
 442         if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
 443         {
 444                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 445         }
 446
 447         arm7_9->wp_available--;
 448
 449         return ERROR_OK;
 450 }
 451
 452 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 453 {
 454         armv4_5_common_t *armv4_5 = target->arch_info;
 455         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 456
 457         if (target->state != TARGET_HALTED)
 458         {
 459                 LOG_WARNING("target not halted");
 460                 return ERROR_TARGET_NOT_HALTED;
 461         }
 462
 463         if (watchpoint->set)
 464         {
 465                 arm7_9_unset_watchpoint(target, watchpoint);
 466         }
 467
 468         arm7_9->wp_available++;
 469
 470         return ERROR_OK;
 471 }
 472
 473 int arm7_9_enable_sw_bkpts(struct target_s *target)
 474 {
 475         armv4_5_common_t *armv4_5 = target->arch_info;
 476         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 477         int retval;
 478
 479         if (arm7_9->sw_bkpts_enabled)
 480                 return ERROR_OK;
 481
 482         if (arm7_9->wp_available < 1)
 483         {
 484                 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
 485                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 486         }
 487         arm7_9->wp_available--;
 488
 489         if (!arm7_9->wp0_used)
 490         {
 491                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
 492                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
 493                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
 494                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 495                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 496                 arm7_9->sw_bkpts_enabled = 1;
 497                 arm7_9->wp0_used = 3;
 498         }
 499         else if (!arm7_9->wp1_used)
 500         {
 501                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
 502                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
 503                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
 504                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 505                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 506                 arm7_9->sw_bkpts_enabled = 2;
 507                 arm7_9->wp1_used = 3;
 508         }
 509         else
 510         {
 511                 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
 512                 return ERROR_FAIL;
 513         }
 514
 515         if ((retval = jtag_execute_queue()) != ERROR_OK)
 516         {
 517                 LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
 518                 return ERROR_FAIL;
 519         };
 520
 521         return ERROR_OK;
 522 }
 523
 524 int arm7_9_disable_sw_bkpts(struct target_s *target)
 525 {
 526         armv4_5_common_t *armv4_5 = target->arch_info;
 527         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 528
 529         if (!arm7_9->sw_bkpts_enabled)
 530                 return ERROR_OK;
 531
 532         if (arm7_9->sw_bkpts_enabled == 1)
 533         {
 534                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 535                 arm7_9->sw_bkpts_enabled = 0;
 536                 arm7_9->wp0_used = 0;
 537                 arm7_9->wp_available++;
 538         }
 539         else if (arm7_9->sw_bkpts_enabled == 2)
 540         {
 541                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 542                 arm7_9->sw_bkpts_enabled = 0;
 543                 arm7_9->wp1_used = 0;
 544                 arm7_9->wp_available++;
 545         }
 546
 547         return ERROR_OK;
 548 }
 549
 550 int arm7_9_execute_sys_speed(struct target_s *target)
 551 {
 552         int timeout;
 553         int retval;
 554
 555         armv4_5_common_t *armv4_5 = target->arch_info;
 556         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 557         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 558         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 559
 560         /* set RESTART instruction */
 561         jtag_add_end_state(TAP_RTI);
 562         if (arm7_9->need_bypass_before_restart) {
 563                 arm7_9->need_bypass_before_restart = 0;
 564                 arm_jtag_set_instr(jtag_info, 0xf, NULL);
 565         }
 566         arm_jtag_set_instr(jtag_info, 0x4, NULL);
 567
 568         for (timeout=0; timeout<50; timeout++)
 569         {
 570                 /* read debug status register */
 571                 embeddedice_read_reg(dbg_stat);
 572                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 573                         return retval;
 574                 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 575                                    && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 576                         break;
 577                 usleep(100000);
 578         }
 579         if (timeout == 50)
 580         {
 581                 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 582                 return ERROR_TARGET_TIMEOUT;
 583         }
 584
 585         return ERROR_OK;
 586 }
 587
 588 int arm7_9_execute_fast_sys_speed(struct target_s *target)
 589 {
 590         static int set=0;
 591         static u8 check_value[4], check_mask[4];
 592
 593         armv4_5_common_t *armv4_5 = target->arch_info;
 594         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 595         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 596         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 597
 598         /* set RESTART instruction */
 599         jtag_add_end_state(TAP_RTI);
 600         if (arm7_9->need_bypass_before_restart) {
 601                 arm7_9->need_bypass_before_restart = 0;
 602                 arm_jtag_set_instr(jtag_info, 0xf, NULL);
 603         }
 604         arm_jtag_set_instr(jtag_info, 0x4, NULL);
 605
 606         if (!set)
 607         {
 608                 /* check for DBGACK and SYSCOMP set (others don't care) */
 609
 610                 /* NB! These are constants that must be available until after next jtag_execute() and
 611                    we evaluate the values upon first execution in lieu of setting up these constants
 612                    during early setup.
 613                 */
 614                 buf_set_u32(check_value, 0, 32, 0x9);
 615                 buf_set_u32(check_mask, 0, 32, 0x9);
 616                 set=1;
 617         }
 618
 619         /* read debug status register */
 620         embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
 621
 622         return ERROR_OK;
 623 }
 624
 625 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
 626 {
 627         armv4_5_common_t *armv4_5 = target->arch_info;
 628         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 629         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 630         u32 *data;
 631         int i;
 632
 633         data = malloc(size * (sizeof(u32)));
 634
 635         embeddedice_receive(jtag_info, data, size);
 636
 637         for (i = 0; i < size; i++)
 638         {
 639                 h_u32_to_le(buffer + (i * 4), data[i]);
 640         }
 641
 642         free(data);
 643
 644         return ERROR_OK;
 645 }
 646
 647 int arm7_9_handle_target_request(void *priv)
 648 {
 649         target_t *target = priv;
 650         if (!target->type->examined)
 651                 return ERROR_OK;
 652         armv4_5_common_t *armv4_5 = target->arch_info;
 653         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 654         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 655         reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
 656
 657
 658         if (!target->dbg_msg_enabled)
 659                 return ERROR_OK;
 660
 661         if (target->state == TARGET_RUNNING)
 662         {
 663                 /* read DCC control register */
 664                 embeddedice_read_reg(dcc_control);
 665                 jtag_execute_queue();
 666
 667                 /* check W bit */
 668                 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
 669                 {
 670                         u32 request;
 671
 672                         embeddedice_receive(jtag_info, &request, 1);
 673                         target_request(target, request);
 674                 }
 675         }
 676
 677         return ERROR_OK;
 678 }
 679
 680 int arm7_9_poll(target_t *target)
 681 {
 682         int retval;
 683         armv4_5_common_t *armv4_5 = target->arch_info;
 684         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 685         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 686
 687         /* read debug status register */
 688         embeddedice_read_reg(dbg_stat);
 689         if ((retval = jtag_execute_queue()) != ERROR_OK)
 690         {
 691                 return retval;
 692         }
 693
 694         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 695         {
 696 /*              LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
 697                 if (target->state == TARGET_UNKNOWN)
 698                 {
 699                         target->state = TARGET_RUNNING;
 700                         LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
 701                 }
 702                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 703                 {
 704                         int check_pc=0;
 705                         if (target->state == TARGET_RESET)
 706                         {
 707                                 if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
 708                                 {
 709                                         if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
 710                                         {
 711                                                 check_pc = 1;
 712                                         }
 713                                 }
 714                         }
 715
 716                         target->state = TARGET_HALTED;
 717
 718                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 719                                 return retval;
 720
 721                         if (check_pc)
 722                         {
 723                                 reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
 724                                 u32 t=*((u32 *)reg->value);
 725                                 if (t!=0)
 726                                 {
 727                                         LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
 728                                 }
 729                         }
 730
 731                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 732                 }
 733                 if (target->state == TARGET_DEBUG_RUNNING)
 734                 {
 735                         target->state = TARGET_HALTED;
 736                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 737                                 return retval;
 738
 739                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 740                 }
 741                 if (target->state != TARGET_HALTED)
 742                 {
 743                         LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
 744                 }
 745         }
 746         else
 747         {
 748                 if (target->state != TARGET_DEBUG_RUNNING)
 749                         target->state = TARGET_RUNNING;
 750         }
 751
 752         return ERROR_OK;
 753 }
 754
 755 /*
 756   Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
 757   in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
 758   while the core is held in reset(SRST). It isn't possible to program the halt
 759   condition once reset was asserted, hence a hook that allows the target to set
 760   up its reset-halt condition prior to asserting reset.
 761 */
 762
 763 int arm7_9_assert_reset(target_t *target)
 764 {
 765         armv4_5_common_t *armv4_5 = target->arch_info;
 766         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 767         LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 768
 769         if (!(jtag_reset_config & RESET_HAS_SRST))
 770         {
 771                 LOG_ERROR("Can't assert SRST");
 772                 return ERROR_FAIL;
 773         }
 774
 775         if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
 776         {
 777                 /*
 778                  * Some targets do not support communication while SRST is asserted. We need to
 779                  * set up the reset vector catch here.
 780                  *
 781                  * If TRST is asserted, then these settings will be reset anyway, so setting them
 782                  * here is harmless.
 783                  */
 784                 if (arm7_9->has_vector_catch)
 785                 {
 786                         /* program vector catch register to catch reset vector */
 787                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
 788                 }
 789                 else
 790                 {
 791                         /* program watchpoint unit to match on reset vector address */
 792                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
 793                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
 794                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
 795                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 796                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 797                 }
 798         }
 799
 800         /* here we should issue a srst only, but we may have to assert trst as well */
 801         if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 802         {
 803                 jtag_add_reset(1, 1);
 804         } else
 805         {
 806                 jtag_add_reset(0, 1);
 807         }
 808
 809
 810         target->state = TARGET_RESET;
 811         jtag_add_sleep(50000);
 812
 813         armv4_5_invalidate_core_regs(target);
 814
 815         return ERROR_OK;
 816
 817 }
 818
 819 int arm7_9_deassert_reset(target_t *target)
 820 {
 821         LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 822
 823         /* deassert reset lines */
 824         jtag_add_reset(0, 0);
 825
 826         return ERROR_OK;
 827 }
 828
 829 int arm7_9_clear_halt(target_t *target)
 830 {
 831         armv4_5_common_t *armv4_5 = target->arch_info;
 832         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 833         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 834
 835         /* we used DBGRQ only if we didn't come out of reset */
 836         if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
 837         {
 838                 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
 839                  */
 840                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 841                 embeddedice_store_reg(dbg_ctrl);
 842         }
 843         else
 844         {
 845                 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
 846                 {
 847                         /* if we came out of reset, and vector catch is supported, we used
 848                          * vector catch to enter debug state
 849                          * restore the register in that case
 850                          */
 851                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
 852                 }
 853                 else
 854                 {
 855                         /* restore registers if watchpoint unit 0 was in use
 856                          */
 857                         if (arm7_9->wp0_used)
 858                         {
 859                                 if (arm7_9->debug_entry_from_reset)
 860                                 {
 861                                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
 862                                 }
 863                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
 864                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
 865                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
 866                         }
 867                         /* control value always has to be restored, as it was either disabled,
 868                          * or enabled with possibly different bits
 869                          */
 870                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 871                 }
 872         }
 873
 874         return ERROR_OK;
 875 }
 876
 877 int arm7_9_soft_reset_halt(struct target_s *target)
 878 {
 879         armv4_5_common_t *armv4_5 = target->arch_info;
 880         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 881         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 882         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 883         int i;
 884         int retval;
 885
 886         if ((retval=target_halt(target))!=ERROR_OK)
 887                 return retval;
 888
 889         for (i=0; i<10; i++)
 890         {
 891                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
 892                         break;
 893                 embeddedice_read_reg(dbg_stat);
 894                 if ((retval=jtag_execute_queue())!=ERROR_OK)
 895                         return retval;
 896                 /* do not eat all CPU, time out after 1 se*/
 897                 usleep(100*1000);
 898
 899         }
 900         if (i==10)
 901         {
 902                 LOG_ERROR("Failed to halt CPU after 1 sec");
 903                 return ERROR_TARGET_TIMEOUT;
 904         }
 905         target->state = TARGET_HALTED;
 906
 907         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 908          * ensure that DBGRQ is cleared
 909          */
 910         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 911         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 912         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 913         embeddedice_store_reg(dbg_ctrl);
 914
 915         arm7_9_clear_halt(target);
 916
 917         /* if the target is in Thumb state, change to ARM state */
 918         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
 919         {
 920                 u32 r0_thumb, pc_thumb;
 921                 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
 922                 /* Entered debug from Thumb mode */
 923                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
 924                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
 925         }
 926
 927         /* all register content is now invalid */
 928         armv4_5_invalidate_core_regs(target);
 929
 930         /* SVC, ARM state, IRQ and FIQ disabled */
 931         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 932         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 933         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 934
 935         /* start fetching from 0x0 */
 936         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 937         armv4_5->core_cache->reg_list[15].dirty = 1;
 938         armv4_5->core_cache->reg_list[15].valid = 1;
 939
 940         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 941         armv4_5->core_state = ARMV4_5_STATE_ARM;
 942
 943         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 944                 return ERROR_FAIL;
 945
 946         /* reset registers */
 947         for (i = 0; i <= 14; i++)
 948         {
 949                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
 950                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
 951                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 952         }
 953
 954         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 955
 956         return ERROR_OK;
 957 }
 958
 959 int arm7_9_halt(target_t *target)
 960 {
 961         armv4_5_common_t *armv4_5 = target->arch_info;
 962         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 963         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 964
 965         LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 966
 967         if (target->state == TARGET_HALTED)
 968         {
 969                 LOG_DEBUG("target was already halted");
 970                 return ERROR_OK;
 971         }
 972
 973         if (target->state == TARGET_UNKNOWN)
 974         {
 975                 LOG_WARNING("target was in unknown state when halt was requested");
 976         }
 977
 978         if (target->state == TARGET_RESET)
 979         {
 980                 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
 981                 {
 982                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 983                         return ERROR_TARGET_FAILURE;
 984                 }
 985                 else
 986                 {
 987                         /* we came here in a reset_halt or reset_init sequence
 988                          * debug entry was already prepared in arm7_9_assert_reset()
 989                          */
 990                         target->debug_reason = DBG_REASON_DBGRQ;
 991
 992                         return ERROR_OK;
 993                 }
 994         }
 995
 996         if (arm7_9->use_dbgrq)
 997         {
 998                 /* program EmbeddedICE Debug Control Register to assert DBGRQ
 999                  */
1000                 if (arm7_9->set_special_dbgrq) {
1001                         arm7_9->set_special_dbgrq(target);
1002                 } else {
1003                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1004                         embeddedice_store_reg(dbg_ctrl);
1005                 }
1006         }
1007         else
1008         {
1009                 /* program watchpoint unit to match on any address
1010                  */
1011                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1012                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1013                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1014                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1015         }
1016
1017         target->debug_reason = DBG_REASON_DBGRQ;
1018
1019         return ERROR_OK;
1020 }
1021
1022 int arm7_9_debug_entry(target_t *target)
1023 {
1024         int i;
1025         u32 context[16];
1026         u32* context_p[16];
1027         u32 r0_thumb, pc_thumb;
1028         u32 cpsr;
1029         int retval;
1030         /* get pointers to arch-specific information */
1031         armv4_5_common_t *armv4_5 = target->arch_info;
1032         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1033         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1034         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1035
1036 #ifdef _DEBUG_ARM7_9_
1037         LOG_DEBUG("-");
1038 #endif
1039
1040         if (arm7_9->pre_debug_entry)
1041                 arm7_9->pre_debug_entry(target);
1042
1043         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1044          * ensure that DBGRQ is cleared
1045          */
1046         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1047         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1048         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1049         embeddedice_store_reg(dbg_ctrl);
1050
1051         arm7_9_clear_halt(target);
1052
1053         if ((retval = jtag_execute_queue()) != ERROR_OK)
1054         {
1055                 return retval;
1056         }
1057
1058         if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1059                 return retval;
1060
1061
1062         if (target->state != TARGET_HALTED)
1063         {
1064                 LOG_WARNING("target not halted");
1065                 return ERROR_TARGET_NOT_HALTED;
1066         }
1067
1068         /* if the target is in Thumb state, change to ARM state */
1069         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1070         {
1071                 LOG_DEBUG("target entered debug from Thumb state");
1072                 /* Entered debug from Thumb mode */
1073                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1074                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1075                 LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1076         }
1077         else
1078         {
1079                 LOG_DEBUG("target entered debug from ARM state");
1080                 /* Entered debug from ARM mode */
1081                 armv4_5->core_state = ARMV4_5_STATE_ARM;
1082         }
1083
1084         for (i = 0; i < 16; i++)
1085                 context_p[i] = &context[i];
1086         /* save core registers (r0 - r15 of current core mode) */
1087         arm7_9->read_core_regs(target, 0xffff, context_p);
1088
1089         arm7_9->read_xpsr(target, &cpsr, 0);
1090
1091         if ((retval = jtag_execute_queue()) != ERROR_OK)
1092                 return retval;
1093
1094         /* if the core has been executing in Thumb state, set the T bit */
1095         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1096                 cpsr |= 0x20;
1097
1098         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1099         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1100         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1101
1102         armv4_5->core_mode = cpsr & 0x1f;
1103
1104         if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1105         {
1106                 target->state = TARGET_UNKNOWN;
1107                 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1108                 return ERROR_TARGET_FAILURE;
1109         }
1110
1111         LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1112
1113         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1114         {
1115                 LOG_DEBUG("thumb state, applying fixups");
1116                 context[0] = r0_thumb;
1117                 context[15] = pc_thumb;
1118         } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1119         {
1120                 /* adjust value stored by STM */
1121                 context[15] -= 3 * 4;
1122         }
1123
1124         if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1125                         || (target->debug_reason == DBG_REASON_SINGLESTEP)
1126                         || (target->debug_reason == DBG_REASON_WATCHPOINT)
1127                         || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1128                         || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1129                 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1130         else if (target->debug_reason == DBG_REASON_DBGRQ)
1131                 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1132         else
1133         {
1134                 LOG_ERROR("unknown debug reason: %i", target->debug_reason);
1135         }
1136
1137         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1138                 return ERROR_FAIL;
1139
1140         for (i=0; i<=15; i++)
1141         {
1142                 LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
1143                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1144                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1145                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1146         }
1147
1148         LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
1149
1150         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1151                 return ERROR_FAIL;
1152
1153         /* exceptions other than USR & SYS have a saved program status register */
1154         if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1155         {
1156                 u32 spsr;
1157                 arm7_9->read_xpsr(target, &spsr, 1);
1158                 jtag_execute_queue();
1159                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1160                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1161                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1162         }
1163
1164         /* r0 and r15 (pc) have to be restored later */
1165         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1166         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1167
1168         if ((retval = jtag_execute_queue()) != ERROR_OK)
1169                 return retval;
1170
1171         if (arm7_9->post_debug_entry)
1172                 arm7_9->post_debug_entry(target);
1173
1174         return ERROR_OK;
1175 }
1176
1177 int arm7_9_full_context(target_t *target)
1178 {
1179         int i;
1180         int retval;
1181         armv4_5_common_t *armv4_5 = target->arch_info;
1182         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1183
1184         LOG_DEBUG("-");
1185
1186         if (target->state != TARGET_HALTED)
1187         {
1188                 LOG_WARNING("target not halted");
1189                 return ERROR_TARGET_NOT_HALTED;
1190         }
1191
1192         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1193                 return ERROR_FAIL;
1194
1195         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1196          * SYS shares registers with User, so we don't touch SYS
1197          */
1198         for(i = 0; i < 6; i++)
1199         {
1200                 u32 mask = 0;
1201                 u32* reg_p[16];
1202                 int j;
1203                 int valid = 1;
1204
1205                 /* check if there are invalid registers in the current mode
1206                  */
1207                 for (j = 0; j <= 16; j++)
1208                 {
1209                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1210                                 valid = 0;
1211                 }
1212
1213                 if (!valid)
1214                 {
1215                         u32 tmp_cpsr;
1216
1217                         /* change processor mode (and mask T bit) */
1218                         tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1219                         tmp_cpsr |= armv4_5_number_to_mode(i);
1220                         tmp_cpsr &= ~0x20;
1221                         arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1222
1223                         for (j = 0; j < 15; j++)
1224                         {
1225                                 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1226                                 {
1227                                         reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1228                                         mask |= 1 << j;
1229                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1230                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1231                                 }
1232                         }
1233
1234                         /* if only the PSR is invalid, mask is all zeroes */
1235                         if (mask)
1236                                 arm7_9->read_core_regs(target, mask, reg_p);
1237
1238                         /* check if the PSR has to be read */
1239                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1240                         {
1241                                 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1242                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1243                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1244                         }
1245                 }
1246         }
1247
1248         /* restore processor mode (mask T bit) */
1249         arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1250
1251         if ((retval = jtag_execute_queue()) != ERROR_OK)
1252         {
1253                 return retval;
1254         }
1255         return ERROR_OK;
1256 }
1257
1258 int arm7_9_restore_context(target_t *target)
1259 {
1260         armv4_5_common_t *armv4_5 = target->arch_info;
1261         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1262         reg_t *reg;
1263         armv4_5_core_reg_t *reg_arch_info;
1264         enum armv4_5_mode current_mode = armv4_5->core_mode;
1265         int i, j;
1266         int dirty;
1267         int mode_change;
1268
1269         LOG_DEBUG("-");
1270
1271         if (target->state != TARGET_HALTED)
1272         {
1273                 LOG_WARNING("target not halted");
1274                 return ERROR_TARGET_NOT_HALTED;
1275         }
1276
1277         if (arm7_9->pre_restore_context)
1278                 arm7_9->pre_restore_context(target);
1279
1280         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1281                 return ERROR_FAIL;
1282
1283         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1284          * SYS shares registers with User, so we don't touch SYS
1285          */
1286         for (i = 0; i < 6; i++)
1287         {
1288                 LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1289                 dirty = 0;
1290                 mode_change = 0;
1291                 /* check if there are dirty registers in the current mode
1292                 */
1293                 for (j = 0; j <= 16; j++)
1294                 {
1295                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1296                         reg_arch_info = reg->arch_info;
1297                         if (reg->dirty == 1)
1298                         {
1299                                 if (reg->valid == 1)
1300                                 {
1301                                         dirty = 1;
1302                                         LOG_DEBUG("examining dirty reg: %s", reg->name);
1303                                         if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1304                                                 && (reg_arch_info->mode != current_mode)
1305                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1306                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1307                                         {
1308                                                 mode_change = 1;
1309                                                 LOG_DEBUG("require mode change");
1310                                         }
1311                                 }
1312                                 else
1313                                 {
1314                                         LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1315                                 }
1316                         }
1317                 }
1318
1319                 if (dirty)
1320                 {
1321                         u32 mask = 0x0;
1322                         int num_regs = 0;
1323                         u32 regs[16];
1324
1325                         if (mode_change)
1326                         {
1327                                 u32 tmp_cpsr;
1328
1329                                 /* change processor mode (mask T bit) */
1330                                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1331                                 tmp_cpsr |= armv4_5_number_to_mode(i);
1332                                 tmp_cpsr &= ~0x20;
1333                                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1334                                 current_mode = armv4_5_number_to_mode(i);
1335                         }
1336
1337                         for (j = 0; j <= 14; j++)
1338                         {
1339                                 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1340                                 reg_arch_info = reg->arch_info;
1341
1342
1343                                 if (reg->dirty == 1)
1344                                 {
1345                                         regs[j] = buf_get_u32(reg->value, 0, 32);
1346                                         mask |= 1 << j;
1347                                         num_regs++;
1348                                         reg->dirty = 0;
1349                                         reg->valid = 1;
1350                                         LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1351                                 }
1352                         }
1353
1354                         if (mask)
1355                         {
1356                                 arm7_9->write_core_regs(target, mask, regs);
1357                         }
1358
1359                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1360                         reg_arch_info = reg->arch_info;
1361                         if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1362                         {
1363                                 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1364                                 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1365                         }
1366                 }
1367         }
1368
1369         if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1370         {
1371                 /* restore processor mode (mask T bit) */
1372                 u32 tmp_cpsr;
1373
1374                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1375                 tmp_cpsr |= armv4_5_number_to_mode(i);
1376                 tmp_cpsr &= ~0x20;
1377                 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1378                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1379         }
1380         else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1381         {
1382                 /* CPSR has been changed, full restore necessary (mask T bit) */
1383                 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1384                 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1385                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1386                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1387         }
1388
1389         /* restore PC */
1390         LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1391         arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1392         armv4_5->core_cache->reg_list[15].dirty = 0;
1393
1394         if (arm7_9->post_restore_context)
1395                 arm7_9->post_restore_context(target);
1396
1397         return ERROR_OK;
1398 }
1399
1400 int arm7_9_restart_core(struct target_s *target)
1401 {
1402         armv4_5_common_t *armv4_5 = target->arch_info;
1403         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1404         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1405
1406         /* set RESTART instruction */
1407         jtag_add_end_state(TAP_RTI);
1408         if (arm7_9->need_bypass_before_restart) {
1409                 arm7_9->need_bypass_before_restart = 0;
1410                 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1411         }
1412         arm_jtag_set_instr(jtag_info, 0x4, NULL);
1413
1414         jtag_add_runtest(1, TAP_RTI);
1415         return jtag_execute_queue();
1416 }
1417
1418 void arm7_9_enable_watchpoints(struct target_s *target)
1419 {
1420         watchpoint_t *watchpoint = target->watchpoints;
1421
1422         while (watchpoint)
1423         {
1424                 if (watchpoint->set == 0)
1425                         arm7_9_set_watchpoint(target, watchpoint);
1426                 watchpoint = watchpoint->next;
1427         }
1428 }
1429
1430 void arm7_9_enable_breakpoints(struct target_s *target)
1431 {
1432         breakpoint_t *breakpoint = target->breakpoints;
1433
1434         /* set any pending breakpoints */
1435         while (breakpoint)
1436         {
1437                 if (breakpoint->set == 0)
1438                         arm7_9_set_breakpoint(target, breakpoint);
1439                 breakpoint = breakpoint->next;
1440         }
1441 }
1442
1443 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1444 {
1445         breakpoint_t *breakpoint = target->breakpoints;
1446         watchpoint_t *watchpoint = target->watchpoints;
1447
1448         /* set any pending breakpoints */
1449         while (breakpoint)
1450         {
1451                 if (breakpoint->set != 0)
1452                         arm7_9_unset_breakpoint(target, breakpoint);
1453                 breakpoint = breakpoint->next;
1454         }
1455
1456         while (watchpoint)
1457         {
1458                 if (watchpoint->set != 0)
1459                         arm7_9_unset_watchpoint(target, watchpoint);
1460                 watchpoint = watchpoint->next;
1461         }
1462 }
1463
1464 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1465 {
1466         armv4_5_common_t *armv4_5 = target->arch_info;
1467         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1468         breakpoint_t *breakpoint = target->breakpoints;
1469         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1470         int err;
1471
1472         LOG_DEBUG("-");
1473
1474         if (target->state != TARGET_HALTED)
1475         {
1476                 LOG_WARNING("target not halted");
1477                 return ERROR_TARGET_NOT_HALTED;
1478         }
1479
1480         if (!debug_execution)
1481         {
1482                 target_free_all_working_areas(target);
1483         }
1484
1485         /* current = 1: continue on current pc, otherwise continue at <address> */
1486         if (!current)
1487                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1488
1489         /* the front-end may request us not to handle breakpoints */
1490         if (handle_breakpoints)
1491         {
1492                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1493                 {
1494                         LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1495                         arm7_9_unset_breakpoint(target, breakpoint);
1496
1497                         LOG_DEBUG("enable single-step");
1498                         arm7_9->enable_single_step(target);
1499
1500                         target->debug_reason = DBG_REASON_SINGLESTEP;
1501
1502                         arm7_9_restore_context(target);
1503
1504                         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1505                                 arm7_9->branch_resume(target);
1506                         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1507                         {
1508                                 arm7_9->branch_resume_thumb(target);
1509                         }
1510                         else
1511                         {
1512                                 LOG_ERROR("unhandled core state");
1513                                 return ERROR_FAIL;
1514                         }
1515
1516                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1517                         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1518                         err = arm7_9_execute_sys_speed(target);
1519
1520                         LOG_DEBUG("disable single-step");
1521                         arm7_9->disable_single_step(target);
1522
1523                         if (err != ERROR_OK)
1524                         {
1525                                 arm7_9_set_breakpoint(target, breakpoint);
1526                                 target->state = TARGET_UNKNOWN;
1527                                 return err;
1528                         }
1529
1530                         arm7_9_debug_entry(target);
1531                         LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1532
1533                         LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1534                         arm7_9_set_breakpoint(target, breakpoint);
1535                 }
1536         }
1537
1538         /* enable any pending breakpoints and watchpoints */
1539         arm7_9_enable_breakpoints(target);
1540         arm7_9_enable_watchpoints(target);
1541
1542         arm7_9_restore_context(target);
1543
1544         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1545         {
1546                 arm7_9->branch_resume(target);
1547         }
1548         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1549         {
1550                 arm7_9->branch_resume_thumb(target);
1551         }
1552         else
1553         {
1554                 LOG_ERROR("unhandled core state");
1555                 return ERROR_FAIL;
1556         }
1557
1558         /* deassert DBGACK and INTDIS */
1559         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1560         /* INTDIS only when we really resume, not during debug execution */
1561         if (!debug_execution)
1562                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1563         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1564
1565         arm7_9_restart_core(target);
1566
1567         target->debug_reason = DBG_REASON_NOTHALTED;
1568
1569         if (!debug_execution)
1570         {
1571                 /* registers are now invalid */
1572                 armv4_5_invalidate_core_regs(target);
1573                 target->state = TARGET_RUNNING;
1574                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1575         }
1576         else
1577         {
1578                 target->state = TARGET_DEBUG_RUNNING;
1579                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1580         }
1581
1582         LOG_DEBUG("target resumed");
1583
1584         return ERROR_OK;
1585 }
1586
1587 void arm7_9_enable_eice_step(target_t *target)
1588 {
1589         armv4_5_common_t *armv4_5 = target->arch_info;
1590         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1591
1592         /* setup an inverse breakpoint on the current PC
1593         * - comparator 1 matches the current address
1594         * - rangeout from comparator 1 is connected to comparator 0 rangein
1595         * - comparator 0 matches any address, as long as rangein is low */
1596         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1597         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1598         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1599         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
1600         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1601         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1602         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1603         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1604         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1605 }
1606
1607 void arm7_9_disable_eice_step(target_t *target)
1608 {
1609         armv4_5_common_t *armv4_5 = target->arch_info;
1610         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1611
1612         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1613         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1614         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1615         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1616         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1617         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1618         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1619         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1620         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1621 }
1622
1623 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1624 {
1625         armv4_5_common_t *armv4_5 = target->arch_info;
1626         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1627         breakpoint_t *breakpoint = NULL;
1628         int err;
1629
1630         if (target->state != TARGET_HALTED)
1631         {
1632                 LOG_WARNING("target not halted");
1633                 return ERROR_TARGET_NOT_HALTED;
1634         }
1635
1636         /* current = 1: continue on current pc, otherwise continue at <address> */
1637         if (!current)
1638                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1639
1640         /* the front-end may request us not to handle breakpoints */
1641         if (handle_breakpoints)
1642                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1643                         arm7_9_unset_breakpoint(target, breakpoint);
1644
1645         target->debug_reason = DBG_REASON_SINGLESTEP;
1646
1647         arm7_9_restore_context(target);
1648
1649         arm7_9->enable_single_step(target);
1650
1651         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1652         {
1653                 arm7_9->branch_resume(target);
1654         }
1655         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1656         {
1657                 arm7_9->branch_resume_thumb(target);
1658         }
1659         else
1660         {
1661                 LOG_ERROR("unhandled core state");
1662                 return ERROR_FAIL;
1663         }
1664
1665         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1666
1667         err = arm7_9_execute_sys_speed(target);
1668         arm7_9->disable_single_step(target);
1669
1670         /* registers are now invalid */
1671         armv4_5_invalidate_core_regs(target);
1672
1673         if (err != ERROR_OK)
1674         {
1675                 target->state = TARGET_UNKNOWN;
1676         } else {
1677                 arm7_9_debug_entry(target);
1678                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1679                 LOG_DEBUG("target stepped");
1680         }
1681
1682         if (breakpoint)
1683                 arm7_9_set_breakpoint(target, breakpoint);
1684
1685         return err;
1686
1687 }
1688
1689 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1690 {
1691         u32* reg_p[16];
1692         u32 value;
1693         int retval;
1694         armv4_5_common_t *armv4_5 = target->arch_info;
1695         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1696
1697         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1698                 return ERROR_FAIL;
1699
1700         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1701
1702         if ((num < 0) || (num > 16))
1703                 return ERROR_INVALID_ARGUMENTS;
1704
1705         if ((mode != ARMV4_5_MODE_ANY)
1706                         && (mode != armv4_5->core_mode)
1707                         && (reg_mode != ARMV4_5_MODE_ANY))
1708         {
1709                 u32 tmp_cpsr;
1710
1711                 /* change processor mode (mask T bit) */
1712                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1713                 tmp_cpsr |= mode;
1714                 tmp_cpsr &= ~0x20;
1715                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1716         }
1717
1718         if ((num >= 0) && (num <= 15))
1719         {
1720                 /* read a normal core register */
1721                 reg_p[num] = &value;
1722
1723                 arm7_9->read_core_regs(target, 1 << num, reg_p);
1724         }
1725         else
1726         {
1727                 /* read a program status register
1728                  * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1729                  */
1730                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1731                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1732
1733                 arm7_9->read_xpsr(target, &value, spsr);
1734         }
1735
1736         if ((retval = jtag_execute_queue()) != ERROR_OK)
1737         {
1738                 return retval;
1739         }
1740
1741         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1742         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1743         buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1744
1745         if ((mode != ARMV4_5_MODE_ANY)
1746                         && (mode != armv4_5->core_mode)
1747                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1748                 /* restore processor mode (mask T bit) */
1749                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1750         }
1751
1752         return ERROR_OK;
1753
1754 }
1755
1756 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1757 {
1758         u32 reg[16];
1759         armv4_5_common_t *armv4_5 = target->arch_info;
1760         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1761
1762         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1763                 return ERROR_FAIL;
1764
1765         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1766
1767         if ((num < 0) || (num > 16))
1768                 return ERROR_INVALID_ARGUMENTS;
1769
1770         if ((mode != ARMV4_5_MODE_ANY)
1771                         && (mode != armv4_5->core_mode)
1772                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1773                 u32 tmp_cpsr;
1774
1775                 /* change processor mode (mask T bit) */
1776                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1777                 tmp_cpsr |= mode;
1778                 tmp_cpsr &= ~0x20;
1779                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1780         }
1781
1782         if ((num >= 0) && (num <= 15))
1783         {
1784                 /* write a normal core register */
1785                 reg[num] = value;
1786
1787                 arm7_9->write_core_regs(target, 1 << num, reg);
1788         }
1789         else
1790         {
1791                 /* write a program status register
1792                 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1793                 */
1794                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1795                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1796
1797                 /* if we're writing the CPSR, mask the T bit */
1798                 if (!spsr)
1799                         value &= ~0x20;
1800
1801                 arm7_9->write_xpsr(target, value, spsr);
1802         }
1803
1804         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1805         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1806
1807         if ((mode != ARMV4_5_MODE_ANY)
1808                         && (mode != armv4_5->core_mode)
1809                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1810                 /* restore processor mode (mask T bit) */
1811                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1812         }
1813
1814         return jtag_execute_queue();
1815 }
1816
1817 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1818 {
1819         armv4_5_common_t *armv4_5 = target->arch_info;
1820         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1821
1822         u32 reg[16];
1823         int num_accesses = 0;
1824         int thisrun_accesses;
1825         int i;
1826         u32 cpsr;
1827         int retval;
1828         int last_reg = 0;
1829
1830         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1831
1832         if (target->state != TARGET_HALTED)
1833         {
1834                 LOG_WARNING("target not halted");
1835                 return ERROR_TARGET_NOT_HALTED;
1836         }
1837
1838         /* sanitize arguments */
1839         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1840                 return ERROR_INVALID_ARGUMENTS;
1841
1842         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1843                 return ERROR_TARGET_UNALIGNED_ACCESS;
1844
1845         /* load the base register with the address of the first word */
1846         reg[0] = address;
1847         arm7_9->write_core_regs(target, 0x1, reg);
1848
1849         switch (size)
1850         {
1851                 case 4:
1852                         while (num_accesses < count)
1853                         {
1854                                 u32 reg_list;
1855                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1856                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1857
1858                                 if (last_reg <= thisrun_accesses)
1859                                         last_reg = thisrun_accesses;
1860
1861                                 arm7_9->load_word_regs(target, reg_list);
1862
1863                                 /* fast memory reads are only safe when the target is running
1864                                  * from a sufficiently high clock (32 kHz is usually too slow)
1865                                  */
1866                                 if (arm7_9->fast_memory_access)
1867                                         arm7_9_execute_fast_sys_speed(target);
1868                                 else
1869                                         arm7_9_execute_sys_speed(target);
1870
1871                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1872
1873                                 /* advance buffer, count number of accesses */
1874                                 buffer += thisrun_accesses * 4;
1875                                 num_accesses += thisrun_accesses;
1876                         }
1877                         break;
1878                 case 2:
1879                         while (num_accesses < count)
1880                         {
1881                                 u32 reg_list;
1882                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1883                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1884
1885                                 for (i = 1; i <= thisrun_accesses; i++)
1886                                 {
1887                                         if (i > last_reg)
1888                                                 last_reg = i;
1889                                         arm7_9->load_hword_reg(target, i);
1890                                         /* fast memory reads are only safe when the target is running
1891                                          * from a sufficiently high clock (32 kHz is usually too slow)
1892                                          */
1893                                         if (arm7_9->fast_memory_access)
1894                                                 arm7_9_execute_fast_sys_speed(target);
1895                                         else
1896                                                 arm7_9_execute_sys_speed(target);
1897                                 }
1898
1899                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1900
1901                                 /* advance buffer, count number of accesses */
1902                                 buffer += thisrun_accesses * 2;
1903                                 num_accesses += thisrun_accesses;
1904                         }
1905                         break;
1906                 case 1:
1907                         while (num_accesses < count)
1908                         {
1909                                 u32 reg_list;
1910                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1911                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1912
1913                                 for (i = 1; i <= thisrun_accesses; i++)
1914                                 {
1915                                         if (i > last_reg)
1916                                                 last_reg = i;
1917                                         arm7_9->load_byte_reg(target, i);
1918                                         /* fast memory reads are only safe when the target is running
1919                                          * from a sufficiently high clock (32 kHz is usually too slow)
1920                                          */
1921                                         if (arm7_9->fast_memory_access)
1922                                                 arm7_9_execute_fast_sys_speed(target);
1923                                         else
1924                                                 arm7_9_execute_sys_speed(target);
1925                                 }
1926
1927                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1928
1929                                 /* advance buffer, count number of accesses */
1930                                 buffer += thisrun_accesses * 1;
1931                                 num_accesses += thisrun_accesses;
1932                         }
1933                         break;
1934                 default:
1935                         LOG_ERROR("BUG: we shouldn't get here");
1936                         exit(-1);
1937                         break;
1938         }
1939
1940         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1941                 return ERROR_FAIL;
1942
1943         for (i=0; i<=last_reg; i++)
1944                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1945
1946         arm7_9->read_xpsr(target, &cpsr, 0);
1947         if ((retval = jtag_execute_queue()) != ERROR_OK)
1948         {
1949                 LOG_ERROR("JTAG error while reading cpsr");
1950                 return ERROR_TARGET_DATA_ABORT;
1951         }
1952
1953         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1954         {
1955                 LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1956
1957                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1958
1959                 return ERROR_TARGET_DATA_ABORT;
1960         }
1961
1962         return ERROR_OK;
1963 }
1964
1965 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1966 {
1967         armv4_5_common_t *armv4_5 = target->arch_info;
1968         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1969         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1970
1971         u32 reg[16];
1972         int num_accesses = 0;
1973         int thisrun_accesses;
1974         int i;
1975         u32 cpsr;
1976         int retval;
1977         int last_reg = 0;
1978
1979 #ifdef _DEBUG_ARM7_9_
1980         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1981 #endif
1982
1983         if (target->state != TARGET_HALTED)
1984         {
1985                 LOG_WARNING("target not halted");
1986                 return ERROR_TARGET_NOT_HALTED;
1987         }
1988
1989         /* sanitize arguments */
1990         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1991                 return ERROR_INVALID_ARGUMENTS;
1992
1993         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1994                 return ERROR_TARGET_UNALIGNED_ACCESS;
1995
1996         /* load the base register with the address of the first word */
1997         reg[0] = address;
1998         arm7_9->write_core_regs(target, 0x1, reg);
1999
2000         /* Clear DBGACK, to make sure memory fetches work as expected */
2001         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2002         embeddedice_store_reg(dbg_ctrl);
2003
2004         switch (size)
2005         {
2006                 case 4:
2007                         while (num_accesses < count)
2008                         {
2009                                 u32 reg_list;
2010                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2011                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2012
2013                                 for (i = 1; i <= thisrun_accesses; i++)
2014                                 {
2015                                         if (i > last_reg)
2016                                                 last_reg = i;
2017                                         reg[i] = target_buffer_get_u32(target, buffer);
2018                                         buffer += 4;
2019                                 }
2020
2021                                 arm7_9->write_core_regs(target, reg_list, reg);
2022
2023                                 arm7_9->store_word_regs(target, reg_list);
2024
2025                                 /* fast memory writes are only safe when the target is running
2026                                  * from a sufficiently high clock (32 kHz is usually too slow)
2027                                  */
2028                                 if (arm7_9->fast_memory_access)
2029                                         arm7_9_execute_fast_sys_speed(target);
2030                                 else
2031                                         arm7_9_execute_sys_speed(target);
2032
2033                                 num_accesses += thisrun_accesses;
2034                         }
2035                         break;
2036                 case 2:
2037                         while (num_accesses < count)
2038                         {
2039                                 u32 reg_list;
2040                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2041                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2042
2043                                 for (i = 1; i <= thisrun_accesses; i++)
2044                                 {
2045                                         if (i > last_reg)
2046                                                 last_reg = i;
2047                                         reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2048                                         buffer += 2;
2049                                 }
2050
2051                                 arm7_9->write_core_regs(target, reg_list, reg);
2052
2053                                 for (i = 1; i <= thisrun_accesses; i++)
2054                                 {
2055                                         arm7_9->store_hword_reg(target, i);
2056
2057                                         /* fast memory writes are only safe when the target is running
2058                                          * from a sufficiently high clock (32 kHz is usually too slow)
2059                                          */
2060                                         if (arm7_9->fast_memory_access)
2061                                                 arm7_9_execute_fast_sys_speed(target);
2062                                         else
2063                                                 arm7_9_execute_sys_speed(target);
2064                                 }
2065
2066                                 num_accesses += thisrun_accesses;
2067                         }
2068                         break;
2069                 case 1:
2070                         while (num_accesses < count)
2071                         {
2072                                 u32 reg_list;
2073                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2074                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2075
2076                                 for (i = 1; i <= thisrun_accesses; i++)
2077                                 {
2078                                         if (i > last_reg)
2079                                                 last_reg = i;
2080                                         reg[i] = *buffer++ & 0xff;
2081                                 }
2082
2083                                 arm7_9->write_core_regs(target, reg_list, reg);
2084
2085                                 for (i = 1; i <= thisrun_accesses; i++)
2086                                 {
2087                                         arm7_9->store_byte_reg(target, i);
2088                                         /* fast memory writes are only safe when the target is running
2089                                          * from a sufficiently high clock (32 kHz is usually too slow)
2090                                          */
2091                                         if (arm7_9->fast_memory_access)
2092                                                 arm7_9_execute_fast_sys_speed(target);
2093                                         else
2094                                                 arm7_9_execute_sys_speed(target);
2095                                 }
2096
2097                                 num_accesses += thisrun_accesses;
2098                         }
2099                         break;
2100                 default:
2101                         LOG_ERROR("BUG: we shouldn't get here");
2102                         exit(-1);
2103                         break;
2104         }
2105
2106         /* Re-Set DBGACK */
2107         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2108         embeddedice_store_reg(dbg_ctrl);
2109
2110         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2111                 return ERROR_FAIL;
2112
2113         for (i=0; i<=last_reg; i++)
2114                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2115
2116         arm7_9->read_xpsr(target, &cpsr, 0);
2117         if ((retval = jtag_execute_queue()) != ERROR_OK)
2118         {
2119                 LOG_ERROR("JTAG error while reading cpsr");
2120                 return ERROR_TARGET_DATA_ABORT;
2121         }
2122
2123         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2124         {
2125                 LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2126
2127                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2128
2129                 return ERROR_TARGET_DATA_ABORT;
2130         }
2131
2132         return ERROR_OK;
2133 }
2134
2135 static const u32 dcc_code[] =
2136 {
2137         /* MRC      TST         BNE         MRC         STR         B */
2138         0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2139 };
2140
2141 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2142 {
2143         armv4_5_common_t *armv4_5 = target->arch_info;
2144         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2145         enum armv4_5_state core_state = armv4_5->core_state;
2146         u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2147         u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2148         u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2149         int i;
2150
2151         if (!arm7_9->dcc_downloads)
2152                 return target->type->write_memory(target, address, 4, count, buffer);
2153
2154         /* regrab previously allocated working_area, or allocate a new one */
2155         if (!arm7_9->dcc_working_area)
2156         {
2157                 u8 dcc_code_buf[6 * 4];
2158
2159                 /* make sure we have a working area */
2160                 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2161                 {
2162                         LOG_INFO("no working area available, falling back to memory writes");
2163                         return target->type->write_memory(target, address, 4, count, buffer);
2164                 }
2165
2166                 /* copy target instructions to target endianness */
2167                 for (i = 0; i < 6; i++)
2168                 {
2169                         target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2170                 }
2171
2172                 /* write DCC code to working area */
2173                 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2174         }
2175
2176         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2177         armv4_5->core_cache->reg_list[0].valid = 1;
2178         armv4_5->core_cache->reg_list[0].dirty = 1;
2179         armv4_5->core_state = ARMV4_5_STATE_ARM;
2180
2181         arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2182
2183         int little=target->endianness==TARGET_LITTLE_ENDIAN;
2184         if (count>2)
2185         {
2186                 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2187                    core function repeated.
2188                  */
2189                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2190                 buffer+=4;
2191
2192                 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2193                 u8 reg_addr = ice_reg->addr & 0x1f;
2194                 int chain_pos = ice_reg->jtag_info->chain_pos;
2195                 /* we want the compiler to duplicate the code, which it does not
2196                  * do automatically.
2197                  */
2198                 if (little)
2199                 {
2200                         for (i = 1; i < count - 1; i++)
2201                         {
2202                                 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2203                                 buffer += 4;
2204                         }
2205                 } else
2206                 {
2207                         for (i = 1; i < count - 1; i++)
2208                         {
2209                                 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2210                                 buffer += 4;
2211                         }
2212                 }
2213                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2214         } else
2215         {
2216                 for (i = 0; i < count; i++)
2217                 {
2218                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2219                         buffer += 4;
2220                 }
2221         }
2222
2223         target_halt(target);
2224
2225         for (i=0; i<100; i++)
2226         {
2227                 target_poll(target);
2228                 if (target->state == TARGET_HALTED)
2229                         break;
2230                 usleep(1000); /* sleep 1ms */
2231         }
2232         if (i == 100)
2233         {
2234                 LOG_ERROR("bulk write timed out, target not halted");
2235                 return ERROR_TARGET_TIMEOUT;
2236         }
2237
2238         /* restore target state */
2239         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2240         armv4_5->core_cache->reg_list[0].valid = 1;
2241         armv4_5->core_cache->reg_list[0].dirty = 1;
2242         buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2243         armv4_5->core_cache->reg_list[1].valid = 1;
2244         armv4_5->core_cache->reg_list[1].dirty = 1;
2245         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2246         armv4_5->core_cache->reg_list[15].valid = 1;
2247         armv4_5->core_cache->reg_list[15].dirty = 1;
2248         armv4_5->core_state = core_state;
2249
2250         return ERROR_OK;
2251 }
2252
2253 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2254 {
2255         working_area_t *crc_algorithm;
2256         armv4_5_algorithm_t armv4_5_info;
2257         reg_param_t reg_params[2];
2258         int retval;
2259
2260         u32 arm7_9_crc_code[] = {
2261                 0xE1A02000,                             /* mov          r2, r0 */
2262                 0xE3E00000,                             /* mov          r0, #0xffffffff */
2263                 0xE1A03001,                             /* mov          r3, r1 */
2264                 0xE3A04000,                             /* mov          r4, #0 */
2265                 0xEA00000B,                             /* b            ncomp */
2266                                                                 /* nbyte: */
2267                 0xE7D21004,                             /* ldrb r1, [r2, r4] */
2268                 0xE59F7030,                             /* ldr          r7, CRC32XOR */
2269                 0xE0200C01,                             /* eor          r0, r0, r1, asl 24 */
2270                 0xE3A05000,                             /* mov          r5, #0 */
2271                                                                 /* loop: */
2272                 0xE3500000,                             /* cmp          r0, #0 */
2273                 0xE1A06080,                             /* mov          r6, r0, asl #1 */
2274                 0xE2855001,                             /* add          r5, r5, #1 */
2275                 0xE1A00006,                             /* mov          r0, r6 */
2276                 0xB0260007,                             /* eorlt        r0, r6, r7 */
2277                 0xE3550008,                             /* cmp          r5, #8 */
2278                 0x1AFFFFF8,                             /* bne          loop */
2279                 0xE2844001,                             /* add          r4, r4, #1 */
2280                                                                 /* ncomp: */
2281                 0xE1540003,                             /* cmp          r4, r3 */
2282                 0x1AFFFFF1,                             /* bne          nbyte */
2283                                                                 /* end: */
2284                 0xEAFFFFFE,                             /* b            end */
2285                 0x04C11DB7                              /* CRC32XOR:    .word 0x04C11DB7 */
2286         };
2287
2288         int i;
2289
2290         if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2291         {
2292                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2293         }
2294
2295         /* convert flash writing code into a buffer in target endianness */
2296         for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2297                 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2298
2299         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2300         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2301         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2302
2303         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2304         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2305
2306         buf_set_u32(reg_params[0].value, 0, 32, address);
2307         buf_set_u32(reg_params[1].value, 0, 32, count);
2308
2309         if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2310                 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2311         {
2312                 LOG_ERROR("error executing arm7_9 crc algorithm");
2313                 destroy_reg_param(&reg_params[0]);
2314                 destroy_reg_param(&reg_params[1]);
2315                 target_free_working_area(target, crc_algorithm);
2316                 return retval;
2317         }
2318
2319         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2320
2321         destroy_reg_param(&reg_params[0]);
2322         destroy_reg_param(&reg_params[1]);
2323
2324         target_free_working_area(target, crc_algorithm);
2325
2326         return ERROR_OK;
2327 }
2328
2329 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
2330 {
2331         working_area_t *erase_check_algorithm;
2332         reg_param_t reg_params[3];
2333         armv4_5_algorithm_t armv4_5_info;
2334         int retval;
2335         int i;
2336
2337         u32 erase_check_code[] =
2338         {
2339                                                 /* loop: */
2340                 0xe4d03001,             /* ldrb r3, [r0], #1    */
2341                 0xe0022003,             /* and r2, r2, r3               */
2342                 0xe2511001,     /* subs r1, r1, #1              */
2343                 0x1afffffb,             /* bne loop                             */
2344                                                 /* end: */
2345                 0xeafffffe              /* b end                                */
2346         };
2347
2348         /* make sure we have a working area */
2349         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
2350         {
2351                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2352         }
2353
2354         /* convert flash writing code into a buffer in target endianness */
2355         for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
2356                 target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]);
2357
2358         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2359         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2360         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2361
2362         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
2363         buf_set_u32(reg_params[0].value, 0, 32, address);
2364
2365         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2366         buf_set_u32(reg_params[1].value, 0, 32, count);
2367
2368         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
2369         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2370
2371         if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
2372                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
2373         {
2374                 destroy_reg_param(&reg_params[0]);
2375                 destroy_reg_param(&reg_params[1]);
2376                 destroy_reg_param(&reg_params[2]);
2377                 target_free_working_area(target, erase_check_algorithm);
2378                 return 0;
2379         }
2380
2381         *blank = buf_get_u32(reg_params[2].value, 0, 32);
2382
2383         destroy_reg_param(&reg_params[0]);
2384         destroy_reg_param(&reg_params[1]);
2385         destroy_reg_param(&reg_params[2]);
2386
2387         target_free_working_area(target, erase_check_algorithm);
2388
2389         return ERROR_OK;
2390 }
2391
2392 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2393 {
2394         command_t *arm7_9_cmd;
2395
2396         arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2397
2398         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2399         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2400
2401         register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2402
2403         register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2404         register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2405         register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2406                 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2407         register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2408                  COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2409         register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2410                  COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2411         register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2412                 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2413
2414         armv4_5_register_commands(cmd_ctx);
2415
2416         etm_register_commands(cmd_ctx);
2417
2418         return ERROR_OK;
2419 }
2420
2421 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2422 {
2423         u32 value;
2424         int spsr;
2425         int retval;
2426         target_t *target = get_current_target(cmd_ctx);
2427         armv4_5_common_t *armv4_5;
2428         arm7_9_common_t *arm7_9;
2429
2430         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2431         {
2432                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2433                 return ERROR_OK;
2434         }
2435
2436         if (target->state != TARGET_HALTED)
2437         {
2438                 command_print(cmd_ctx, "can't write registers while running");
2439                 return ERROR_OK;
2440         }
2441
2442         if (argc < 2)
2443         {
2444                 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2445                 return ERROR_OK;
2446         }
2447
2448         value = strtoul(args[0], NULL, 0);
2449         spsr = strtol(args[1], NULL, 0);
2450
2451         /* if we're writing the CPSR, mask the T bit */
2452         if (!spsr)
2453                 value &= ~0x20;
2454
2455         arm7_9->write_xpsr(target, value, spsr);
2456         if ((retval = jtag_execute_queue()) != ERROR_OK)
2457         {
2458                 LOG_ERROR("JTAG error while writing to xpsr");
2459                 return retval;
2460         }
2461
2462         return ERROR_OK;
2463 }
2464
2465 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2466 {
2467         u32 value;
2468         int rotate;
2469         int spsr;
2470         int retval;
2471         target_t *target = get_current_target(cmd_ctx);
2472         armv4_5_common_t *armv4_5;
2473         arm7_9_common_t *arm7_9;
2474
2475         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2476         {
2477                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2478                 return ERROR_OK;
2479         }
2480
2481         if (target->state != TARGET_HALTED)
2482         {
2483                 command_print(cmd_ctx, "can't write registers while running");
2484                 return ERROR_OK;
2485         }
2486
2487         if (argc < 3)
2488         {
2489                 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2490                 return ERROR_OK;
2491         }
2492
2493         value = strtoul(args[0], NULL, 0);
2494         rotate = strtol(args[1], NULL, 0);
2495         spsr = strtol(args[2], NULL, 0);
2496
2497         arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2498         if ((retval = jtag_execute_queue()) != ERROR_OK)
2499         {
2500                 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2501                 return retval;
2502         }
2503
2504         return ERROR_OK;
2505 }
2506
2507 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2508 {
2509         u32 value;
2510         u32 mode;
2511         int num;
2512         target_t *target = get_current_target(cmd_ctx);
2513         armv4_5_common_t *armv4_5;
2514         arm7_9_common_t *arm7_9;
2515
2516         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2517         {
2518                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2519                 return ERROR_OK;
2520         }
2521
2522         if (target->state != TARGET_HALTED)
2523         {
2524                 command_print(cmd_ctx, "can't write registers while running");
2525                 return ERROR_OK;
2526         }
2527
2528         if (argc < 3)
2529         {
2530                 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2531                 return ERROR_OK;
2532         }
2533
2534         num = strtol(args[0], NULL, 0);
2535         mode = strtoul(args[1], NULL, 0);
2536         value = strtoul(args[2], NULL, 0);
2537
2538         arm7_9_write_core_reg(target, num, mode, value);
2539
2540         return ERROR_OK;
2541 }
2542
2543 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2544 {
2545         target_t *target = get_current_target(cmd_ctx);
2546         armv4_5_common_t *armv4_5;
2547         arm7_9_common_t *arm7_9;
2548
2549         if (target->state != TARGET_HALTED)
2550         {
2551                 LOG_ERROR("target not halted");
2552                 return ERROR_TARGET_NOT_HALTED;
2553         }
2554
2555         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2556         {
2557                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2558                 return ERROR_OK;
2559         }
2560
2561         if (argc == 0)
2562         {
2563                 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2564                 return ERROR_OK;
2565         }
2566
2567         if (strcmp("enable", args[0]) == 0)
2568         {
2569                 if (arm7_9->sw_bkpts_use_wp)
2570                 {
2571                         arm7_9_enable_sw_bkpts(target);
2572                 }
2573                 else
2574                 {
2575                         arm7_9->sw_bkpts_enabled = 1;
2576                 }
2577         }
2578         else if (strcmp("disable", args[0]) == 0)
2579         {
2580                 if (arm7_9->sw_bkpts_use_wp)
2581                 {
2582                         arm7_9_disable_sw_bkpts(target);
2583                 }
2584                 else
2585                 {
2586                         arm7_9->sw_bkpts_enabled = 0;
2587                 }
2588         }
2589         else
2590         {
2591                 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2592         }
2593
2594         command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2595
2596         return ERROR_OK;
2597 }
2598
2599 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2600 {
2601         target_t *target = get_current_target(cmd_ctx);
2602         armv4_5_common_t *armv4_5;
2603         arm7_9_common_t *arm7_9;
2604
2605         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2606         {
2607                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2608                 return ERROR_OK;
2609         }
2610
2611         if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2612         {
2613                 arm7_9->force_hw_bkpts = 1;
2614                 if (arm7_9->sw_bkpts_use_wp)
2615                 {
2616                         arm7_9_disable_sw_bkpts(target);
2617                 }
2618         }
2619         else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2620         {
2621                 arm7_9->force_hw_bkpts = 0;
2622         }
2623         else
2624         {
2625                 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2626         }
2627
2628         command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2629
2630         return ERROR_OK;
2631 }
2632
2633 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2634 {
2635         target_t *target = get_current_target(cmd_ctx);
2636         armv4_5_common_t *armv4_5;
2637         arm7_9_common_t *arm7_9;
2638
2639         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2640         {
2641                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2642                 return ERROR_OK;
2643         }
2644
2645         if (argc > 0)
2646         {
2647                 if (strcmp("enable", args[0]) == 0)
2648                 {
2649                         arm7_9->use_dbgrq = 1;
2650                 }
2651                 else if (strcmp("disable", args[0]) == 0)
2652                 {
2653                         arm7_9->use_dbgrq = 0;
2654                 }
2655                 else
2656                 {
2657                         command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2658                 }
2659         }
2660
2661         command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2662
2663         return ERROR_OK;
2664 }
2665
2666 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2667 {
2668         target_t *target = get_current_target(cmd_ctx);
2669         armv4_5_common_t *armv4_5;
2670         arm7_9_common_t *arm7_9;
2671
2672         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2673         {
2674                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2675                 return ERROR_OK;
2676         }
2677
2678         if (argc > 0)
2679         {
2680                 if (strcmp("enable", args[0]) == 0)
2681                 {
2682                         arm7_9->fast_memory_access = 1;
2683                 }
2684                 else if (strcmp("disable", args[0]) == 0)
2685                 {
2686                         arm7_9->fast_memory_access = 0;
2687                 }
2688                 else
2689                 {
2690                         command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2691                 }
2692         }
2693
2694         command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2695
2696         return ERROR_OK;
2697 }
2698
2699 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2700 {
2701         target_t *target = get_current_target(cmd_ctx);
2702         armv4_5_common_t *armv4_5;
2703         arm7_9_common_t *arm7_9;
2704
2705         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2706         {
2707                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2708                 return ERROR_OK;
2709         }
2710
2711         if (argc > 0)
2712         {
2713                 if (strcmp("enable", args[0]) == 0)
2714                 {
2715                         arm7_9->dcc_downloads = 1;
2716                 }
2717                 else if (strcmp("disable", args[0]) == 0)
2718                 {
2719                         arm7_9->dcc_downloads = 0;
2720                 }
2721                 else
2722                 {
2723                         command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2724                 }
2725         }
2726
2727         command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2728
2729         return ERROR_OK;
2730 }
2731
2732 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2733 {
2734         armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2735
2736         arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2737
2738         arm_jtag_setup_connection(&arm7_9->jtag_info);
2739         arm7_9->wp_available = 2;
2740         arm7_9->wp0_used = 0;
2741         arm7_9->wp1_used = 0;
2742         arm7_9->force_hw_bkpts = 0;
2743         arm7_9->use_dbgrq = 0;
2744
2745         arm7_9->etm_ctx = NULL;
2746         arm7_9->has_single_step = 0;
2747         arm7_9->has_monitor_mode = 0;
2748         arm7_9->has_vector_catch = 0;
2749
2750         arm7_9->debug_entry_from_reset = 0;
2751
2752         arm7_9->dcc_working_area = NULL;
2753
2754         arm7_9->fast_memory_access = fast_and_dangerous;
2755         arm7_9->dcc_downloads = fast_and_dangerous;
2756
2757         arm7_9->need_bypass_before_restart = 0;
2758
2759         armv4_5->arch_info = arm7_9;
2760         armv4_5->read_core_reg = arm7_9_read_core_reg;
2761         armv4_5->write_core_reg = arm7_9_write_core_reg;
2762         armv4_5->full_context = arm7_9_full_context;
2763
2764         armv4_5_init_arch_info(target, armv4_5);
2765
2766         target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
2767
2768         return ERROR_OK;
2769 }