1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
28 #include "target_request.h"
33 #include "arm7_9_common.h"
34 #include "breakpoints.h"
40 #include <sys/types.h>
45 int arm7_9_debug_entry(target_t *target);
46 int arm7_9_enable_sw_bkpts(struct target_s *target);
48 /* command handler forward declarations */
49 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
60 int arm7_9_reinit_embeddedice(target_t *target)
62 armv4_5_common_t *armv4_5 = target->arch_info;
63 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
65 breakpoint_t *breakpoint = target->breakpoints;
67 arm7_9->wp_available = 2;
71 /* mark all hardware breakpoints as unset */
74 if (breakpoint->type == BKPT_HARD)
78 breakpoint = breakpoint->next;
81 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
83 arm7_9->sw_bkpts_enabled = 0;
84 arm7_9_enable_sw_bkpts(target);
90 /* set things up after a reset / on startup */
91 int arm7_9_setup(target_t *target)
93 /* a test-logic reset have occured
94 * the EmbeddedICE registers have been reset
95 * hardware breakpoints have been cleared
97 return arm7_9_reinit_embeddedice(target);
100 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
102 armv4_5_common_t *armv4_5 = target->arch_info;
103 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
105 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
110 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
115 *armv4_5_p = armv4_5;
121 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
123 armv4_5_common_t *armv4_5 = target->arch_info;
124 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
126 if (target->state != TARGET_HALTED)
128 LOG_WARNING("target not halted");
129 return ERROR_TARGET_NOT_HALTED;
132 if (arm7_9->force_hw_bkpts)
133 breakpoint->type = BKPT_HARD;
137 LOG_WARNING("breakpoint already set");
141 if (breakpoint->type == BKPT_HARD)
143 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
144 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
145 if (!arm7_9->wp0_used)
147 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
148 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
149 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
150 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
151 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
153 jtag_execute_queue();
154 arm7_9->wp0_used = 1;
157 else if (!arm7_9->wp1_used)
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
162 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
163 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
165 jtag_execute_queue();
166 arm7_9->wp1_used = 1;
171 LOG_ERROR("BUG: no hardware comparator available");
175 else if (breakpoint->type == BKPT_SOFT)
177 if (breakpoint->length == 4)
179 u32 verify = 0xffffffff;
180 /* keep the original instruction in target endianness */
181 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
182 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
183 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
185 target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
186 if (verify != arm7_9->arm_bkpt)
188 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
195 /* keep the original instruction in target endianness */
196 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
197 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
198 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
200 target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
201 if (verify != arm7_9->thumb_bkpt)
203 LOG_ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
214 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
216 armv4_5_common_t *armv4_5 = target->arch_info;
217 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
219 if (target->state != TARGET_HALTED)
221 LOG_WARNING("target not halted");
222 return ERROR_TARGET_NOT_HALTED;
225 if (!breakpoint->set)
227 LOG_WARNING("breakpoint not set");
231 if (breakpoint->type == BKPT_HARD)
233 if (breakpoint->set == 1)
235 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
236 jtag_execute_queue();
237 arm7_9->wp0_used = 0;
239 else if (breakpoint->set == 2)
241 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
242 jtag_execute_queue();
243 arm7_9->wp1_used = 0;
249 /* restore original instruction (kept in target endianness) */
250 if (breakpoint->length == 4)
253 /* check that user program as not modified breakpoint instruction */
254 target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr);
255 if (current_instr==arm7_9->arm_bkpt)
256 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
261 /* check that user program as not modified breakpoint instruction */
262 target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr);
263 if (current_instr==arm7_9->thumb_bkpt)
264 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
272 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
274 armv4_5_common_t *armv4_5 = target->arch_info;
275 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
277 if (target->state != TARGET_HALTED)
279 LOG_WARNING("target not halted");
280 return ERROR_TARGET_NOT_HALTED;
283 if (arm7_9->force_hw_bkpts)
285 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
286 breakpoint->type = BKPT_HARD;
289 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
291 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
292 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
295 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
297 LOG_INFO("no watchpoint unit available for hardware breakpoint");
298 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
301 if ((breakpoint->length != 2) && (breakpoint->length != 4))
303 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
304 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
307 if (breakpoint->type == BKPT_HARD)
308 arm7_9->wp_available--;
313 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
315 armv4_5_common_t *armv4_5 = target->arch_info;
316 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
318 if (target->state != TARGET_HALTED)
320 LOG_WARNING("target not halted");
321 return ERROR_TARGET_NOT_HALTED;
326 arm7_9_unset_breakpoint(target, breakpoint);
329 if (breakpoint->type == BKPT_HARD)
330 arm7_9->wp_available++;
335 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
337 armv4_5_common_t *armv4_5 = target->arch_info;
338 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
342 mask = watchpoint->length - 1;
344 if (target->state != TARGET_HALTED)
346 LOG_WARNING("target not halted");
347 return ERROR_TARGET_NOT_HALTED;
350 if (watchpoint->rw == WPT_ACCESS)
355 if (!arm7_9->wp0_used)
357 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
359 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
360 if( watchpoint->mask != 0xffffffffu )
361 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
363 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
365 jtag_execute_queue();
367 arm7_9->wp0_used = 2;
369 else if (!arm7_9->wp1_used)
371 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
372 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
373 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
374 if( watchpoint->mask != 0xffffffffu )
375 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
376 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
377 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
379 jtag_execute_queue();
381 arm7_9->wp1_used = 2;
385 LOG_ERROR("BUG: no hardware comparator available");
392 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
394 armv4_5_common_t *armv4_5 = target->arch_info;
395 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
397 if (target->state != TARGET_HALTED)
399 LOG_WARNING("target not halted");
400 return ERROR_TARGET_NOT_HALTED;
403 if (!watchpoint->set)
405 LOG_WARNING("breakpoint not set");
409 if (watchpoint->set == 1)
411 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
412 jtag_execute_queue();
413 arm7_9->wp0_used = 0;
415 else if (watchpoint->set == 2)
417 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
418 jtag_execute_queue();
419 arm7_9->wp1_used = 0;
426 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
428 armv4_5_common_t *armv4_5 = target->arch_info;
429 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
431 if (target->state != TARGET_HALTED)
433 LOG_WARNING("target not halted");
434 return ERROR_TARGET_NOT_HALTED;
437 if (arm7_9->wp_available < 1)
439 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
442 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
447 arm7_9->wp_available--;
452 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
454 armv4_5_common_t *armv4_5 = target->arch_info;
455 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
457 if (target->state != TARGET_HALTED)
459 LOG_WARNING("target not halted");
460 return ERROR_TARGET_NOT_HALTED;
465 arm7_9_unset_watchpoint(target, watchpoint);
468 arm7_9->wp_available++;
473 int arm7_9_enable_sw_bkpts(struct target_s *target)
475 armv4_5_common_t *armv4_5 = target->arch_info;
476 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
479 if (arm7_9->sw_bkpts_enabled)
482 if (arm7_9->wp_available < 1)
484 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
487 arm7_9->wp_available--;
489 if (!arm7_9->wp0_used)
491 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
492 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
493 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
494 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
495 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
496 arm7_9->sw_bkpts_enabled = 1;
497 arm7_9->wp0_used = 3;
499 else if (!arm7_9->wp1_used)
501 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
502 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
503 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
504 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
505 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
506 arm7_9->sw_bkpts_enabled = 2;
507 arm7_9->wp1_used = 3;
511 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
515 if ((retval = jtag_execute_queue()) != ERROR_OK)
517 LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
524 int arm7_9_disable_sw_bkpts(struct target_s *target)
526 armv4_5_common_t *armv4_5 = target->arch_info;
527 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
529 if (!arm7_9->sw_bkpts_enabled)
532 if (arm7_9->sw_bkpts_enabled == 1)
534 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
535 arm7_9->sw_bkpts_enabled = 0;
536 arm7_9->wp0_used = 0;
537 arm7_9->wp_available++;
539 else if (arm7_9->sw_bkpts_enabled == 2)
541 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
542 arm7_9->sw_bkpts_enabled = 0;
543 arm7_9->wp1_used = 0;
544 arm7_9->wp_available++;
550 int arm7_9_execute_sys_speed(struct target_s *target)
555 armv4_5_common_t *armv4_5 = target->arch_info;
556 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
557 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
558 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
560 /* set RESTART instruction */
561 jtag_add_end_state(TAP_RTI);
562 if (arm7_9->need_bypass_before_restart) {
563 arm7_9->need_bypass_before_restart = 0;
564 arm_jtag_set_instr(jtag_info, 0xf, NULL);
566 arm_jtag_set_instr(jtag_info, 0x4, NULL);
568 for (timeout=0; timeout<50; timeout++)
570 /* read debug status register */
571 embeddedice_read_reg(dbg_stat);
572 if ((retval = jtag_execute_queue()) != ERROR_OK)
574 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
575 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
581 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
582 return ERROR_TARGET_TIMEOUT;
588 int arm7_9_execute_fast_sys_speed(struct target_s *target)
591 static u8 check_value[4], check_mask[4];
593 armv4_5_common_t *armv4_5 = target->arch_info;
594 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
595 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
596 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
598 /* set RESTART instruction */
599 jtag_add_end_state(TAP_RTI);
600 if (arm7_9->need_bypass_before_restart) {
601 arm7_9->need_bypass_before_restart = 0;
602 arm_jtag_set_instr(jtag_info, 0xf, NULL);
604 arm_jtag_set_instr(jtag_info, 0x4, NULL);
608 /* check for DBGACK and SYSCOMP set (others don't care) */
610 /* NB! These are constants that must be available until after next jtag_execute() and
611 we evaluate the values upon first execution in lieu of setting up these constants
614 buf_set_u32(check_value, 0, 32, 0x9);
615 buf_set_u32(check_mask, 0, 32, 0x9);
619 /* read debug status register */
620 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
625 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
627 armv4_5_common_t *armv4_5 = target->arch_info;
628 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
629 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
633 data = malloc(size * (sizeof(u32)));
635 embeddedice_receive(jtag_info, data, size);
637 for (i = 0; i < size; i++)
639 h_u32_to_le(buffer + (i * 4), data[i]);
647 int arm7_9_handle_target_request(void *priv)
649 target_t *target = priv;
650 if (!target->type->examined)
652 armv4_5_common_t *armv4_5 = target->arch_info;
653 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
654 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
655 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
658 if (!target->dbg_msg_enabled)
661 if (target->state == TARGET_RUNNING)
663 /* read DCC control register */
664 embeddedice_read_reg(dcc_control);
665 jtag_execute_queue();
668 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
672 embeddedice_receive(jtag_info, &request, 1);
673 target_request(target, request);
680 int arm7_9_poll(target_t *target)
683 armv4_5_common_t *armv4_5 = target->arch_info;
684 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
685 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
687 /* read debug status register */
688 embeddedice_read_reg(dbg_stat);
689 if ((retval = jtag_execute_queue()) != ERROR_OK)
694 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
696 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
697 if (target->state == TARGET_UNKNOWN)
699 target->state = TARGET_RUNNING;
700 LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
702 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
705 if (target->state == TARGET_RESET)
707 if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
709 if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
716 target->state = TARGET_HALTED;
718 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
723 reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
724 u32 t=*((u32 *)reg->value);
727 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
731 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
733 if (target->state == TARGET_DEBUG_RUNNING)
735 target->state = TARGET_HALTED;
736 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
739 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
741 if (target->state != TARGET_HALTED)
743 LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
748 if (target->state != TARGET_DEBUG_RUNNING)
749 target->state = TARGET_RUNNING;
756 Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
757 in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
758 while the core is held in reset(SRST). It isn't possible to program the halt
759 condition once reset was asserted, hence a hook that allows the target to set
760 up its reset-halt condition prior to asserting reset.
763 int arm7_9_assert_reset(target_t *target)
765 armv4_5_common_t *armv4_5 = target->arch_info;
766 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
767 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
769 if (!(jtag_reset_config & RESET_HAS_SRST))
771 LOG_ERROR("Can't assert SRST");
775 if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
778 * Some targets do not support communication while SRST is asserted. We need to
779 * set up the reset vector catch here.
781 * If TRST is asserted, then these settings will be reset anyway, so setting them
784 if (arm7_9->has_vector_catch)
786 /* program vector catch register to catch reset vector */
787 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
791 /* program watchpoint unit to match on reset vector address */
792 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
793 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
794 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
795 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
799 /* here we should issue a srst only, but we may have to assert trst as well */
800 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
802 jtag_add_reset(1, 1);
805 jtag_add_reset(0, 1);
809 target->state = TARGET_RESET;
810 jtag_add_sleep(50000);
812 armv4_5_invalidate_core_regs(target);
818 int arm7_9_deassert_reset(target_t *target)
820 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
822 /* deassert reset lines */
823 jtag_add_reset(0, 0);
828 int arm7_9_clear_halt(target_t *target)
830 armv4_5_common_t *armv4_5 = target->arch_info;
831 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
832 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
834 /* we used DBGRQ only if we didn't come out of reset */
835 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
837 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
839 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
840 embeddedice_store_reg(dbg_ctrl);
844 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
846 /* if we came out of reset, and vector catch is supported, we used
847 * vector catch to enter debug state
848 * restore the register in that case
850 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
854 /* restore registers if watchpoint unit 0 was in use
856 if (arm7_9->wp0_used)
858 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
859 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
860 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
862 /* control value always has to be restored, as it was either disabled,
863 * or enabled with possibly different bits
865 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
872 int arm7_9_soft_reset_halt(struct target_s *target)
874 armv4_5_common_t *armv4_5 = target->arch_info;
875 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
876 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
877 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
881 if ((retval=target_halt(target))!=ERROR_OK)
886 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
888 embeddedice_read_reg(dbg_stat);
889 if ((retval=jtag_execute_queue())!=ERROR_OK)
891 /* do not eat all CPU, time out after 1 se*/
897 LOG_ERROR("Failed to halt CPU after 1 sec");
898 return ERROR_TARGET_TIMEOUT;
900 target->state = TARGET_HALTED;
902 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
903 * ensure that DBGRQ is cleared
905 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
906 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
907 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
908 embeddedice_store_reg(dbg_ctrl);
910 arm7_9_clear_halt(target);
912 /* if the target is in Thumb state, change to ARM state */
913 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
915 u32 r0_thumb, pc_thumb;
916 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
917 /* Entered debug from Thumb mode */
918 armv4_5->core_state = ARMV4_5_STATE_THUMB;
919 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
922 /* all register content is now invalid */
923 armv4_5_invalidate_core_regs(target);
925 /* SVC, ARM state, IRQ and FIQ disabled */
926 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
927 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
928 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
930 /* start fetching from 0x0 */
931 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
932 armv4_5->core_cache->reg_list[15].dirty = 1;
933 armv4_5->core_cache->reg_list[15].valid = 1;
935 armv4_5->core_mode = ARMV4_5_MODE_SVC;
936 armv4_5->core_state = ARMV4_5_STATE_ARM;
938 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
941 /* reset registers */
942 for (i = 0; i <= 14; i++)
944 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
945 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
946 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
949 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
954 int arm7_9_halt(target_t *target)
956 armv4_5_common_t *armv4_5 = target->arch_info;
957 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
958 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
960 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
962 if (target->state == TARGET_HALTED)
964 LOG_DEBUG("target was already halted");
968 if (target->state == TARGET_UNKNOWN)
970 LOG_WARNING("target was in unknown state when halt was requested");
973 if (target->state == TARGET_RESET)
975 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
977 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
978 return ERROR_TARGET_FAILURE;
982 /* we came here in a reset_halt or reset_init sequence
983 * debug entry was already prepared in arm7_9_prepare_reset_halt()
985 target->debug_reason = DBG_REASON_DBGRQ;
991 if (arm7_9->use_dbgrq)
993 /* program EmbeddedICE Debug Control Register to assert DBGRQ
995 if (arm7_9->set_special_dbgrq) {
996 arm7_9->set_special_dbgrq(target);
998 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
999 embeddedice_store_reg(dbg_ctrl);
1004 /* program watchpoint unit to match on any address
1006 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1007 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1008 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1009 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
1012 target->debug_reason = DBG_REASON_DBGRQ;
1017 int arm7_9_debug_entry(target_t *target)
1022 u32 r0_thumb, pc_thumb;
1025 /* get pointers to arch-specific information */
1026 armv4_5_common_t *armv4_5 = target->arch_info;
1027 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1028 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1029 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1031 #ifdef _DEBUG_ARM7_9_
1035 if (arm7_9->pre_debug_entry)
1036 arm7_9->pre_debug_entry(target);
1038 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1039 * ensure that DBGRQ is cleared
1041 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1042 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1043 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1044 embeddedice_store_reg(dbg_ctrl);
1046 arm7_9_clear_halt(target);
1048 if ((retval = jtag_execute_queue()) != ERROR_OK)
1053 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1057 if (target->state != TARGET_HALTED)
1059 LOG_WARNING("target not halted");
1060 return ERROR_TARGET_NOT_HALTED;
1063 /* if the target is in Thumb state, change to ARM state */
1064 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1066 LOG_DEBUG("target entered debug from Thumb state");
1067 /* Entered debug from Thumb mode */
1068 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1069 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1070 LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1074 LOG_DEBUG("target entered debug from ARM state");
1075 /* Entered debug from ARM mode */
1076 armv4_5->core_state = ARMV4_5_STATE_ARM;
1079 for (i = 0; i < 16; i++)
1080 context_p[i] = &context[i];
1081 /* save core registers (r0 - r15 of current core mode) */
1082 arm7_9->read_core_regs(target, 0xffff, context_p);
1084 arm7_9->read_xpsr(target, &cpsr, 0);
1086 if ((retval = jtag_execute_queue()) != ERROR_OK)
1089 /* if the core has been executing in Thumb state, set the T bit */
1090 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1093 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1094 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1095 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1097 armv4_5->core_mode = cpsr & 0x1f;
1099 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1101 target->state = TARGET_UNKNOWN;
1102 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1103 return ERROR_TARGET_FAILURE;
1106 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1108 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1110 LOG_DEBUG("thumb state, applying fixups");
1111 context[0] = r0_thumb;
1112 context[15] = pc_thumb;
1113 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1115 /* adjust value stored by STM */
1116 context[15] -= 3 * 4;
1119 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1120 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1121 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1122 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1123 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1124 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1125 else if (target->debug_reason == DBG_REASON_DBGRQ)
1126 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1129 LOG_ERROR("unknown debug reason: %i", target->debug_reason);
1132 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1135 for (i=0; i<=15; i++)
1137 LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
1138 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1139 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1140 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1143 LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
1145 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1148 /* exceptions other than USR & SYS have a saved program status register */
1149 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1152 arm7_9->read_xpsr(target, &spsr, 1);
1153 jtag_execute_queue();
1154 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1155 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1156 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1159 /* r0 and r15 (pc) have to be restored later */
1160 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1161 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1163 if ((retval = jtag_execute_queue()) != ERROR_OK)
1166 if (arm7_9->post_debug_entry)
1167 arm7_9->post_debug_entry(target);
1172 int arm7_9_full_context(target_t *target)
1176 armv4_5_common_t *armv4_5 = target->arch_info;
1177 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1181 if (target->state != TARGET_HALTED)
1183 LOG_WARNING("target not halted");
1184 return ERROR_TARGET_NOT_HALTED;
1187 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1190 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1191 * SYS shares registers with User, so we don't touch SYS
1193 for(i = 0; i < 6; i++)
1200 /* check if there are invalid registers in the current mode
1202 for (j = 0; j <= 16; j++)
1204 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1212 /* change processor mode (and mask T bit) */
1213 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1214 tmp_cpsr |= armv4_5_number_to_mode(i);
1216 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1218 for (j = 0; j < 15; j++)
1220 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1222 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1224 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1225 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1229 /* if only the PSR is invalid, mask is all zeroes */
1231 arm7_9->read_core_regs(target, mask, reg_p);
1233 /* check if the PSR has to be read */
1234 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1236 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1237 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1238 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1243 /* restore processor mode (mask T bit) */
1244 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1246 if ((retval = jtag_execute_queue()) != ERROR_OK)
1253 int arm7_9_restore_context(target_t *target)
1255 armv4_5_common_t *armv4_5 = target->arch_info;
1256 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1258 armv4_5_core_reg_t *reg_arch_info;
1259 enum armv4_5_mode current_mode = armv4_5->core_mode;
1266 if (target->state != TARGET_HALTED)
1268 LOG_WARNING("target not halted");
1269 return ERROR_TARGET_NOT_HALTED;
1272 if (arm7_9->pre_restore_context)
1273 arm7_9->pre_restore_context(target);
1275 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1278 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1279 * SYS shares registers with User, so we don't touch SYS
1281 for (i = 0; i < 6; i++)
1283 LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1286 /* check if there are dirty registers in the current mode
1288 for (j = 0; j <= 16; j++)
1290 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1291 reg_arch_info = reg->arch_info;
1292 if (reg->dirty == 1)
1294 if (reg->valid == 1)
1297 LOG_DEBUG("examining dirty reg: %s", reg->name);
1298 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1299 && (reg_arch_info->mode != current_mode)
1300 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1301 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1304 LOG_DEBUG("require mode change");
1309 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1324 /* change processor mode (mask T bit) */
1325 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1326 tmp_cpsr |= armv4_5_number_to_mode(i);
1328 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1329 current_mode = armv4_5_number_to_mode(i);
1332 for (j = 0; j <= 14; j++)
1334 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1335 reg_arch_info = reg->arch_info;
1338 if (reg->dirty == 1)
1340 regs[j] = buf_get_u32(reg->value, 0, 32);
1345 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1351 arm7_9->write_core_regs(target, mask, regs);
1354 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1355 reg_arch_info = reg->arch_info;
1356 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1358 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1359 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1364 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1366 /* restore processor mode (mask T bit) */
1369 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1370 tmp_cpsr |= armv4_5_number_to_mode(i);
1372 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1373 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1375 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1377 /* CPSR has been changed, full restore necessary (mask T bit) */
1378 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1379 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1380 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1381 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1385 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1386 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1387 armv4_5->core_cache->reg_list[15].dirty = 0;
1389 if (arm7_9->post_restore_context)
1390 arm7_9->post_restore_context(target);
1395 int arm7_9_restart_core(struct target_s *target)
1397 armv4_5_common_t *armv4_5 = target->arch_info;
1398 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1399 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1401 /* set RESTART instruction */
1402 jtag_add_end_state(TAP_RTI);
1403 if (arm7_9->need_bypass_before_restart) {
1404 arm7_9->need_bypass_before_restart = 0;
1405 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1407 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1409 jtag_add_runtest(1, TAP_RTI);
1410 return jtag_execute_queue();
1413 void arm7_9_enable_watchpoints(struct target_s *target)
1415 watchpoint_t *watchpoint = target->watchpoints;
1419 if (watchpoint->set == 0)
1420 arm7_9_set_watchpoint(target, watchpoint);
1421 watchpoint = watchpoint->next;
1425 void arm7_9_enable_breakpoints(struct target_s *target)
1427 breakpoint_t *breakpoint = target->breakpoints;
1429 /* set any pending breakpoints */
1432 if (breakpoint->set == 0)
1433 arm7_9_set_breakpoint(target, breakpoint);
1434 breakpoint = breakpoint->next;
1438 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1440 breakpoint_t *breakpoint = target->breakpoints;
1441 watchpoint_t *watchpoint = target->watchpoints;
1443 /* set any pending breakpoints */
1446 if (breakpoint->set != 0)
1447 arm7_9_unset_breakpoint(target, breakpoint);
1448 breakpoint = breakpoint->next;
1453 if (watchpoint->set != 0)
1454 arm7_9_unset_watchpoint(target, watchpoint);
1455 watchpoint = watchpoint->next;
1459 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1461 armv4_5_common_t *armv4_5 = target->arch_info;
1462 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1463 breakpoint_t *breakpoint = target->breakpoints;
1464 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1469 if (target->state != TARGET_HALTED)
1471 LOG_WARNING("target not halted");
1472 return ERROR_TARGET_NOT_HALTED;
1475 if (!debug_execution)
1477 target_free_all_working_areas(target);
1480 /* current = 1: continue on current pc, otherwise continue at <address> */
1482 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1484 /* the front-end may request us not to handle breakpoints */
1485 if (handle_breakpoints)
1487 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1489 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1490 arm7_9_unset_breakpoint(target, breakpoint);
1492 LOG_DEBUG("enable single-step");
1493 arm7_9->enable_single_step(target);
1495 target->debug_reason = DBG_REASON_SINGLESTEP;
1497 arm7_9_restore_context(target);
1499 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1500 arm7_9->branch_resume(target);
1501 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1503 arm7_9->branch_resume_thumb(target);
1507 LOG_ERROR("unhandled core state");
1511 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1512 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1513 err = arm7_9_execute_sys_speed(target);
1515 LOG_DEBUG("disable single-step");
1516 arm7_9->disable_single_step(target);
1518 if (err != ERROR_OK)
1520 arm7_9_set_breakpoint(target, breakpoint);
1521 target->state = TARGET_UNKNOWN;
1525 arm7_9_debug_entry(target);
1526 LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1528 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1529 arm7_9_set_breakpoint(target, breakpoint);
1533 /* enable any pending breakpoints and watchpoints */
1534 arm7_9_enable_breakpoints(target);
1535 arm7_9_enable_watchpoints(target);
1537 arm7_9_restore_context(target);
1539 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1541 arm7_9->branch_resume(target);
1543 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1545 arm7_9->branch_resume_thumb(target);
1549 LOG_ERROR("unhandled core state");
1553 /* deassert DBGACK and INTDIS */
1554 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1555 /* INTDIS only when we really resume, not during debug execution */
1556 if (!debug_execution)
1557 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1558 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1560 arm7_9_restart_core(target);
1562 target->debug_reason = DBG_REASON_NOTHALTED;
1564 if (!debug_execution)
1566 /* registers are now invalid */
1567 armv4_5_invalidate_core_regs(target);
1568 target->state = TARGET_RUNNING;
1569 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1573 target->state = TARGET_DEBUG_RUNNING;
1574 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1577 LOG_DEBUG("target resumed");
1582 void arm7_9_enable_eice_step(target_t *target)
1584 armv4_5_common_t *armv4_5 = target->arch_info;
1585 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1587 /* setup an inverse breakpoint on the current PC
1588 * - comparator 1 matches the current address
1589 * - rangeout from comparator 1 is connected to comparator 0 rangein
1590 * - comparator 0 matches any address, as long as rangein is low */
1591 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1592 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1593 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1594 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1595 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1596 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1597 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1598 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1599 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1602 void arm7_9_disable_eice_step(target_t *target)
1604 armv4_5_common_t *armv4_5 = target->arch_info;
1605 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1607 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1608 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1609 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1610 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1611 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1612 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1613 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1614 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1615 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1618 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1620 armv4_5_common_t *armv4_5 = target->arch_info;
1621 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1622 breakpoint_t *breakpoint = NULL;
1625 if (target->state != TARGET_HALTED)
1627 LOG_WARNING("target not halted");
1628 return ERROR_TARGET_NOT_HALTED;
1631 /* current = 1: continue on current pc, otherwise continue at <address> */
1633 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1635 /* the front-end may request us not to handle breakpoints */
1636 if (handle_breakpoints)
1637 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1638 arm7_9_unset_breakpoint(target, breakpoint);
1640 target->debug_reason = DBG_REASON_SINGLESTEP;
1642 arm7_9_restore_context(target);
1644 arm7_9->enable_single_step(target);
1646 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1648 arm7_9->branch_resume(target);
1650 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1652 arm7_9->branch_resume_thumb(target);
1656 LOG_ERROR("unhandled core state");
1660 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1662 err = arm7_9_execute_sys_speed(target);
1663 arm7_9->disable_single_step(target);
1665 /* registers are now invalid */
1666 armv4_5_invalidate_core_regs(target);
1668 if (err != ERROR_OK)
1670 target->state = TARGET_UNKNOWN;
1672 arm7_9_debug_entry(target);
1673 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1674 LOG_DEBUG("target stepped");
1678 arm7_9_set_breakpoint(target, breakpoint);
1684 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1689 armv4_5_common_t *armv4_5 = target->arch_info;
1690 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1692 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1695 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1697 if ((num < 0) || (num > 16))
1698 return ERROR_INVALID_ARGUMENTS;
1700 if ((mode != ARMV4_5_MODE_ANY)
1701 && (mode != armv4_5->core_mode)
1702 && (reg_mode != ARMV4_5_MODE_ANY))
1706 /* change processor mode (mask T bit) */
1707 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1710 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1713 if ((num >= 0) && (num <= 15))
1715 /* read a normal core register */
1716 reg_p[num] = &value;
1718 arm7_9->read_core_regs(target, 1 << num, reg_p);
1722 /* read a program status register
1723 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1725 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1726 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1728 arm7_9->read_xpsr(target, &value, spsr);
1731 if ((retval = jtag_execute_queue()) != ERROR_OK)
1736 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1737 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1738 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1740 if ((mode != ARMV4_5_MODE_ANY)
1741 && (mode != armv4_5->core_mode)
1742 && (reg_mode != ARMV4_5_MODE_ANY)) {
1743 /* restore processor mode (mask T bit) */
1744 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1751 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1754 armv4_5_common_t *armv4_5 = target->arch_info;
1755 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1757 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1760 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1762 if ((num < 0) || (num > 16))
1763 return ERROR_INVALID_ARGUMENTS;
1765 if ((mode != ARMV4_5_MODE_ANY)
1766 && (mode != armv4_5->core_mode)
1767 && (reg_mode != ARMV4_5_MODE_ANY)) {
1770 /* change processor mode (mask T bit) */
1771 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1774 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1777 if ((num >= 0) && (num <= 15))
1779 /* write a normal core register */
1782 arm7_9->write_core_regs(target, 1 << num, reg);
1786 /* write a program status register
1787 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1789 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1790 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1792 /* if we're writing the CPSR, mask the T bit */
1796 arm7_9->write_xpsr(target, value, spsr);
1799 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1800 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1802 if ((mode != ARMV4_5_MODE_ANY)
1803 && (mode != armv4_5->core_mode)
1804 && (reg_mode != ARMV4_5_MODE_ANY)) {
1805 /* restore processor mode (mask T bit) */
1806 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1809 return jtag_execute_queue();
1812 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1814 armv4_5_common_t *armv4_5 = target->arch_info;
1815 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1818 int num_accesses = 0;
1819 int thisrun_accesses;
1825 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1827 if (target->state != TARGET_HALTED)
1829 LOG_WARNING("target not halted");
1830 return ERROR_TARGET_NOT_HALTED;
1833 /* sanitize arguments */
1834 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1835 return ERROR_INVALID_ARGUMENTS;
1837 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1838 return ERROR_TARGET_UNALIGNED_ACCESS;
1840 /* load the base register with the address of the first word */
1842 arm7_9->write_core_regs(target, 0x1, reg);
1847 while (num_accesses < count)
1850 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1851 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1853 if (last_reg <= thisrun_accesses)
1854 last_reg = thisrun_accesses;
1856 arm7_9->load_word_regs(target, reg_list);
1858 /* fast memory reads are only safe when the target is running
1859 * from a sufficiently high clock (32 kHz is usually too slow)
1861 if (arm7_9->fast_memory_access)
1862 arm7_9_execute_fast_sys_speed(target);
1864 arm7_9_execute_sys_speed(target);
1866 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1868 /* advance buffer, count number of accesses */
1869 buffer += thisrun_accesses * 4;
1870 num_accesses += thisrun_accesses;
1874 while (num_accesses < count)
1877 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1878 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1880 for (i = 1; i <= thisrun_accesses; i++)
1884 arm7_9->load_hword_reg(target, i);
1885 /* fast memory reads are only safe when the target is running
1886 * from a sufficiently high clock (32 kHz is usually too slow)
1888 if (arm7_9->fast_memory_access)
1889 arm7_9_execute_fast_sys_speed(target);
1891 arm7_9_execute_sys_speed(target);
1894 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1896 /* advance buffer, count number of accesses */
1897 buffer += thisrun_accesses * 2;
1898 num_accesses += thisrun_accesses;
1902 while (num_accesses < count)
1905 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1906 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1908 for (i = 1; i <= thisrun_accesses; i++)
1912 arm7_9->load_byte_reg(target, i);
1913 /* fast memory reads are only safe when the target is running
1914 * from a sufficiently high clock (32 kHz is usually too slow)
1916 if (arm7_9->fast_memory_access)
1917 arm7_9_execute_fast_sys_speed(target);
1919 arm7_9_execute_sys_speed(target);
1922 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1924 /* advance buffer, count number of accesses */
1925 buffer += thisrun_accesses * 1;
1926 num_accesses += thisrun_accesses;
1930 LOG_ERROR("BUG: we shouldn't get here");
1935 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1938 for (i=0; i<=last_reg; i++)
1939 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1941 arm7_9->read_xpsr(target, &cpsr, 0);
1942 if ((retval = jtag_execute_queue()) != ERROR_OK)
1944 LOG_ERROR("JTAG error while reading cpsr");
1945 return ERROR_TARGET_DATA_ABORT;
1948 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1950 LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1952 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1954 return ERROR_TARGET_DATA_ABORT;
1960 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1962 armv4_5_common_t *armv4_5 = target->arch_info;
1963 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1964 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1967 int num_accesses = 0;
1968 int thisrun_accesses;
1974 #ifdef _DEBUG_ARM7_9_
1975 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1978 if (target->state != TARGET_HALTED)
1980 LOG_WARNING("target not halted");
1981 return ERROR_TARGET_NOT_HALTED;
1984 /* sanitize arguments */
1985 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1986 return ERROR_INVALID_ARGUMENTS;
1988 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1989 return ERROR_TARGET_UNALIGNED_ACCESS;
1991 /* load the base register with the address of the first word */
1993 arm7_9->write_core_regs(target, 0x1, reg);
1995 /* Clear DBGACK, to make sure memory fetches work as expected */
1996 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1997 embeddedice_store_reg(dbg_ctrl);
2002 while (num_accesses < count)
2005 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2006 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2008 for (i = 1; i <= thisrun_accesses; i++)
2012 reg[i] = target_buffer_get_u32(target, buffer);
2016 arm7_9->write_core_regs(target, reg_list, reg);
2018 arm7_9->store_word_regs(target, reg_list);
2020 /* fast memory writes are only safe when the target is running
2021 * from a sufficiently high clock (32 kHz is usually too slow)
2023 if (arm7_9->fast_memory_access)
2024 arm7_9_execute_fast_sys_speed(target);
2026 arm7_9_execute_sys_speed(target);
2028 num_accesses += thisrun_accesses;
2032 while (num_accesses < count)
2035 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2036 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2038 for (i = 1; i <= thisrun_accesses; i++)
2042 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2046 arm7_9->write_core_regs(target, reg_list, reg);
2048 for (i = 1; i <= thisrun_accesses; i++)
2050 arm7_9->store_hword_reg(target, i);
2052 /* fast memory writes are only safe when the target is running
2053 * from a sufficiently high clock (32 kHz is usually too slow)
2055 if (arm7_9->fast_memory_access)
2056 arm7_9_execute_fast_sys_speed(target);
2058 arm7_9_execute_sys_speed(target);
2061 num_accesses += thisrun_accesses;
2065 while (num_accesses < count)
2068 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2069 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2071 for (i = 1; i <= thisrun_accesses; i++)
2075 reg[i] = *buffer++ & 0xff;
2078 arm7_9->write_core_regs(target, reg_list, reg);
2080 for (i = 1; i <= thisrun_accesses; i++)
2082 arm7_9->store_byte_reg(target, i);
2083 /* fast memory writes are only safe when the target is running
2084 * from a sufficiently high clock (32 kHz is usually too slow)
2086 if (arm7_9->fast_memory_access)
2087 arm7_9_execute_fast_sys_speed(target);
2089 arm7_9_execute_sys_speed(target);
2092 num_accesses += thisrun_accesses;
2096 LOG_ERROR("BUG: we shouldn't get here");
2102 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2103 embeddedice_store_reg(dbg_ctrl);
2105 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2108 for (i=0; i<=last_reg; i++)
2109 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2111 arm7_9->read_xpsr(target, &cpsr, 0);
2112 if ((retval = jtag_execute_queue()) != ERROR_OK)
2114 LOG_ERROR("JTAG error while reading cpsr");
2115 return ERROR_TARGET_DATA_ABORT;
2118 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2120 LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2122 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2124 return ERROR_TARGET_DATA_ABORT;
2130 static const u32 dcc_code[] =
2132 /* MRC TST BNE MRC STR B */
2133 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2136 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2138 armv4_5_common_t *armv4_5 = target->arch_info;
2139 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2140 enum armv4_5_state core_state = armv4_5->core_state;
2141 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2142 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2143 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2146 if (!arm7_9->dcc_downloads)
2147 return target->type->write_memory(target, address, 4, count, buffer);
2149 /* regrab previously allocated working_area, or allocate a new one */
2150 if (!arm7_9->dcc_working_area)
2152 u8 dcc_code_buf[6 * 4];
2154 /* make sure we have a working area */
2155 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2157 LOG_INFO("no working area available, falling back to memory writes");
2158 return target->type->write_memory(target, address, 4, count, buffer);
2161 /* copy target instructions to target endianness */
2162 for (i = 0; i < 6; i++)
2164 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2167 /* write DCC code to working area */
2168 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2171 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2172 armv4_5->core_cache->reg_list[0].valid = 1;
2173 armv4_5->core_cache->reg_list[0].dirty = 1;
2174 armv4_5->core_state = ARMV4_5_STATE_ARM;
2176 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2178 int little=target->endianness==TARGET_LITTLE_ENDIAN;
2181 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2182 core function repeated.
2184 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2187 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2188 u8 reg_addr = ice_reg->addr & 0x1f;
2189 int chain_pos = ice_reg->jtag_info->chain_pos;
2190 /* we want the compiler to duplicate the code, which it does not
2195 for (i = 1; i < count - 1; i++)
2197 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2202 for (i = 1; i < count - 1; i++)
2204 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2208 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2211 for (i = 0; i < count; i++)
2213 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2218 target_halt(target);
2220 for (i=0; i<100; i++)
2222 target_poll(target);
2223 if (target->state == TARGET_HALTED)
2225 usleep(1000); /* sleep 1ms */
2229 LOG_ERROR("bulk write timed out, target not halted");
2230 return ERROR_TARGET_TIMEOUT;
2233 /* restore target state */
2234 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2235 armv4_5->core_cache->reg_list[0].valid = 1;
2236 armv4_5->core_cache->reg_list[0].dirty = 1;
2237 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2238 armv4_5->core_cache->reg_list[1].valid = 1;
2239 armv4_5->core_cache->reg_list[1].dirty = 1;
2240 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2241 armv4_5->core_cache->reg_list[15].valid = 1;
2242 armv4_5->core_cache->reg_list[15].dirty = 1;
2243 armv4_5->core_state = core_state;
2248 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2250 working_area_t *crc_algorithm;
2251 armv4_5_algorithm_t armv4_5_info;
2252 reg_param_t reg_params[2];
2255 u32 arm7_9_crc_code[] = {
2256 0xE1A02000, /* mov r2, r0 */
2257 0xE3E00000, /* mov r0, #0xffffffff */
2258 0xE1A03001, /* mov r3, r1 */
2259 0xE3A04000, /* mov r4, #0 */
2260 0xEA00000B, /* b ncomp */
2262 0xE7D21004, /* ldrb r1, [r2, r4] */
2263 0xE59F7030, /* ldr r7, CRC32XOR */
2264 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2265 0xE3A05000, /* mov r5, #0 */
2267 0xE3500000, /* cmp r0, #0 */
2268 0xE1A06080, /* mov r6, r0, asl #1 */
2269 0xE2855001, /* add r5, r5, #1 */
2270 0xE1A00006, /* mov r0, r6 */
2271 0xB0260007, /* eorlt r0, r6, r7 */
2272 0xE3550008, /* cmp r5, #8 */
2273 0x1AFFFFF8, /* bne loop */
2274 0xE2844001, /* add r4, r4, #1 */
2276 0xE1540003, /* cmp r4, r3 */
2277 0x1AFFFFF1, /* bne nbyte */
2279 0xEAFFFFFE, /* b end */
2280 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2285 if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2287 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2290 /* convert flash writing code into a buffer in target endianness */
2291 for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2292 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2294 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2295 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2296 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2298 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
2299 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
2301 buf_set_u32(reg_params[0].value, 0, 32, address);
2302 buf_set_u32(reg_params[1].value, 0, 32, count);
2304 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2305 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2307 LOG_ERROR("error executing arm7_9 crc algorithm");
2308 destroy_reg_param(®_params[0]);
2309 destroy_reg_param(®_params[1]);
2310 target_free_working_area(target, crc_algorithm);
2314 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2316 destroy_reg_param(®_params[0]);
2317 destroy_reg_param(®_params[1]);
2319 target_free_working_area(target, crc_algorithm);
2324 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
2326 working_area_t *erase_check_algorithm;
2327 reg_param_t reg_params[3];
2328 armv4_5_algorithm_t armv4_5_info;
2332 u32 erase_check_code[] =
2335 0xe4d03001, /* ldrb r3, [r0], #1 */
2336 0xe0022003, /* and r2, r2, r3 */
2337 0xe2511001, /* subs r1, r1, #1 */
2338 0x1afffffb, /* bne loop */
2340 0xeafffffe /* b end */
2343 /* make sure we have a working area */
2344 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
2346 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2349 /* convert flash writing code into a buffer in target endianness */
2350 for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
2351 target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]);
2353 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2354 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2355 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2357 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
2358 buf_set_u32(reg_params[0].value, 0, 32, address);
2360 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
2361 buf_set_u32(reg_params[1].value, 0, 32, count);
2363 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
2364 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2366 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
2367 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
2369 destroy_reg_param(®_params[0]);
2370 destroy_reg_param(®_params[1]);
2371 destroy_reg_param(®_params[2]);
2372 target_free_working_area(target, erase_check_algorithm);
2376 *blank = buf_get_u32(reg_params[2].value, 0, 32);
2378 destroy_reg_param(®_params[0]);
2379 destroy_reg_param(®_params[1]);
2380 destroy_reg_param(®_params[2]);
2382 target_free_working_area(target, erase_check_algorithm);
2387 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2389 command_t *arm7_9_cmd;
2391 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2393 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2394 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2396 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2398 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2399 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2400 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2401 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2402 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2403 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2404 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2405 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2406 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2407 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2409 armv4_5_register_commands(cmd_ctx);
2411 etm_register_commands(cmd_ctx);
2416 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2421 target_t *target = get_current_target(cmd_ctx);
2422 armv4_5_common_t *armv4_5;
2423 arm7_9_common_t *arm7_9;
2425 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2427 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2431 if (target->state != TARGET_HALTED)
2433 command_print(cmd_ctx, "can't write registers while running");
2439 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2443 value = strtoul(args[0], NULL, 0);
2444 spsr = strtol(args[1], NULL, 0);
2446 /* if we're writing the CPSR, mask the T bit */
2450 arm7_9->write_xpsr(target, value, spsr);
2451 if ((retval = jtag_execute_queue()) != ERROR_OK)
2453 LOG_ERROR("JTAG error while writing to xpsr");
2460 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2466 target_t *target = get_current_target(cmd_ctx);
2467 armv4_5_common_t *armv4_5;
2468 arm7_9_common_t *arm7_9;
2470 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2472 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2476 if (target->state != TARGET_HALTED)
2478 command_print(cmd_ctx, "can't write registers while running");
2484 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2488 value = strtoul(args[0], NULL, 0);
2489 rotate = strtol(args[1], NULL, 0);
2490 spsr = strtol(args[2], NULL, 0);
2492 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2493 if ((retval = jtag_execute_queue()) != ERROR_OK)
2495 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2502 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2507 target_t *target = get_current_target(cmd_ctx);
2508 armv4_5_common_t *armv4_5;
2509 arm7_9_common_t *arm7_9;
2511 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2513 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2517 if (target->state != TARGET_HALTED)
2519 command_print(cmd_ctx, "can't write registers while running");
2525 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2529 num = strtol(args[0], NULL, 0);
2530 mode = strtoul(args[1], NULL, 0);
2531 value = strtoul(args[2], NULL, 0);
2533 arm7_9_write_core_reg(target, num, mode, value);
2538 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2540 target_t *target = get_current_target(cmd_ctx);
2541 armv4_5_common_t *armv4_5;
2542 arm7_9_common_t *arm7_9;
2544 if (target->state != TARGET_HALTED)
2546 LOG_ERROR("target not halted");
2547 return ERROR_TARGET_NOT_HALTED;
2550 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2552 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2558 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2562 if (strcmp("enable", args[0]) == 0)
2564 if (arm7_9->sw_bkpts_use_wp)
2566 arm7_9_enable_sw_bkpts(target);
2570 arm7_9->sw_bkpts_enabled = 1;
2573 else if (strcmp("disable", args[0]) == 0)
2575 if (arm7_9->sw_bkpts_use_wp)
2577 arm7_9_disable_sw_bkpts(target);
2581 arm7_9->sw_bkpts_enabled = 0;
2586 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2589 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2594 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2596 target_t *target = get_current_target(cmd_ctx);
2597 armv4_5_common_t *armv4_5;
2598 arm7_9_common_t *arm7_9;
2600 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2602 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2606 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2608 arm7_9->force_hw_bkpts = 1;
2609 if (arm7_9->sw_bkpts_use_wp)
2611 arm7_9_disable_sw_bkpts(target);
2614 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2616 arm7_9->force_hw_bkpts = 0;
2620 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2623 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2628 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2630 target_t *target = get_current_target(cmd_ctx);
2631 armv4_5_common_t *armv4_5;
2632 arm7_9_common_t *arm7_9;
2634 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2636 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2642 if (strcmp("enable", args[0]) == 0)
2644 arm7_9->use_dbgrq = 1;
2646 else if (strcmp("disable", args[0]) == 0)
2648 arm7_9->use_dbgrq = 0;
2652 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2656 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2661 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2663 target_t *target = get_current_target(cmd_ctx);
2664 armv4_5_common_t *armv4_5;
2665 arm7_9_common_t *arm7_9;
2667 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2669 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2675 if (strcmp("enable", args[0]) == 0)
2677 arm7_9->fast_memory_access = 1;
2679 else if (strcmp("disable", args[0]) == 0)
2681 arm7_9->fast_memory_access = 0;
2685 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2689 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2694 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2696 target_t *target = get_current_target(cmd_ctx);
2697 armv4_5_common_t *armv4_5;
2698 arm7_9_common_t *arm7_9;
2700 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2702 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2708 if (strcmp("enable", args[0]) == 0)
2710 arm7_9->dcc_downloads = 1;
2712 else if (strcmp("disable", args[0]) == 0)
2714 arm7_9->dcc_downloads = 0;
2718 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2722 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2727 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2729 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2731 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2733 arm_jtag_setup_connection(&arm7_9->jtag_info);
2734 arm7_9->wp_available = 2;
2735 arm7_9->wp0_used = 0;
2736 arm7_9->wp1_used = 0;
2737 arm7_9->force_hw_bkpts = 0;
2738 arm7_9->use_dbgrq = 0;
2740 arm7_9->etm_ctx = NULL;
2741 arm7_9->has_single_step = 0;
2742 arm7_9->has_monitor_mode = 0;
2743 arm7_9->has_vector_catch = 0;
2745 arm7_9->debug_entry_from_reset = 0;
2747 arm7_9->dcc_working_area = NULL;
2749 arm7_9->fast_memory_access = fast_and_dangerous;
2750 arm7_9->dcc_downloads = fast_and_dangerous;
2752 arm7_9->need_bypass_before_restart = 0;
2754 armv4_5->arch_info = arm7_9;
2755 armv4_5->read_core_reg = arm7_9_read_core_reg;
2756 armv4_5->write_core_reg = arm7_9_write_core_reg;
2757 armv4_5->full_context = arm7_9_full_context;
2759 armv4_5_init_arch_info(target, armv4_5);
2761 target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);