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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2008 by Hongtao Zheng                                   *
  12  *   hontor@126.com                                                        *
  13  *                                                                         *
  14  *   Copyright (C) 2009 by David Brownell                                  *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  30  ***************************************************************************/
  31 #ifdef HAVE_CONFIG_H
  32 #include "config.h"
  33 #endif
  34
  35 #include "breakpoints.h"
  36 #include "embeddedice.h"
  37 #include "target_request.h"
  38 #include "etm.h"
  39 #include <helper/time_support.h>
  40 #include "arm_simulator.h"
  41 #include "arm_semihosting.h"
  42 #include "algorithm.h"
  43 #include "register.h"
  44 #include "armv4_5.h"
  45
  46
  47 /**
  48  * @file
  49  * Hold common code supporting the ARM7 and ARM9 core generations.
  50  *
  51  * While the ARM core implementations evolved substantially during these
  52  * two generations, they look quite similar from the JTAG perspective.
  53  * Both have similar debug facilities, based on the same two scan chains
  54  * providing access to the core and to an EmbeddedICE module.  Both can
  55  * support similar ETM and ETB modules, for tracing.  And both expose
  56  * what could be viewed as "ARM Classic", with multiple processor modes,
  57  * shadowed registers, and support for the Thumb instruction set.
  58  *
  59  * Processor differences include things like presence or absence of MMU
  60  * and cache, pipeline sizes, use of a modified Harvard Architecure
  61  * (with separate instruction and data busses from the CPU), support
  62  * for cpu clock gating during idle, and more.
  63  */
  64
  65 static int arm7_9_debug_entry(struct target *target);
  66
  67 /**
  68  * Clear watchpoints for an ARM7/9 target.
  69  *
  70  * @param arm7_9 Pointer to the common struct for an ARM7/9 target
  71  * @return JTAG error status after executing queue
  72  */
  73 static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
  74 {
  75         LOG_DEBUG("-");
  76         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
  77         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  78         arm7_9->sw_breakpoint_count = 0;
  79         arm7_9->sw_breakpoints_added = 0;
  80         arm7_9->wp0_used = 0;
  81         arm7_9->wp1_used = arm7_9->wp1_used_default;
  82         arm7_9->wp_available = arm7_9->wp_available_max;
  83
  84         return jtag_execute_queue();
  85 }
  86
  87 /**
  88  * Assign a watchpoint to one of the two available hardware comparators in an
  89  * ARM7 or ARM9 target.
  90  *
  91  * @param arm7_9 Pointer to the common struct for an ARM7/9 target
  92  * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
  93  */
  94 static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
  95 {
  96         if (!arm7_9->wp0_used)
  97         {
  98                 arm7_9->wp0_used = 1;
  99                 breakpoint->set = 1;
 100                 arm7_9->wp_available--;
 101         }
 102         else if (!arm7_9->wp1_used)
 103         {
 104                 arm7_9->wp1_used = 1;
 105                 breakpoint->set = 2;
 106                 arm7_9->wp_available--;
 107         }
 108         else
 109         {
 110                 LOG_ERROR("BUG: no hardware comparator available");
 111         }
 112         LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
 113                           breakpoint->unique_id,
 114                           breakpoint->address,
 115                           breakpoint->set );
 116 }
 117
 118 /**
 119  * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
 120  *
 121  * @param arm7_9 Pointer to common struct for ARM7/9 targets
 122  * @return Error codes if there is a problem finding a watchpoint or the result
 123  *         of executing the JTAG queue
 124  */
 125 static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
 126 {
 127         if (arm7_9->sw_breakpoints_added)
 128         {
 129                 return ERROR_OK;
 130         }
 131         if (arm7_9->wp_available < 1)
 132         {
 133                 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
 134                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 135         }
 136         arm7_9->wp_available--;
 137
 138         /* pick a breakpoint unit */
 139         if (!arm7_9->wp0_used)
 140         {
 141                 arm7_9->sw_breakpoints_added = 1;
 142                 arm7_9->wp0_used = 3;
 143         } else if (!arm7_9->wp1_used)
 144         {
 145                 arm7_9->sw_breakpoints_added = 2;
 146                 arm7_9->wp1_used = 3;
 147         }
 148         else
 149         {
 150                 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
 151                 return ERROR_FAIL;
 152         }
 153
 154         if (arm7_9->sw_breakpoints_added == 1)
 155         {
 156                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
 157                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
 158                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
 159                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 160                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 161         }
 162         else if (arm7_9->sw_breakpoints_added == 2)
 163         {
 164                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
 165                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
 166                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
 167                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 168                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 169         }
 170         else
 171         {
 172                 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
 173                 return ERROR_FAIL;
 174         }
 175         LOG_DEBUG("SW BP using hw wp: %d",
 176                           arm7_9->sw_breakpoints_added );
 177
 178         return jtag_execute_queue();
 179 }
 180
 181 /**
 182  * Setup the common pieces for an ARM7/9 target after reset or on startup.
 183  *
 184  * @param target Pointer to an ARM7/9 target to setup
 185  * @return Result of clearing the watchpoints on the target
 186  */
 187 static int arm7_9_setup(struct target *target)
 188 {
 189         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 190
 191         return arm7_9_clear_watchpoints(arm7_9);
 192 }
 193
 194 /**
 195  * Set either a hardware or software breakpoint on an ARM7/9 target.  The
 196  * breakpoint is set up even if it is already set.  Some actions, e.g. reset,
 197  * might have erased the values in Embedded ICE.
 198  *
 199  * @param target Pointer to the target device to set the breakpoints on
 200  * @param breakpoint Pointer to the breakpoint to be set
 201  * @return For hardware breakpoints, this is the result of executing the JTAG
 202  *         queue.  For software breakpoints, this will be the status of the
 203  *         required memory reads and writes
 204  */
 205 static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 206 {
 207         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 208         int retval = ERROR_OK;
 209
 210         LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
 211                           breakpoint->unique_id,
 212                           breakpoint->address,
 213                           breakpoint->type);
 214
 215         if (target->state != TARGET_HALTED)
 216         {
 217                 LOG_WARNING("target not halted");
 218                 return ERROR_TARGET_NOT_HALTED;
 219         }
 220
 221         if (breakpoint->type == BKPT_HARD)
 222         {
 223                 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
 224                 uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 225
 226                 /* reassign a hw breakpoint */
 227                 if (breakpoint->set == 0)
 228                 {
 229                         arm7_9_assign_wp(arm7_9, breakpoint);
 230                 }
 231
 232                 if (breakpoint->set == 1)
 233                 {
 234                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
 235                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 236                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
 237                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 238                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 239                 }
 240                 else if (breakpoint->set == 2)
 241                 {
 242                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
 243                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 244                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
 245                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 246                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 247                 }
 248                 else
 249                 {
 250                         LOG_ERROR("BUG: no hardware comparator available");
 251                         return ERROR_OK;
 252                 }
 253
 254                 retval = jtag_execute_queue();
 255         }
 256         else if (breakpoint->type == BKPT_SOFT)
 257         {
 258                 /* did we already set this breakpoint? */
 259                 if (breakpoint->set)
 260                         return ERROR_OK;
 261
 262                 if (breakpoint->length == 4)
 263                 {
 264                         uint32_t verify = 0xffffffff;
 265                         /* keep the original instruction in target endianness */
 266                         if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 267                         {
 268                                 return retval;
 269                         }
 270                         /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 271                         if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
 272                         {
 273                                 return retval;
 274                         }
 275
 276                         if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
 277                         {
 278                                 return retval;
 279                         }
 280                         if (verify != arm7_9->arm_bkpt)
 281                         {
 282                                 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 283                                 return ERROR_OK;
 284                         }
 285                 }
 286                 else
 287                 {
 288                         uint16_t verify = 0xffff;
 289                         /* keep the original instruction in target endianness */
 290                         if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 291                         {
 292                                 return retval;
 293                         }
 294                         /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
 295                         if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
 296                         {
 297                                 return retval;
 298                         }
 299
 300                         if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
 301                         {
 302                                 return retval;
 303                         }
 304                         if (verify != arm7_9->thumb_bkpt)
 305                         {
 306                                 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 307                                 return ERROR_OK;
 308                         }
 309                 }
 310
 311                 if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
 312                         return retval;
 313
 314                 arm7_9->sw_breakpoint_count++;
 315
 316                 breakpoint->set = 1;
 317         }
 318
 319         return retval;
 320 }
 321
 322 /**
 323  * Unsets an existing breakpoint on an ARM7/9 target.  If it is a hardware
 324  * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
 325  * will be updated.  Otherwise, the software breakpoint will be restored to its
 326  * original instruction if it hasn't already been modified.
 327  *
 328  * @param target Pointer to ARM7/9 target to unset the breakpoint from
 329  * @param breakpoint Pointer to breakpoint to be unset
 330  * @return For hardware breakpoints, this is the result of executing the JTAG
 331  *         queue.  For software breakpoints, this will be the status of the
 332  *         required memory reads and writes
 333  */
 334 static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 335 {
 336         int retval = ERROR_OK;
 337         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 338
 339         LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
 340                           breakpoint->unique_id,
 341                           breakpoint->address );
 342
 343         if (!breakpoint->set)
 344         {
 345                 LOG_WARNING("breakpoint not set");
 346                 return ERROR_OK;
 347         }
 348
 349         if (breakpoint->type == BKPT_HARD)
 350         {
 351                 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
 352                                   breakpoint->unique_id,
 353                                   breakpoint->set );
 354                 if (breakpoint->set == 1)
 355                 {
 356                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 357                         arm7_9->wp0_used = 0;
 358                         arm7_9->wp_available++;
 359                 }
 360                 else if (breakpoint->set == 2)
 361                 {
 362                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 363                         arm7_9->wp1_used = 0;
 364                         arm7_9->wp_available++;
 365                 }
 366                 retval = jtag_execute_queue();
 367                 breakpoint->set = 0;
 368         }
 369         else
 370         {
 371                 /* restore original instruction (kept in target endianness) */
 372                 if (breakpoint->length == 4)
 373                 {
 374                         uint32_t current_instr;
 375                         /* check that user program as not modified breakpoint instruction */
 376                         if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
 377                         {
 378                                 return retval;
 379                         }
 380                         current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
 381                         if (current_instr == arm7_9->arm_bkpt)
 382                                 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 383                                 {
 384                                         return retval;
 385                                 }
 386                 }
 387                 else
 388                 {
 389                         uint16_t current_instr;
 390                         /* check that user program as not modified breakpoint instruction */
 391                         if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
 392                         {
 393                                 return retval;
 394                         }
 395                         current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
 396                         if (current_instr == arm7_9->thumb_bkpt)
 397                                 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 398                                 {
 399                                         return retval;
 400                                 }
 401                 }
 402
 403                 if (--arm7_9->sw_breakpoint_count==0)
 404                 {
 405                         /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
 406                         if (arm7_9->sw_breakpoints_added == 1)
 407                         {
 408                                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
 409                         }
 410                         else if (arm7_9->sw_breakpoints_added == 2)
 411                         {
 412                                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
 413                         }
 414                 }
 415
 416                 breakpoint->set = 0;
 417         }
 418
 419         return retval;
 420 }
 421
 422 /**
 423  * Add a breakpoint to an ARM7/9 target.  This makes sure that there are no
 424  * dangling breakpoints and that the desired breakpoint can be added.
 425  *
 426  * @param target Pointer to the target ARM7/9 device to add a breakpoint to
 427  * @param breakpoint Pointer to the breakpoint to be added
 428  * @return An error status if there is a problem adding the breakpoint or the
 429  *         result of setting the breakpoint
 430  */
 431 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 432 {
 433         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 434
 435         if (arm7_9->breakpoint_count == 0)
 436         {
 437                 /* make sure we don't have any dangling breakpoints. This is vital upon
 438                  * GDB connect/disconnect
 439                  */
 440                 arm7_9_clear_watchpoints(arm7_9);
 441         }
 442
 443         if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
 444         {
 445                 LOG_INFO("no watchpoint unit available for hardware breakpoint");
 446                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 447         }
 448
 449         if ((breakpoint->length != 2) && (breakpoint->length != 4))
 450         {
 451                 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 452                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 453         }
 454
 455         if (breakpoint->type == BKPT_HARD)
 456         {
 457                 arm7_9_assign_wp(arm7_9, breakpoint);
 458         }
 459
 460         arm7_9->breakpoint_count++;
 461
 462         return arm7_9_set_breakpoint(target, breakpoint);
 463 }
 464
 465 /**
 466  * Removes a breakpoint from an ARM7/9 target.  This will make sure there are no
 467  * dangling breakpoints and updates available watchpoints if it is a hardware
 468  * breakpoint.
 469  *
 470  * @param target Pointer to the target to have a breakpoint removed
 471  * @param breakpoint Pointer to the breakpoint to be removed
 472  * @return Error status if there was a problem unsetting the breakpoint or the
 473  *         watchpoints could not be cleared
 474  */
 475 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 476 {
 477         int retval = ERROR_OK;
 478         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 479
 480         if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
 481         {
 482                 return retval;
 483         }
 484
 485         if (breakpoint->type == BKPT_HARD)
 486                 arm7_9->wp_available++;
 487
 488         arm7_9->breakpoint_count--;
 489         if (arm7_9->breakpoint_count == 0)
 490         {
 491                 /* make sure we don't have any dangling breakpoints */
 492                 if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
 493                 {
 494                         return retval;
 495                 }
 496         }
 497
 498         return ERROR_OK;
 499 }
 500
 501 /**
 502  * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units.  It is
 503  * considered a bug to call this function when there are no available watchpoint
 504  * units.
 505  *
 506  * @param target Pointer to an ARM7/9 target to set a watchpoint on
 507  * @param watchpoint Pointer to the watchpoint to be set
 508  * @return Error status if watchpoint set fails or the result of executing the
 509  *         JTAG queue
 510  */
 511 static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
 512 {
 513         int retval = ERROR_OK;
 514         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 515         int rw_mask = 1;
 516         uint32_t mask;
 517
 518         mask = watchpoint->length - 1;
 519
 520         if (target->state != TARGET_HALTED)
 521         {
 522                 LOG_WARNING("target not halted");
 523                 return ERROR_TARGET_NOT_HALTED;
 524         }
 525
 526         if (watchpoint->rw == WPT_ACCESS)
 527                 rw_mask = 0;
 528         else
 529                 rw_mask = 1;
 530
 531         if (!arm7_9->wp0_used)
 532         {
 533                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
 534                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 535                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
 536                 if (watchpoint->mask != 0xffffffffu)
 537                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
 538                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 539                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 540
 541                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 542                 {
 543                         return retval;
 544                 }
 545                 watchpoint->set = 1;
 546                 arm7_9->wp0_used = 2;
 547         }
 548         else if (!arm7_9->wp1_used)
 549         {
 550                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
 551                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 552                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
 553                 if (watchpoint->mask != 0xffffffffu)
 554                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
 555                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 556                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 557
 558                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 559                 {
 560                         return retval;
 561                 }
 562                 watchpoint->set = 2;
 563                 arm7_9->wp1_used = 2;
 564         }
 565         else
 566         {
 567                 LOG_ERROR("BUG: no hardware comparator available");
 568                 return ERROR_OK;
 569         }
 570
 571         return ERROR_OK;
 572 }
 573
 574 /**
 575  * Unset an existing watchpoint and clear the used watchpoint unit.
 576  *
 577  * @param target Pointer to the target to have the watchpoint removed
 578  * @param watchpoint Pointer to the watchpoint to be removed
 579  * @return Error status while trying to unset the watchpoint or the result of
 580  *         executing the JTAG queue
 581  */
 582 static int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
 583 {
 584         int retval = ERROR_OK;
 585         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 586
 587         if (target->state != TARGET_HALTED)
 588         {
 589                 LOG_WARNING("target not halted");
 590                 return ERROR_TARGET_NOT_HALTED;
 591         }
 592
 593         if (!watchpoint->set)
 594         {
 595                 LOG_WARNING("breakpoint not set");
 596                 return ERROR_OK;
 597         }
 598
 599         if (watchpoint->set == 1)
 600         {
 601                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 602                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 603                 {
 604                         return retval;
 605                 }
 606                 arm7_9->wp0_used = 0;
 607         }
 608         else if (watchpoint->set == 2)
 609         {
 610                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 611                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 612                 {
 613                         return retval;
 614                 }
 615                 arm7_9->wp1_used = 0;
 616         }
 617         watchpoint->set = 0;
 618
 619         return ERROR_OK;
 620 }
 621
 622 /**
 623  * Add a watchpoint to an ARM7/9 target.  If there are no watchpoint units
 624  * available, an error response is returned.
 625  *
 626  * @param target Pointer to the ARM7/9 target to add a watchpoint to
 627  * @param watchpoint Pointer to the watchpoint to be added
 628  * @return Error status while trying to add the watchpoint
 629  */
 630 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 631 {
 632         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 633
 634         if (arm7_9->wp_available < 1)
 635         {
 636                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 637         }
 638
 639         if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
 640         {
 641                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 642         }
 643
 644         arm7_9->wp_available--;
 645
 646         return ERROR_OK;
 647 }
 648
 649 /**
 650  * Remove a watchpoint from an ARM7/9 target.  The watchpoint will be unset and
 651  * the used watchpoint unit will be reopened.
 652  *
 653  * @param target Pointer to the target to remove a watchpoint from
 654  * @param watchpoint Pointer to the watchpoint to be removed
 655  * @return Result of trying to unset the watchpoint
 656  */
 657 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
 658 {
 659         int retval = ERROR_OK;
 660         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 661
 662         if (watchpoint->set)
 663         {
 664                 if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
 665                 {
 666                         return retval;
 667                 }
 668         }
 669
 670         arm7_9->wp_available++;
 671
 672         return ERROR_OK;
 673 }
 674
 675 /**
 676  * Restarts the target by sending a RESTART instruction and moving the JTAG
 677  * state to IDLE.  This includes a timeout waiting for DBGACK and SYSCOMP to be
 678  * asserted by the processor.
 679  *
 680  * @param target Pointer to target to issue commands to
 681  * @return Error status if there is a timeout or a problem while executing the
 682  *         JTAG queue
 683  */
 684 int arm7_9_execute_sys_speed(struct target *target)
 685 {
 686         int retval;
 687         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 688         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 689         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 690
 691         /* set RESTART instruction */
 692         if (arm7_9->need_bypass_before_restart) {
 693                 arm7_9->need_bypass_before_restart = 0;
 694                 retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
 695                 if (retval != ERROR_OK)
 696                         return retval;
 697         }
 698         retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
 699         if (retval != ERROR_OK)
 700                 return retval;
 701
 702         long long then = timeval_ms();
 703         int timeout;
 704         while (!(timeout = ((timeval_ms()-then) > 1000)))
 705         {
 706                 /* read debug status register */
 707                 embeddedice_read_reg(dbg_stat);
 708                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 709                         return retval;
 710                 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 711                                    && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 712                         break;
 713                 if (debug_level >= 3)
 714                 {
 715                         alive_sleep(100);
 716                 } else
 717                 {
 718                         keep_alive();
 719                 }
 720         }
 721         if (timeout)
 722         {
 723                 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 724                 return ERROR_TARGET_TIMEOUT;
 725         }
 726
 727         return ERROR_OK;
 728 }
 729
 730 /**
 731  * Restarts the target by sending a RESTART instruction and moving the JTAG
 732  * state to IDLE.  This validates that DBGACK and SYSCOMP are set without
 733  * waiting until they are.
 734  *
 735  * @param target Pointer to the target to issue commands to
 736  * @return Always ERROR_OK
 737  */
 738 static int arm7_9_execute_fast_sys_speed(struct target *target)
 739 {
 740         static int set = 0;
 741         static uint8_t check_value[4], check_mask[4];
 742
 743         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 744         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 745         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 746         int retval;
 747
 748         /* set RESTART instruction */
 749         if (arm7_9->need_bypass_before_restart) {
 750                 arm7_9->need_bypass_before_restart = 0;
 751                 retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
 752                 if (retval != ERROR_OK)
 753                         return retval;
 754         }
 755         retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
 756         if (retval != ERROR_OK)
 757                 return retval;
 758
 759         if (!set)
 760         {
 761                 /* check for DBGACK and SYSCOMP set (others don't care) */
 762
 763                 /* NB! These are constants that must be available until after next jtag_execute() and
 764                  * we evaluate the values upon first execution in lieu of setting up these constants
 765                  * during early setup.
 766                  * */
 767                 buf_set_u32(check_value, 0, 32, 0x9);
 768                 buf_set_u32(check_mask, 0, 32, 0x9);
 769                 set = 1;
 770         }
 771
 772         /* read debug status register */
 773         embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask);
 774
 775         return ERROR_OK;
 776 }
 777
 778 /**
 779  * Get some data from the ARM7/9 target.
 780  *
 781  * @param target Pointer to the ARM7/9 target to read data from
 782  * @param size The number of 32bit words to be read
 783  * @param buffer Pointer to the buffer that will hold the data
 784  * @return The result of receiving data from the Embedded ICE unit
 785  */
 786 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
 787 {
 788         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 789         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 790         uint32_t *data;
 791         int retval = ERROR_OK;
 792         uint32_t i;
 793
 794         data = malloc(size * (sizeof(uint32_t)));
 795
 796         retval = embeddedice_receive(jtag_info, data, size);
 797
 798         /* return the 32-bit ints in the 8-bit array */
 799         for (i = 0; i < size; i++)
 800         {
 801                 h_u32_to_le(buffer + (i * 4), data[i]);
 802         }
 803
 804         free(data);
 805
 806         return retval;
 807 }
 808
 809 /**
 810  * Handles requests to an ARM7/9 target.  If debug messaging is enabled, the
 811  * target is running and the DCC control register has the W bit high, this will
 812  * execute the request on the target.
 813  *
 814  * @param priv Void pointer expected to be a struct target pointer
 815  * @return ERROR_OK unless there are issues with the JTAG queue or when reading
 816  *                  from the Embedded ICE unit
 817  */
 818 static int arm7_9_handle_target_request(void *priv)
 819 {
 820         int retval = ERROR_OK;
 821         struct target *target = priv;
 822         if (!target_was_examined(target))
 823                 return ERROR_OK;
 824         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 825         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 826         struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
 827
 828         if (!target->dbg_msg_enabled)
 829                 return ERROR_OK;
 830
 831         if (target->state == TARGET_RUNNING)
 832         {
 833                 /* read DCC control register */
 834                 embeddedice_read_reg(dcc_control);
 835                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 836                 {
 837                         return retval;
 838                 }
 839
 840                 /* check W bit */
 841                 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
 842                 {
 843                         uint32_t request;
 844
 845                         if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
 846                         {
 847                                 return retval;
 848                         }
 849                         if ((retval = target_request(target, request)) != ERROR_OK)
 850                         {
 851                                 return retval;
 852                         }
 853                 }
 854         }
 855
 856         return ERROR_OK;
 857 }
 858
 859 /**
 860  * Polls an ARM7/9 target for its current status.  If DBGACK is set, the target
 861  * is manipulated to the right halted state based on its current state.  This is
 862  * what happens:
 863  *
 864  * <table>
 865  *              <tr><th > State</th><th > Action</th></tr>
 866  *              <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode.  If TARGET_RESET, pc may be checked</td></tr>
 867  *              <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
 868  *              <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
 869  *              <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
 870  * </table>
 871  *
 872  * If the target does not end up in the halted state, a warning is produced.  If
 873  * DBGACK is cleared, then the target is expected to either be running or
 874  * running in debug.
 875  *
 876  * @param target Pointer to the ARM7/9 target to poll
 877  * @return ERROR_OK or an error status if a command fails
 878  */
 879 int arm7_9_poll(struct target *target)
 880 {
 881         int retval;
 882         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 883         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 884
 885         /* read debug status register */
 886         embeddedice_read_reg(dbg_stat);
 887         if ((retval = jtag_execute_queue()) != ERROR_OK)
 888         {
 889                 return retval;
 890         }
 891
 892         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 893         {
 894 /*              LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
 895                 if (target->state == TARGET_UNKNOWN)
 896                 {
 897                         /* Starting OpenOCD with target in debug-halt */
 898                         target->state = TARGET_RUNNING;
 899                         LOG_DEBUG("DBGACK already set during server startup.");
 900                 }
 901                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 902                 {
 903                         target->state = TARGET_HALTED;
 904
 905                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 906                                 return retval;
 907
 908                         if (arm_semihosting(target, &retval) != 0)
 909                                 return retval;
 910
 911                         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 912                         {
 913                                 return retval;
 914                         }
 915                 }
 916                 if (target->state == TARGET_DEBUG_RUNNING)
 917                 {
 918                         target->state = TARGET_HALTED;
 919                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 920                                 return retval;
 921
 922                         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
 923                         {
 924                                 return retval;
 925                         }
 926                 }
 927                 if (target->state != TARGET_HALTED)
 928                 {
 929                         LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state);
 930                 }
 931         }
 932         else
 933         {
 934                 if (target->state != TARGET_DEBUG_RUNNING)
 935                         target->state = TARGET_RUNNING;
 936         }
 937
 938         return ERROR_OK;
 939 }
 940
 941 /**
 942  * Asserts the reset (SRST) on an ARM7/9 target.  Some -S targets (ARM966E-S in
 943  * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
 944  * affected) completely stop the JTAG clock while the core is held in reset
 945  * (SRST).  It isn't possible to program the halt condition once reset is
 946  * asserted, hence a hook that allows the target to set up its reset-halt
 947  * condition is setup prior to asserting reset.
 948  *
 949  * @param target Pointer to an ARM7/9 target to assert reset on
 950  * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
 951  */
 952 int arm7_9_assert_reset(struct target *target)
 953 {
 954         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 955         enum reset_types jtag_reset_config = jtag_get_reset_config();
 956         bool use_event = false;
 957
 958         LOG_DEBUG("target->state: %s",
 959                   target_state_name(target));
 960
 961         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
 962                 use_event = true;
 963         else if (!(jtag_reset_config & RESET_HAS_SRST)) {
 964                 LOG_ERROR("%s: how to reset?", target_name(target));
 965                 return ERROR_FAIL;
 966         }
 967
 968         /* At this point trst has been asserted/deasserted once. We would
 969          * like to program EmbeddedICE while SRST is asserted, instead of
 970          * depending on SRST to leave that module alone.  However, many CPUs
 971          * gate the JTAG clock while SRST is asserted; or JTAG may need
 972          * clock stability guarantees (adaptive clocking might help).
 973          *
 974          * So we assume JTAG access during SRST is off the menu unless it's
 975          * been specifically enabled.
 976          */
 977         bool srst_asserted = false;
 978
 979         if (!use_event
 980                         && !(jtag_reset_config & RESET_SRST_PULLS_TRST)
 981                         && (jtag_reset_config & RESET_SRST_NO_GATING))
 982         {
 983                 jtag_add_reset(0, 1);
 984                 srst_asserted = true;
 985         }
 986
 987         if (target->reset_halt)
 988         {
 989                 /*
 990                  * For targets that don't support communication while SRST is
 991                  * asserted, we need to set up the reset vector catch first.
 992                  *
 993                  * When we use TRST+SRST and that's equivalent to a power-up
 994                  * reset, these settings may well be reset anyway; so setting
 995                  * them here won't matter.
 996                  */
 997                 if (arm7_9->has_vector_catch)
 998                 {
 999                         /* program vector catch register to catch reset */
1000                         embeddedice_write_reg(&arm7_9->eice_cache
1001                                         ->reg_list[EICE_VEC_CATCH], 0x1);
1002
1003                         /* extra runtest added as issues were found with
1004                          * certain ARM9 cores (maybe more) - AT91SAM9260
1005                          * and STR9
1006                          */
1007                         jtag_add_runtest(1, TAP_IDLE);
1008                 }
1009                 else
1010                 {
1011                         /* program watchpoint unit to match on reset vector
1012                          * address
1013                          */
1014                         embeddedice_write_reg(&arm7_9->eice_cache
1015                                         ->reg_list[EICE_W0_ADDR_VALUE], 0x0);
1016                         embeddedice_write_reg(&arm7_9->eice_cache
1017                                         ->reg_list[EICE_W0_ADDR_MASK], 0x3);
1018                         embeddedice_write_reg(&arm7_9->eice_cache
1019                                         ->reg_list[EICE_W0_DATA_MASK],
1020                                                 0xffffffff);
1021                         embeddedice_write_reg(&arm7_9->eice_cache
1022                                         ->reg_list[EICE_W0_CONTROL_VALUE],
1023                                                 EICE_W_CTRL_ENABLE);
1024                         embeddedice_write_reg(&arm7_9->eice_cache
1025                                         ->reg_list[EICE_W0_CONTROL_MASK],
1026                                                 ~EICE_W_CTRL_nOPC & 0xff);
1027                 }
1028         }
1029
1030         if (use_event) {
1031                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1032         } else {
1033                 /* If we use SRST ... we'd like to issue just SRST, but the
1034                  * board or chip may be set up so we have to assert TRST as
1035                  * well.  On some chips that combination is equivalent to a
1036                  * power-up reset, and generally clobbers EICE state.
1037                  */
1038                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1039                         jtag_add_reset(1, 1);
1040                 else if (!srst_asserted)
1041                         jtag_add_reset(0, 1);
1042                 jtag_add_sleep(50000);
1043         }
1044
1045         target->state = TARGET_RESET;
1046         register_cache_invalidate(arm7_9->arm.core_cache);
1047
1048         /* REVISIT why isn't standard debug entry logic sufficient?? */
1049         if (target->reset_halt
1050                         && (!(jtag_reset_config & RESET_SRST_PULLS_TRST)
1051                                 || use_event))
1052         {
1053                 /* debug entry was prepared above */
1054                 target->debug_reason = DBG_REASON_DBGRQ;
1055         }
1056
1057         return ERROR_OK;
1058 }
1059
1060 /**
1061  * Deassert the reset (SRST) signal on an ARM7/9 target.  If SRST pulls TRST
1062  * and the target is being reset into a halt, a warning will be triggered
1063  * because it is not possible to reset into a halted mode in this case.  The
1064  * target is halted using the target's functions.
1065  *
1066  * @param target Pointer to the target to have the reset deasserted
1067  * @return ERROR_OK or an error from polling or halting the target
1068  */
1069 int arm7_9_deassert_reset(struct target *target)
1070 {
1071         int retval = ERROR_OK;
1072         LOG_DEBUG("target->state: %s",
1073                 target_state_name(target));
1074
1075         /* deassert reset lines */
1076         jtag_add_reset(0, 0);
1077
1078         /* In case polling is disabled, we need to examine the
1079          * target and poll here for this target to work correctly.
1080          *
1081          * Otherwise, e.g. halt will fail afterwards with bogus
1082          * error messages as halt will believe that reset is
1083          * still in effect.
1084          */
1085         if ((retval = target_examine_one(target)) != ERROR_OK)
1086                 return retval;
1087
1088         if ((retval = target_poll(target)) != ERROR_OK)
1089         {
1090                 return retval;
1091         }
1092
1093         enum reset_types jtag_reset_config = jtag_get_reset_config();
1094         if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
1095         {
1096                 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1097                 if ((retval = target_halt(target)) != ERROR_OK)
1098                 {
1099                         return retval;
1100                 }
1101         }
1102         return retval;
1103 }
1104
1105 /**
1106  * Clears the halt condition for an ARM7/9 target.  If it isn't coming out of
1107  * reset and if DBGRQ is used, it is progammed to be deasserted.  If the reset
1108  * vector catch was used, it is restored.  Otherwise, the control value is
1109  * restored and the watchpoint unit is restored if it was in use.
1110  *
1111  * @param target Pointer to the ARM7/9 target to have halt cleared
1112  * @return Always ERROR_OK
1113  */
1114 static int arm7_9_clear_halt(struct target *target)
1115 {
1116         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1117         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1118
1119         /* we used DBGRQ only if we didn't come out of reset */
1120         if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
1121         {
1122                 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1123                  */
1124                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1125                 embeddedice_store_reg(dbg_ctrl);
1126         }
1127         else
1128         {
1129                 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
1130                 {
1131                         /* if we came out of reset, and vector catch is supported, we used
1132                          * vector catch to enter debug state
1133                          * restore the register in that case
1134                          */
1135                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
1136                 }
1137                 else
1138                 {
1139                         /* restore registers if watchpoint unit 0 was in use
1140                          */
1141                         if (arm7_9->wp0_used)
1142                         {
1143                                 if (arm7_9->debug_entry_from_reset)
1144                                 {
1145                                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
1146                                 }
1147                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1148                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1149                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1150                         }
1151                         /* control value always has to be restored, as it was either disabled,
1152                          * or enabled with possibly different bits
1153                          */
1154                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1155                 }
1156         }
1157
1158         return ERROR_OK;
1159 }
1160
1161 /**
1162  * Issue a software reset and halt to an ARM7/9 target.  The target is halted
1163  * and then there is a wait until the processor shows the halt.  This wait can
1164  * timeout and results in an error being returned.  The software reset involves
1165  * clearing the halt, updating the debug control register, changing to ARM mode,
1166  * reset of the program counter, and reset of all of the registers.
1167  *
1168  * @param target Pointer to the ARM7/9 target to be reset and halted by software
1169  * @return Error status if any of the commands fail, otherwise ERROR_OK
1170  */
1171 int arm7_9_soft_reset_halt(struct target *target)
1172 {
1173         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1174         struct arm *arm = &arm7_9->arm;
1175         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1176         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1177         int i;
1178         int retval;
1179
1180         /* FIX!!! replace some of this code with tcl commands
1181          *
1182          * halt # the halt command is synchronous
1183          * armv4_5 core_state arm
1184          *
1185          */
1186
1187         if ((retval = target_halt(target)) != ERROR_OK)
1188                 return retval;
1189
1190         long long then = timeval_ms();
1191         int timeout;
1192         while (!(timeout = ((timeval_ms()-then) > 1000)))
1193         {
1194                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
1195                         break;
1196                 embeddedice_read_reg(dbg_stat);
1197                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1198                         return retval;
1199                 if (debug_level >= 3)
1200                 {
1201                         alive_sleep(100);
1202                 } else
1203                 {
1204                         keep_alive();
1205                 }
1206         }
1207         if (timeout)
1208         {
1209                 LOG_ERROR("Failed to halt CPU after 1 sec");
1210                 return ERROR_TARGET_TIMEOUT;
1211         }
1212         target->state = TARGET_HALTED;
1213
1214         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1215          * ensure that DBGRQ is cleared
1216          */
1217         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1218         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1219         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1220         embeddedice_store_reg(dbg_ctrl);
1221
1222         if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1223         {
1224                 return retval;
1225         }
1226
1227         /* if the target is in Thumb state, change to ARM state */
1228         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1229         {
1230                 uint32_t r0_thumb, pc_thumb;
1231                 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1232                 /* Entered debug from Thumb mode */
1233                 arm->core_state = ARM_STATE_THUMB;
1234                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1235         }
1236
1237         /* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */
1238
1239         /* all register content is now invalid */
1240         register_cache_invalidate(arm->core_cache);
1241
1242         /* SVC, ARM state, IRQ and FIQ disabled */
1243         uint32_t cpsr;
1244
1245         cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1246         cpsr &= ~0xff;
1247         cpsr |= 0xd3;
1248         arm_set_cpsr(arm, cpsr);
1249         arm->cpsr->dirty = 1;
1250
1251         /* start fetching from 0x0 */
1252         buf_set_u32(arm->pc->value, 0, 32, 0x0);
1253         arm->pc->dirty = 1;
1254         arm->pc->valid = 1;
1255
1256         /* reset registers */
1257         for (i = 0; i <= 14; i++)
1258         {
1259                 struct reg *r = arm_reg_current(arm, i);
1260
1261                 buf_set_u32(r->value, 0, 32, 0xffffffff);
1262                 r->dirty = 1;
1263                 r->valid = 1;
1264         }
1265
1266         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1267         {
1268                 return retval;
1269         }
1270
1271         return ERROR_OK;
1272 }
1273
1274 /**
1275  * Halt an ARM7/9 target.  This is accomplished by either asserting the DBGRQ
1276  * line or by programming a watchpoint to trigger on any address.  It is
1277  * considered a bug to call this function while the target is in the
1278  * TARGET_RESET state.
1279  *
1280  * @param target Pointer to the ARM7/9 target to be halted
1281  * @return Always ERROR_OK
1282  */
1283 int arm7_9_halt(struct target *target)
1284 {
1285         if (target->state == TARGET_RESET)
1286         {
1287                 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1288                 return ERROR_OK;
1289         }
1290
1291         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1292         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1293
1294         LOG_DEBUG("target->state: %s",
1295                   target_state_name(target));
1296
1297         if (target->state == TARGET_HALTED)
1298         {
1299                 LOG_DEBUG("target was already halted");
1300                 return ERROR_OK;
1301         }
1302
1303         if (target->state == TARGET_UNKNOWN)
1304         {
1305                 LOG_WARNING("target was in unknown state when halt was requested");
1306         }
1307
1308         if (arm7_9->use_dbgrq)
1309         {
1310                 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1311                  */
1312                 if (arm7_9->set_special_dbgrq) {
1313                         arm7_9->set_special_dbgrq(target);
1314                 } else {
1315                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1316                         embeddedice_store_reg(dbg_ctrl);
1317                 }
1318         }
1319         else
1320         {
1321                 /* program watchpoint unit to match on any address
1322                  */
1323                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1324                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1325                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1326                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1327         }
1328
1329         target->debug_reason = DBG_REASON_DBGRQ;
1330
1331         return ERROR_OK;
1332 }
1333
1334 /**
1335  * Handle an ARM7/9 target's entry into debug mode.  The halt is cleared on the
1336  * ARM.  The JTAG queue is then executed and the reason for debug entry is
1337  * examined.  Once done, the target is verified to be halted and the processor
1338  * is forced into ARM mode.  The core registers are saved for the current core
1339  * mode and the program counter (register 15) is updated as needed.  The core
1340  * registers and CPSR and SPSR are saved for restoration later.
1341  *
1342  * @param target Pointer to target that is entering debug mode
1343  * @return Error code if anything fails, otherwise ERROR_OK
1344  */
1345 static int arm7_9_debug_entry(struct target *target)
1346 {
1347         int i;
1348         uint32_t context[16];
1349         uint32_t* context_p[16];
1350         uint32_t r0_thumb, pc_thumb;
1351         uint32_t cpsr, cpsr_mask = 0;
1352         int retval;
1353         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1354         struct arm *arm = &arm7_9->arm;
1355         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1356         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1357
1358 #ifdef _DEBUG_ARM7_9_
1359         LOG_DEBUG("-");
1360 #endif
1361
1362         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1363          * ensure that DBGRQ is cleared
1364          */
1365         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1366         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1367         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1368         embeddedice_store_reg(dbg_ctrl);
1369
1370         if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1371         {
1372                 return retval;
1373         }
1374
1375         if ((retval = jtag_execute_queue()) != ERROR_OK)
1376         {
1377                 return retval;
1378         }
1379
1380         if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1381                 return retval;
1382
1383
1384         if (target->state != TARGET_HALTED)
1385         {
1386                 LOG_WARNING("target not halted");
1387                 return ERROR_TARGET_NOT_HALTED;
1388         }
1389
1390         /* if the target is in Thumb state, change to ARM state */
1391         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1392         {
1393                 LOG_DEBUG("target entered debug from Thumb state");
1394                 /* Entered debug from Thumb mode */
1395                 arm->core_state = ARM_STATE_THUMB;
1396                 cpsr_mask = 1 << 5;
1397                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1398                 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
1399                         ", pc_thumb: 0x%8.8" PRIx32, r0_thumb, pc_thumb);
1400         } else if (buf_get_u32(dbg_stat->value, 5, 1)) {
1401                 /* \todo Get some vaguely correct handling of Jazelle, if
1402                  * anyone ever uses it and full info becomes available.
1403                  * See ARM9EJS TRM B.7.1 for how to switch J->ARM; and
1404                  * B.7.3 for the reverse.  That'd be the bare minimum...
1405                  */
1406                 LOG_DEBUG("target entered debug from Jazelle state");
1407                 arm->core_state = ARM_STATE_JAZELLE;
1408                 cpsr_mask = 1 << 24;
1409                 LOG_ERROR("Jazelle debug entry -- BROKEN!");
1410         } else {
1411                 LOG_DEBUG("target entered debug from ARM state");
1412                 /* Entered debug from ARM mode */
1413                 arm->core_state = ARM_STATE_ARM;
1414         }
1415
1416         for (i = 0; i < 16; i++)
1417                 context_p[i] = &context[i];
1418         /* save core registers (r0 - r15 of current core mode) */
1419         arm7_9->read_core_regs(target, 0xffff, context_p);
1420
1421         arm7_9->read_xpsr(target, &cpsr, 0);
1422
1423         if ((retval = jtag_execute_queue()) != ERROR_OK)
1424                 return retval;
1425
1426         /* Sync our CPSR copy with J or T bits EICE reported, but
1427          * which we then erased by putting the core into ARM mode.
1428          */
1429         arm_set_cpsr(arm, cpsr | cpsr_mask);
1430
1431         if (!is_arm_mode(arm->core_mode))
1432         {
1433                 target->state = TARGET_UNKNOWN;
1434                 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1435                 return ERROR_TARGET_FAILURE;
1436         }
1437
1438         LOG_DEBUG("target entered debug state in %s mode",
1439                          arm_mode_name(arm->core_mode));
1440
1441         if (arm->core_state == ARM_STATE_THUMB)
1442         {
1443                 LOG_DEBUG("thumb state, applying fixups");
1444                 context[0] = r0_thumb;
1445                 context[15] = pc_thumb;
1446         } else if (arm->core_state == ARM_STATE_ARM)
1447         {
1448                 /* adjust value stored by STM */
1449                 context[15] -= 3 * 4;
1450         }
1451
1452         if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
1453                 context[15] -= 3 * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2);
1454         else
1455                 context[15] -= arm7_9->dbgreq_adjust_pc * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2);
1456
1457         for (i = 0; i <= 15; i++)
1458         {
1459                 struct reg *r = arm_reg_current(arm, i);
1460
1461                 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
1462
1463                 buf_set_u32(r->value, 0, 32, context[i]);
1464                 /* r0 and r15 (pc) have to be restored later */
1465                 r->dirty = (i == 0) || (i == 15);
1466                 r->valid = 1;
1467         }
1468
1469         LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
1470
1471         /* exceptions other than USR & SYS have a saved program status register */
1472         if (arm->spsr) {
1473                 uint32_t spsr;
1474                 arm7_9->read_xpsr(target, &spsr, 1);
1475                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1476                 {
1477                         return retval;
1478                 }
1479                 buf_set_u32(arm->spsr->value, 0, 32, spsr);
1480                 arm->spsr->dirty = 0;
1481                 arm->spsr->valid = 1;
1482         }
1483
1484         if ((retval = jtag_execute_queue()) != ERROR_OK)
1485                 return retval;
1486
1487         if (arm7_9->post_debug_entry)
1488         {
1489                 retval = arm7_9->post_debug_entry(target);
1490                 if (retval != ERROR_OK)
1491                         return retval;
1492         }
1493
1494         return ERROR_OK;
1495 }
1496
1497 /**
1498  * Validate the full context for an ARM7/9 target in all processor modes.  If
1499  * there are any invalid registers for the target, they will all be read.  This
1500  * includes the PSR.
1501  *
1502  * @param target Pointer to the ARM7/9 target to capture the full context from
1503  * @return Error if the target is not halted, has an invalid core mode, or if
1504  *         the JTAG queue fails to execute
1505  */
1506 static int arm7_9_full_context(struct target *target)
1507 {
1508         int i;
1509         int retval;
1510         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1511         struct arm *arm = &arm7_9->arm;
1512
1513         LOG_DEBUG("-");
1514
1515         if (target->state != TARGET_HALTED)
1516         {
1517                 LOG_WARNING("target not halted");
1518                 return ERROR_TARGET_NOT_HALTED;
1519         }
1520
1521         if (!is_arm_mode(arm->core_mode))
1522         {
1523                 LOG_ERROR("not a valid arm core mode - communication failure?");
1524                 return ERROR_FAIL;
1525         }
1526
1527         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1528          * SYS shares registers with User, so we don't touch SYS
1529          */
1530         for (i = 0; i < 6; i++)
1531         {
1532                 uint32_t mask = 0;
1533                 uint32_t* reg_p[16];
1534                 int j;
1535                 int valid = 1;
1536
1537                 /* check if there are invalid registers in the current mode
1538                  */
1539                 for (j = 0; j <= 16; j++)
1540                 {
1541                         if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1542                                 valid = 0;
1543                 }
1544
1545                 if (!valid)
1546                 {
1547                         uint32_t tmp_cpsr;
1548
1549                         /* change processor mode (and mask T bit) */
1550                         tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8)
1551                                         & 0xe0;
1552                         tmp_cpsr |= armv4_5_number_to_mode(i);
1553                         tmp_cpsr &= ~0x20;
1554                         arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1555
1556                         for (j = 0; j < 15; j++)
1557                         {
1558                                 if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1559                                 {
1560                                         reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache,
1561                                                         armv4_5_number_to_mode(i), j).value;
1562                                         mask |= 1 << j;
1563                                         ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1564                                         ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1565                                 }
1566                         }
1567
1568                         /* if only the PSR is invalid, mask is all zeroes */
1569                         if (mask)
1570                                 arm7_9->read_core_regs(target, mask, reg_p);
1571
1572                         /* check if the PSR has to be read */
1573                         if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1574                         {
1575                                 arm7_9->read_xpsr(target, (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache,
1576                                                 armv4_5_number_to_mode(i), 16).value, 1);
1577                                 ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1578                                 ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1579                         }
1580                 }
1581         }
1582
1583         /* restore processor mode (mask T bit) */
1584         arm7_9->write_xpsr_im8(target,
1585                         buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20,
1586                         0, 0);
1587
1588         if ((retval = jtag_execute_queue()) != ERROR_OK)
1589         {
1590                 return retval;
1591         }
1592         return ERROR_OK;
1593 }
1594
1595 /**
1596  * Restore the processor context on an ARM7/9 target.  The full processor
1597  * context is analyzed to see if any of the registers are dirty on this end, but
1598  * have a valid new value.  If this is the case, the processor is changed to the
1599  * appropriate mode and the new register values are written out to the
1600  * processor.  If there happens to be a dirty register with an invalid value, an
1601  * error will be logged.
1602  *
1603  * @param target Pointer to the ARM7/9 target to have its context restored
1604  * @return Error status if the target is not halted or the core mode in the
1605  *         armv4_5 struct is invalid.
1606  */
1607 static int arm7_9_restore_context(struct target *target)
1608 {
1609         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1610         struct arm *arm = &arm7_9->arm;
1611         struct reg *reg;
1612         enum arm_mode current_mode = arm->core_mode;
1613         int i, j;
1614         int dirty;
1615         int mode_change;
1616
1617         LOG_DEBUG("-");
1618
1619         if (target->state != TARGET_HALTED)
1620         {
1621                 LOG_WARNING("target not halted");
1622                 return ERROR_TARGET_NOT_HALTED;
1623         }
1624
1625         if (arm7_9->pre_restore_context)
1626                 arm7_9->pre_restore_context(target);
1627
1628         if (!is_arm_mode(arm->core_mode))
1629         {
1630                 LOG_ERROR("not a valid arm core mode - communication failure?");
1631                 return ERROR_FAIL;
1632         }
1633
1634         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1635          * SYS shares registers with User, so we don't touch SYS
1636          */
1637         for (i = 0; i < 6; i++)
1638         {
1639                 LOG_DEBUG("examining %s mode",
1640                                 arm_mode_name(arm->core_mode));
1641                 dirty = 0;
1642                 mode_change = 0;
1643                 /* check if there are dirty registers in the current mode
1644                 */
1645                 for (j = 0; j <= 16; j++)
1646                 {
1647                         reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j);
1648                         if (reg->dirty == 1)
1649                         {
1650                                 if (reg->valid == 1)
1651                                 {
1652                                         dirty = 1;
1653                                         LOG_DEBUG("examining dirty reg: %s", reg->name);
1654                                         struct arm_reg *reg_arch_info;
1655                                         reg_arch_info = reg->arch_info;
1656                                         if ((reg_arch_info->mode != ARM_MODE_ANY)
1657                                                 && (reg_arch_info->mode != current_mode)
1658                                                 && !((reg_arch_info->mode == ARM_MODE_USR)
1659                                                 && (arm->core_mode == ARM_MODE_SYS))
1660                                                 && !((reg_arch_info->mode == ARM_MODE_SYS)
1661                                                 && (arm->core_mode == ARM_MODE_USR)))
1662                                         {
1663                                                 mode_change = 1;
1664                                                 LOG_DEBUG("require mode change");
1665                                         }
1666                                 }
1667                                 else
1668                                 {
1669                                         LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1670                                 }
1671                         }
1672                 }
1673
1674                 if (dirty)
1675                 {
1676                         uint32_t mask = 0x0;
1677                         int num_regs = 0;
1678                         uint32_t regs[16];
1679
1680                         if (mode_change)
1681                         {
1682                                 uint32_t tmp_cpsr;
1683
1684                                 /* change processor mode (mask T bit) */
1685                                 tmp_cpsr = buf_get_u32(arm->cpsr->value,
1686                                                 0, 8) & 0xe0;
1687                                 tmp_cpsr |= armv4_5_number_to_mode(i);
1688                                 tmp_cpsr &= ~0x20;
1689                                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1690                                 current_mode = armv4_5_number_to_mode(i);
1691                         }
1692
1693                         for (j = 0; j <= 14; j++)
1694                         {
1695                                 reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j);
1696
1697                                 if (reg->dirty == 1)
1698                                 {
1699                                         regs[j] = buf_get_u32(reg->value, 0, 32);
1700                                         mask |= 1 << j;
1701                                         num_regs++;
1702                                         reg->dirty = 0;
1703                                         reg->valid = 1;
1704                                         LOG_DEBUG("writing register %i mode %s "
1705                                                 "with value 0x%8.8" PRIx32, j,
1706                                                 arm_mode_name(arm->core_mode),
1707                                                 regs[j]);
1708                                 }
1709                         }
1710
1711                         if (mask)
1712                         {
1713                                 arm7_9->write_core_regs(target, mask, regs);
1714                         }
1715
1716                         reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16);
1717                         struct arm_reg *reg_arch_info;
1718                         reg_arch_info = reg->arch_info;
1719                         if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
1720                         {
1721                                 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
1722                                 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1723                         }
1724                 }
1725         }
1726
1727         if (!arm->cpsr->dirty && (arm->core_mode != current_mode)) {
1728                 /* restore processor mode (mask T bit) */
1729                 uint32_t tmp_cpsr;
1730
1731                 tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xE0;
1732                 tmp_cpsr |= armv4_5_number_to_mode(i);
1733                 tmp_cpsr &= ~0x20;
1734                 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
1735                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1736
1737         } else if (arm->cpsr->dirty) {
1738                 /* CPSR has been changed, full restore necessary (mask T bit) */
1739                 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1740                                 buf_get_u32(arm->cpsr->value, 0, 32));
1741                 arm7_9->write_xpsr(target,
1742                                 buf_get_u32(arm->cpsr->value, 0, 32)
1743                                 & ~0x20, 0);
1744                 arm->cpsr->dirty = 0;
1745                 arm->cpsr->valid = 1;
1746         }
1747
1748         /* restore PC */
1749         LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
1750                         buf_get_u32(arm->pc->value, 0, 32));
1751         arm7_9->write_pc(target, buf_get_u32(arm->pc->value, 0, 32));
1752         arm->pc->dirty = 0;
1753
1754         return ERROR_OK;
1755 }
1756
1757 /**
1758  * Restart the core of an ARM7/9 target.  A RESTART command is sent to the
1759  * instruction register and the JTAG state is set to TAP_IDLE causing a core
1760  * restart.
1761  *
1762  * @param target Pointer to the ARM7/9 target to be restarted
1763  * @return Result of executing the JTAG queue
1764  */
1765 static int arm7_9_restart_core(struct target *target)
1766 {
1767         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1768         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
1769         int retval;
1770
1771         /* set RESTART instruction */
1772         if (arm7_9->need_bypass_before_restart) {
1773                 arm7_9->need_bypass_before_restart = 0;
1774
1775                 retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
1776                 if (retval != ERROR_OK)
1777                         return retval;
1778         }
1779         retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
1780         if (retval != ERROR_OK)
1781                 return retval;
1782
1783         jtag_add_runtest(1, TAP_IDLE);
1784         return jtag_execute_queue();
1785 }
1786
1787 /**
1788  * Enable the watchpoints on an ARM7/9 target.  The target's watchpoints are
1789  * iterated through and are set on the target if they aren't already set.
1790  *
1791  * @param target Pointer to the ARM7/9 target to enable watchpoints on
1792  */
1793 static void arm7_9_enable_watchpoints(struct target *target)
1794 {
1795         struct watchpoint *watchpoint = target->watchpoints;
1796
1797         while (watchpoint)
1798         {
1799                 if (watchpoint->set == 0)
1800                         arm7_9_set_watchpoint(target, watchpoint);
1801                 watchpoint = watchpoint->next;
1802         }
1803 }
1804
1805 /**
1806  * Enable the breakpoints on an ARM7/9 target.  The target's breakpoints are
1807  * iterated through and are set on the target.
1808  *
1809  * @param target Pointer to the ARM7/9 target to enable breakpoints on
1810  */
1811 static void arm7_9_enable_breakpoints(struct target *target)
1812 {
1813         struct breakpoint *breakpoint = target->breakpoints;
1814
1815         /* set any pending breakpoints */
1816         while (breakpoint)
1817         {
1818                 arm7_9_set_breakpoint(target, breakpoint);
1819                 breakpoint = breakpoint->next;
1820         }
1821 }
1822
1823 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
1824 {
1825         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1826         struct arm *arm = &arm7_9->arm;
1827         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1828         int err, retval = ERROR_OK;
1829
1830         LOG_DEBUG("-");
1831
1832         if (target->state != TARGET_HALTED)
1833         {
1834                 LOG_WARNING("target not halted");
1835                 return ERROR_TARGET_NOT_HALTED;
1836         }
1837
1838         if (!debug_execution)
1839         {
1840                 target_free_all_working_areas(target);
1841         }
1842
1843         /* current = 1: continue on current pc, otherwise continue at <address> */
1844         if (!current)
1845                 buf_set_u32(arm->pc->value, 0, 32, address);
1846
1847         uint32_t current_pc;
1848         current_pc = buf_get_u32(arm->pc->value, 0, 32);
1849
1850         /* the front-end may request us not to handle breakpoints */
1851         if (handle_breakpoints)
1852         {
1853                 struct breakpoint *breakpoint;
1854                 breakpoint = breakpoint_find(target,
1855                                 buf_get_u32(arm->pc->value, 0, 32));
1856                 if (breakpoint != NULL)
1857                 {
1858                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
1859                         if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1860                         {
1861                                 return retval;
1862                         }
1863
1864                         /* calculate PC of next instruction */
1865                         uint32_t next_pc;
1866                         if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1867                         {
1868                                 uint32_t current_opcode;
1869                                 target_read_u32(target, current_pc, &current_opcode);
1870                                 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1871                                 return retval;
1872                         }
1873
1874                         LOG_DEBUG("enable single-step");
1875                         arm7_9->enable_single_step(target, next_pc);
1876
1877                         target->debug_reason = DBG_REASON_SINGLESTEP;
1878
1879                         if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1880                                 return retval;
1881
1882                         if (arm->core_state == ARM_STATE_ARM)
1883                                 arm7_9->branch_resume(target);
1884                         else if (arm->core_state == ARM_STATE_THUMB)
1885                                 arm7_9->branch_resume_thumb(target);
1886                         else {
1887                                 LOG_ERROR("unhandled core state");
1888                                 return ERROR_FAIL;
1889                         }
1890
1891                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1892                         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1893                         err = arm7_9_execute_sys_speed(target);
1894
1895                         LOG_DEBUG("disable single-step");
1896                         arm7_9->disable_single_step(target);
1897
1898                         if (err != ERROR_OK)
1899                         {
1900                                 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1901                                 {
1902                                         return retval;
1903                                 }
1904                                 target->state = TARGET_UNKNOWN;
1905                                 return err;
1906                         }
1907
1908                         retval = arm7_9_debug_entry(target);
1909                         if (retval != ERROR_OK)
1910                                 return retval;
1911                         LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
1912                                         buf_get_u32(arm->pc->value, 0, 32));
1913
1914                         LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1915                         if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1916                         {
1917                                 return retval;
1918                         }
1919                 }
1920         }
1921
1922         /* enable any pending breakpoints and watchpoints */
1923         arm7_9_enable_breakpoints(target);
1924         arm7_9_enable_watchpoints(target);
1925
1926         if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1927                 return retval;
1928
1929         if (arm->core_state == ARM_STATE_ARM)
1930                 arm7_9->branch_resume(target);
1931         else if (arm->core_state == ARM_STATE_THUMB)
1932                 arm7_9->branch_resume_thumb(target);
1933         else {
1934                 LOG_ERROR("unhandled core state");
1935                 return ERROR_FAIL;
1936         }
1937
1938         /* deassert DBGACK and INTDIS */
1939         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1940         /* INTDIS only when we really resume, not during debug execution */
1941         if (!debug_execution)
1942                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1943         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1944
1945         if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1946         {
1947                 return retval;
1948         }
1949
1950         target->debug_reason = DBG_REASON_NOTHALTED;
1951
1952         if (!debug_execution)
1953         {
1954                 /* registers are now invalid */
1955                 register_cache_invalidate(arm->core_cache);
1956                 target->state = TARGET_RUNNING;
1957                 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1958                 {
1959                         return retval;
1960                 }
1961         }
1962         else
1963         {
1964                 target->state = TARGET_DEBUG_RUNNING;
1965                 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1966                 {
1967                         return retval;
1968                 }
1969         }
1970
1971         LOG_DEBUG("target resumed");
1972
1973         return ERROR_OK;
1974 }
1975
1976 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
1977 {
1978         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1979         struct arm *arm = &arm7_9->arm;
1980         uint32_t current_pc;
1981         current_pc = buf_get_u32(arm->pc->value, 0, 32);
1982
1983         if (next_pc != current_pc)
1984         {
1985                 /* setup an inverse breakpoint on the current PC
1986                 * - comparator 1 matches the current address
1987                 * - rangeout from comparator 1 is connected to comparator 0 rangein
1988                 * - comparator 0 matches any address, as long as rangein is low */
1989                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1990                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1991                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1992                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
1993                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
1994                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1995                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1996                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1997                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1998         }
1999         else
2000         {
2001                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
2002                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
2003                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
2004                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
2005                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
2006                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
2007                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
2008                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
2009                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
2010         }
2011 }
2012
2013 void arm7_9_disable_eice_step(struct target *target)
2014 {
2015         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2016
2017         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
2018         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
2019         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
2020         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
2021         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
2022         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
2023         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
2024         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
2025         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
2026 }
2027
2028 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
2029 {
2030         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2031         struct arm *arm = &arm7_9->arm;
2032         struct breakpoint *breakpoint = NULL;
2033         int err, retval;
2034
2035         if (target->state != TARGET_HALTED)
2036         {
2037                 LOG_WARNING("target not halted");
2038                 return ERROR_TARGET_NOT_HALTED;
2039         }
2040
2041         /* current = 1: continue on current pc, otherwise continue at <address> */
2042         if (!current)
2043                 buf_set_u32(arm->pc->value, 0, 32, address);
2044
2045         uint32_t current_pc = buf_get_u32(arm->pc->value, 0, 32);
2046
2047         /* the front-end may request us not to handle breakpoints */
2048         if (handle_breakpoints)
2049                 breakpoint = breakpoint_find(target, current_pc);
2050         if (breakpoint != NULL) {
2051                 retval = arm7_9_unset_breakpoint(target, breakpoint);
2052                 if (retval != ERROR_OK)
2053                         return retval;
2054         }
2055
2056         target->debug_reason = DBG_REASON_SINGLESTEP;
2057
2058         /* calculate PC of next instruction */
2059         uint32_t next_pc;
2060         if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
2061         {
2062                 uint32_t current_opcode;
2063                 target_read_u32(target, current_pc, &current_opcode);
2064                 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
2065                 return retval;
2066         }
2067
2068         if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
2069                 return retval;
2070
2071         arm7_9->enable_single_step(target, next_pc);
2072
2073         if (arm->core_state == ARM_STATE_ARM)
2074                 arm7_9->branch_resume(target);
2075         else if (arm->core_state == ARM_STATE_THUMB)
2076                 arm7_9->branch_resume_thumb(target);
2077         else {
2078                 LOG_ERROR("unhandled core state");
2079                 return ERROR_FAIL;
2080         }
2081
2082         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
2083         {
2084                 return retval;
2085         }
2086
2087         err = arm7_9_execute_sys_speed(target);
2088         arm7_9->disable_single_step(target);
2089
2090         /* registers are now invalid */
2091         register_cache_invalidate(arm->core_cache);
2092
2093         if (err != ERROR_OK)
2094         {
2095                 target->state = TARGET_UNKNOWN;
2096         } else {
2097                 retval = arm7_9_debug_entry(target);
2098                 if (retval != ERROR_OK)
2099                         return retval;
2100                 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
2101                 {
2102                         return retval;
2103                 }
2104                 LOG_DEBUG("target stepped");
2105         }
2106
2107         if (breakpoint)
2108                 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
2109                 {
2110                         return retval;
2111                 }
2112
2113         return err;
2114 }
2115
2116 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
2117                 int num, enum arm_mode mode)
2118 {
2119         uint32_t* reg_p[16];
2120         int retval;
2121         struct arm_reg *areg = r->arch_info;
2122         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2123         struct arm *arm = &arm7_9->arm;
2124
2125         if (!is_arm_mode(arm->core_mode))
2126                 return ERROR_FAIL;
2127         if ((num < 0) || (num > 16))
2128                 return ERROR_COMMAND_SYNTAX_ERROR;
2129
2130         if ((mode != ARM_MODE_ANY)
2131                         && (mode != arm->core_mode)
2132                         && (areg->mode != ARM_MODE_ANY))
2133         {
2134                 uint32_t tmp_cpsr;
2135
2136                 /* change processor mode (mask T bit) */
2137                 tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xE0;
2138                 tmp_cpsr |= mode;
2139                 tmp_cpsr &= ~0x20;
2140                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2141         }
2142
2143         uint32_t value = 0;
2144         if ((num >= 0) && (num <= 15))
2145         {
2146                 /* read a normal core register */
2147                 reg_p[num] = &value;
2148
2149                 arm7_9->read_core_regs(target, 1 << num, reg_p);
2150         }
2151         else
2152         {
2153                 /* read a program status register
2154                  * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2155                  */
2156                 arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
2157         }
2158
2159         if ((retval = jtag_execute_queue()) != ERROR_OK)
2160         {
2161                 return retval;
2162         }
2163
2164         r->valid = 1;
2165         r->dirty = 0;
2166         buf_set_u32(r->value, 0, 32, value);
2167
2168         if ((mode != ARM_MODE_ANY)
2169                         && (mode != arm->core_mode)
2170                         && (areg->mode != ARM_MODE_ANY))        {
2171                 /* restore processor mode (mask T bit) */
2172                 arm7_9->write_xpsr_im8(target,
2173                                 buf_get_u32(arm->cpsr->value, 0, 8)
2174                                         & ~0x20, 0, 0);
2175         }
2176
2177         return ERROR_OK;
2178 }
2179
2180 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
2181                 int num, enum arm_mode mode, uint32_t value)
2182 {
2183         uint32_t reg[16];
2184         struct arm_reg *areg = r->arch_info;
2185         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2186         struct arm *arm = &arm7_9->arm;
2187
2188         if (!is_arm_mode(arm->core_mode))
2189                 return ERROR_FAIL;
2190         if ((num < 0) || (num > 16))
2191                 return ERROR_COMMAND_SYNTAX_ERROR;
2192
2193         if ((mode != ARM_MODE_ANY)
2194                         && (mode != arm->core_mode)
2195                         && (areg->mode != ARM_MODE_ANY))        {
2196                 uint32_t tmp_cpsr;
2197
2198                 /* change processor mode (mask T bit) */
2199                 tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xE0;
2200                 tmp_cpsr |= mode;
2201                 tmp_cpsr &= ~0x20;
2202                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2203         }
2204
2205         if ((num >= 0) && (num <= 15))
2206         {
2207                 /* write a normal core register */
2208                 reg[num] = value;
2209
2210                 arm7_9->write_core_regs(target, 1 << num, reg);
2211         }
2212         else
2213         {
2214                 /* write a program status register
2215                 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2216                 */
2217                 int spsr = (areg->mode != ARM_MODE_ANY);
2218
2219                 /* if we're writing the CPSR, mask the T bit */
2220                 if (!spsr)
2221                         value &= ~0x20;
2222
2223                 arm7_9->write_xpsr(target, value, spsr);
2224         }
2225
2226         r->valid = 1;
2227         r->dirty = 0;
2228
2229         if ((mode != ARM_MODE_ANY)
2230                         && (mode != arm->core_mode)
2231                         && (areg->mode != ARM_MODE_ANY))        {
2232                 /* restore processor mode (mask T bit) */
2233                 arm7_9->write_xpsr_im8(target,
2234                                 buf_get_u32(arm->cpsr->value, 0, 8)
2235                                         & ~0x20, 0, 0);
2236         }
2237
2238         return jtag_execute_queue();
2239 }
2240
2241 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2242 {
2243         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2244         struct arm *arm = &arm7_9->arm;
2245         uint32_t reg[16];
2246         uint32_t num_accesses = 0;
2247         int thisrun_accesses;
2248         int i;
2249         uint32_t cpsr;
2250         int retval;
2251         int last_reg = 0;
2252
2253         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
2254
2255         if (target->state != TARGET_HALTED)
2256         {
2257                 LOG_WARNING("target not halted");
2258                 return ERROR_TARGET_NOT_HALTED;
2259         }
2260
2261         /* sanitize arguments */
2262         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2263                 return ERROR_COMMAND_SYNTAX_ERROR;
2264
2265         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2266                 return ERROR_TARGET_UNALIGNED_ACCESS;
2267
2268         /* load the base register with the address of the first word */
2269         reg[0] = address;
2270         arm7_9->write_core_regs(target, 0x1, reg);
2271
2272         int j = 0;
2273
2274         switch (size)
2275         {
2276                 case 4:
2277                         while (num_accesses < count)
2278                         {
2279                                 uint32_t reg_list;
2280                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2281                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2282
2283                                 if (last_reg <= thisrun_accesses)
2284                                         last_reg = thisrun_accesses;
2285
2286                                 arm7_9->load_word_regs(target, reg_list);
2287
2288                                 /* fast memory reads are only safe when the target is running
2289                                  * from a sufficiently high clock (32 kHz is usually too slow)
2290                                  */
2291                                 if (arm7_9->fast_memory_access)
2292                                         retval = arm7_9_execute_fast_sys_speed(target);
2293                                 else
2294                                         retval = arm7_9_execute_sys_speed(target);
2295                                 if (retval != ERROR_OK)
2296                                         return retval;
2297
2298                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2299
2300                                 /* advance buffer, count number of accesses */
2301                                 buffer += thisrun_accesses * 4;
2302                                 num_accesses += thisrun_accesses;
2303
2304                                 if ((j++%1024) == 0)
2305                                 {
2306                                         keep_alive();
2307                                 }
2308                         }
2309                         break;
2310                 case 2:
2311                         while (num_accesses < count)
2312                         {
2313                                 uint32_t reg_list;
2314                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2315                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2316
2317                                 for (i = 1; i <= thisrun_accesses; i++)
2318                                 {
2319                                         if (i > last_reg)
2320                                                 last_reg = i;
2321                                         arm7_9->load_hword_reg(target, i);
2322                                         /* fast memory reads are only safe when the target is running
2323                                          * from a sufficiently high clock (32 kHz is usually too slow)
2324                                          */
2325                                         if (arm7_9->fast_memory_access)
2326                                                 retval = arm7_9_execute_fast_sys_speed(target);
2327                                         else
2328                                                 retval = arm7_9_execute_sys_speed(target);
2329                                         if (retval != ERROR_OK)
2330                                         {
2331                                                 return retval;
2332                                         }
2333
2334                                 }
2335
2336                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2337
2338                                 /* advance buffer, count number of accesses */
2339                                 buffer += thisrun_accesses * 2;
2340                                 num_accesses += thisrun_accesses;
2341
2342                                 if ((j++%1024) == 0)
2343                                 {
2344                                         keep_alive();
2345                                 }
2346                         }
2347                         break;
2348                 case 1:
2349                         while (num_accesses < count)
2350                         {
2351                                 uint32_t reg_list;
2352                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2353                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2354
2355                                 for (i = 1; i <= thisrun_accesses; i++)
2356                                 {
2357                                         if (i > last_reg)
2358                                                 last_reg = i;
2359                                         arm7_9->load_byte_reg(target, i);
2360                                         /* fast memory reads are only safe when the target is running
2361                                          * from a sufficiently high clock (32 kHz is usually too slow)
2362                                          */
2363                                         if (arm7_9->fast_memory_access)
2364                                                 retval = arm7_9_execute_fast_sys_speed(target);
2365                                         else
2366                                                 retval = arm7_9_execute_sys_speed(target);
2367                                         if (retval != ERROR_OK)
2368                                         {
2369                                                 return retval;
2370                                         }
2371                                 }
2372
2373                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2374
2375                                 /* advance buffer, count number of accesses */
2376                                 buffer += thisrun_accesses * 1;
2377                                 num_accesses += thisrun_accesses;
2378
2379                                 if ((j++%1024) == 0)
2380                                 {
2381                                         keep_alive();
2382                                 }
2383                         }
2384                         break;
2385         }
2386
2387         if (!is_arm_mode(arm->core_mode))
2388                 return ERROR_FAIL;
2389
2390         for (i = 0; i <= last_reg; i++) {
2391                 struct reg *r = arm_reg_current(arm, i);
2392
2393                 r->dirty = r->valid;
2394         }
2395
2396         arm7_9->read_xpsr(target, &cpsr, 0);
2397         if ((retval = jtag_execute_queue()) != ERROR_OK)
2398         {
2399                 LOG_ERROR("JTAG error while reading cpsr");
2400                 return ERROR_TARGET_DATA_ABORT;
2401         }
2402
2403         if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT))
2404         {
2405                 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2406
2407                 arm7_9->write_xpsr_im8(target,
2408                                 buf_get_u32(arm->cpsr->value, 0, 8)
2409                                         & ~0x20, 0, 0);
2410
2411                 return ERROR_TARGET_DATA_ABORT;
2412         }
2413
2414         return ERROR_OK;
2415 }
2416
2417 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
2418 {
2419         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2420         struct arm *arm = &arm7_9->arm;
2421         struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2422
2423         uint32_t reg[16];
2424         uint32_t num_accesses = 0;
2425         int thisrun_accesses;
2426         int i;
2427         uint32_t cpsr;
2428         int retval;
2429         int last_reg = 0;
2430
2431 #ifdef _DEBUG_ARM7_9_
2432         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2433 #endif
2434
2435         if (target->state != TARGET_HALTED)
2436         {
2437                 LOG_WARNING("target not halted");
2438                 return ERROR_TARGET_NOT_HALTED;
2439         }
2440
2441         /* sanitize arguments */
2442         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2443                 return ERROR_COMMAND_SYNTAX_ERROR;
2444
2445         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2446                 return ERROR_TARGET_UNALIGNED_ACCESS;
2447
2448         /* load the base register with the address of the first word */
2449         reg[0] = address;
2450         arm7_9->write_core_regs(target, 0x1, reg);
2451
2452         /* Clear DBGACK, to make sure memory fetches work as expected */
2453         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2454         embeddedice_store_reg(dbg_ctrl);
2455
2456         switch (size)
2457         {
2458                 case 4:
2459                         while (num_accesses < count)
2460                         {
2461                                 uint32_t reg_list;
2462                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2463                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2464
2465                                 for (i = 1; i <= thisrun_accesses; i++)
2466                                 {
2467                                         if (i > last_reg)
2468                                                 last_reg = i;
2469                                         reg[i] = target_buffer_get_u32(target, buffer);
2470                                         buffer += 4;
2471                                 }
2472
2473                                 arm7_9->write_core_regs(target, reg_list, reg);
2474
2475                                 arm7_9->store_word_regs(target, reg_list);
2476
2477                                 /* fast memory writes are only safe when the target is running
2478                                  * from a sufficiently high clock (32 kHz is usually too slow)
2479                                  */
2480                                 if (arm7_9->fast_memory_access)
2481                                         retval = arm7_9_execute_fast_sys_speed(target);
2482                                 else
2483                                 {
2484                                         retval = arm7_9_execute_sys_speed(target);
2485
2486                                         /*
2487                                          * if memory writes are made when the clock is running slow
2488                                          * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
2489                                          * processor operations after a "reset halt" or "reset init",
2490                                          * need to immediately stroke the keep alive or will end up with
2491                                          * gdb "keep alive not sent error message" problem.
2492                                          */
2493
2494                                         keep_alive();
2495                                 }
2496
2497                                 if (retval != ERROR_OK)
2498                                 {
2499                                         return retval;
2500                                 }
2501
2502                                 num_accesses += thisrun_accesses;
2503                         }
2504                         break;
2505                 case 2:
2506                         while (num_accesses < count)
2507                         {
2508                                 uint32_t reg_list;
2509                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2510                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2511
2512                                 for (i = 1; i <= thisrun_accesses; i++)
2513                                 {
2514                                         if (i > last_reg)
2515                                                 last_reg = i;
2516                                         reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2517                                         buffer += 2;
2518                                 }
2519
2520                                 arm7_9->write_core_regs(target, reg_list, reg);
2521
2522                                 for (i = 1; i <= thisrun_accesses; i++)
2523                                 {
2524                                         arm7_9->store_hword_reg(target, i);
2525
2526                                         /* fast memory writes are only safe when the target is running
2527                                          * from a sufficiently high clock (32 kHz is usually too slow)
2528                                          */
2529                                         if (arm7_9->fast_memory_access)
2530                                                 retval = arm7_9_execute_fast_sys_speed(target);
2531                                         else
2532                                         {
2533                                                 retval = arm7_9_execute_sys_speed(target);
2534
2535                                                 /*
2536                                                  * if memory writes are made when the clock is running slow
2537                                                  * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
2538                                                  * processor operations after a "reset halt" or "reset init",
2539                                                  * need to immediately stroke the keep alive or will end up with
2540                                                  * gdb "keep alive not sent error message" problem.
2541                                                  */
2542
2543                                                 keep_alive();
2544                                         }
2545
2546                                         if (retval != ERROR_OK)
2547                                         {
2548                                                 return retval;
2549                                         }
2550                                 }
2551
2552                                 num_accesses += thisrun_accesses;
2553                         }
2554                         break;
2555                 case 1:
2556                         while (num_accesses < count)
2557                         {
2558                                 uint32_t reg_list;
2559                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2560                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2561
2562                                 for (i = 1; i <= thisrun_accesses; i++)
2563                                 {
2564                                         if (i > last_reg)
2565                                                 last_reg = i;
2566                                         reg[i] = *buffer++ & 0xff;
2567                                 }
2568
2569                                 arm7_9->write_core_regs(target, reg_list, reg);
2570
2571                                 for (i = 1; i <= thisrun_accesses; i++)
2572                                 {
2573                                         arm7_9->store_byte_reg(target, i);
2574                                         /* fast memory writes are only safe when the target is running
2575                                          * from a sufficiently high clock (32 kHz is usually too slow)
2576                                          */
2577                                         if (arm7_9->fast_memory_access)
2578                                                 retval = arm7_9_execute_fast_sys_speed(target);
2579                                         else
2580                                         {
2581                                                 retval = arm7_9_execute_sys_speed(target);
2582
2583                                                 /*
2584                                                  * if memory writes are made when the clock is running slow
2585                                                  * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
2586                                                  * processor operations after a "reset halt" or "reset init",
2587                                                  * need to immediately stroke the keep alive or will end up with
2588                                                  * gdb "keep alive not sent error message" problem.
2589                                                  */
2590
2591                                                 keep_alive();
2592                                         }
2593
2594                                         if (retval != ERROR_OK)
2595                                         {
2596                                                 return retval;
2597                                         }
2598
2599                                 }
2600
2601                                 num_accesses += thisrun_accesses;
2602                         }
2603                         break;
2604         }
2605
2606         /* Re-Set DBGACK */
2607         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2608         embeddedice_store_reg(dbg_ctrl);
2609
2610         if (!is_arm_mode(arm->core_mode))
2611                 return ERROR_FAIL;
2612
2613         for (i = 0; i <= last_reg; i++) {
2614                 struct reg *r = arm_reg_current(arm, i);
2615
2616                 r->dirty = r->valid;
2617         }
2618
2619         arm7_9->read_xpsr(target, &cpsr, 0);
2620         if ((retval = jtag_execute_queue()) != ERROR_OK)
2621         {
2622                 LOG_ERROR("JTAG error while reading cpsr");
2623                 return ERROR_TARGET_DATA_ABORT;
2624         }
2625
2626         if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT))
2627         {
2628                 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2629
2630                 arm7_9->write_xpsr_im8(target,
2631                                 buf_get_u32(arm->cpsr->value, 0, 8)
2632                                         & ~0x20, 0, 0);
2633
2634                 return ERROR_TARGET_DATA_ABORT;
2635         }
2636
2637         return ERROR_OK;
2638 }
2639
2640 static int dcc_count;
2641 static const uint8_t *dcc_buffer;
2642
2643 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
2644 {
2645         int retval = ERROR_OK;
2646         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2647
2648         if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
2649                 return retval;
2650
2651         int little = target->endianness == TARGET_LITTLE_ENDIAN;
2652         int count = dcc_count;
2653         const uint8_t *buffer = dcc_buffer;
2654         if (count > 2)
2655         {
2656                 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2657                  * core function repeated. */
2658                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2659                 buffer += 4;
2660
2661                 struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2662                 uint8_t reg_addr = ice_reg->addr & 0x1f;
2663                 struct jtag_tap *tap;
2664                 tap = ice_reg->jtag_info->tap;
2665
2666                 embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
2667                 buffer += (count-2)*4;
2668
2669                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2670         } else
2671         {
2672                 int i;
2673                 for (i = 0; i < count; i++)
2674                 {
2675                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2676                         buffer += 4;
2677                 }
2678         }
2679
2680         if ((retval = target_halt(target))!= ERROR_OK)
2681         {
2682                 return retval;
2683         }
2684         return target_wait_state(target, TARGET_HALTED, 500);
2685 }
2686
2687 static const uint32_t dcc_code[] =
2688 {
2689         /* r0 == input, points to memory buffer
2690          * r1 == scratch
2691          */
2692
2693         /* spin until DCC control (c0) reports data arrived */
2694         0xee101e10,     /* w: mrc p14, #0, r1, c0, c0 */
2695         0xe3110001,     /*    tst r1, #1              */
2696         0x0afffffc,     /*    bne w                   */
2697
2698         /* read word from DCC (c1), write to memory */
2699         0xee111e10,     /*    mrc p14, #0, r1, c1, c0 */
2700         0xe4801004,     /*    str r1, [r0], #4        */
2701
2702         /* repeat */
2703         0xeafffff9      /*    b   w                   */
2704 };
2705
2706 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer)
2707 {
2708         int retval;
2709         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2710         int i;
2711
2712         if (!arm7_9->dcc_downloads)
2713                 return target_write_memory(target, address, 4, count, buffer);
2714
2715         /* regrab previously allocated working_area, or allocate a new one */
2716         if (!arm7_9->dcc_working_area)
2717         {
2718                 uint8_t dcc_code_buf[6 * 4];
2719
2720                 /* make sure we have a working area */
2721                 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2722                 {
2723                         LOG_INFO("no working area available, falling back to memory writes");
2724                         return target_write_memory(target, address, 4, count, buffer);
2725                 }
2726
2727                 /* copy target instructions to target endianness */
2728                 for (i = 0; i < 6; i++)
2729                 {
2730                         target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2731                 }
2732
2733                 /* write DCC code to working area */
2734                 if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2735                 {
2736                         return retval;
2737                 }
2738         }
2739
2740         struct arm_algorithm armv4_5_info;
2741         struct reg_param reg_params[1];
2742
2743         armv4_5_info.common_magic = ARM_COMMON_MAGIC;
2744         armv4_5_info.core_mode = ARM_MODE_SVC;
2745         armv4_5_info.core_state = ARM_STATE_ARM;
2746
2747         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2748
2749         buf_set_u32(reg_params[0].value, 0, 32, address);
2750
2751         dcc_count = count;
2752         dcc_buffer = buffer;
2753         retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2754                         arm7_9->dcc_working_area->address,
2755                                 arm7_9->dcc_working_area->address + 6*4,
2756                         20*1000, &armv4_5_info, arm7_9_dcc_completion);
2757
2758         if (retval == ERROR_OK)
2759         {
2760                 uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
2761                 if (endaddress != (address + count*4))
2762                 {
2763                         LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
2764                         retval = ERROR_FAIL;
2765                 }
2766         }
2767
2768         destroy_reg_param(&reg_params[0]);
2769
2770         return retval;
2771 }
2772
2773 /**
2774  * Perform per-target setup that requires JTAG access.
2775  */
2776 int arm7_9_examine(struct target *target)
2777 {
2778         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2779         int retval;
2780
2781         if (!target_was_examined(target)) {
2782                 struct reg_cache *t, **cache_p;
2783
2784                 t = embeddedice_build_reg_cache(target, arm7_9);
2785                 if (t == NULL)
2786                         return ERROR_FAIL;
2787
2788                 cache_p = register_get_last_cache_p(&target->reg_cache);
2789                 (*cache_p) = t;
2790                 arm7_9->eice_cache = (*cache_p);
2791
2792                 if (arm7_9->arm.etm)
2793                         (*cache_p)->next = etm_build_reg_cache(target,
2794                                         &arm7_9->jtag_info,
2795                                         arm7_9->arm.etm);
2796
2797                 target_set_examined(target);
2798         }
2799
2800         retval = embeddedice_setup(target);
2801         if (retval == ERROR_OK)
2802                 retval = arm7_9_setup(target);
2803         if (retval == ERROR_OK && arm7_9->arm.etm)
2804                 retval = etm_setup(target);
2805         return retval;
2806 }
2807
2808
2809 int arm7_9_check_reset(struct target *target)
2810 {
2811         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2812
2813         if (get_target_reset_nag() && !arm7_9->dcc_downloads)
2814         {
2815                 LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.");
2816         }
2817
2818         if (get_target_reset_nag() && (target->working_area_size == 0))
2819         {
2820                 LOG_WARNING("NOTE! Severe performance degradation without working memory enabled.");
2821         }
2822
2823         if (get_target_reset_nag() && !arm7_9->fast_memory_access)
2824         {
2825                 LOG_WARNING("NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'.");
2826         }
2827
2828         return ERROR_OK;
2829 }
2830
2831 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
2832 {
2833         struct target *target = get_current_target(CMD_CTX);
2834         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2835
2836         if (!is_arm7_9(arm7_9))
2837         {
2838                 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2839                 return ERROR_TARGET_INVALID;
2840         }
2841
2842         if (CMD_ARGC > 0)
2843                 COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
2844
2845         command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2846
2847         return ERROR_OK;
2848 }
2849
2850 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
2851 {
2852         struct target *target = get_current_target(CMD_CTX);
2853         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2854
2855         if (!is_arm7_9(arm7_9))
2856         {
2857                 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2858                 return ERROR_TARGET_INVALID;
2859         }
2860
2861         if (CMD_ARGC > 0)
2862                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
2863
2864         command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2865
2866         return ERROR_OK;
2867 }
2868
2869 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
2870 {
2871         struct target *target = get_current_target(CMD_CTX);
2872         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2873
2874         if (!is_arm7_9(arm7_9))
2875         {
2876                 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2877                 return ERROR_TARGET_INVALID;
2878         }
2879
2880         if (CMD_ARGC > 0)
2881                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
2882
2883         command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2884
2885         return ERROR_OK;
2886 }
2887
2888 static int arm7_9_setup_semihosting(struct target *target, int enable)
2889 {
2890         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2891
2892         if (!is_arm7_9(arm7_9))
2893         {
2894                 LOG_USER("current target isn't an ARM7/ARM9 target");
2895                 return ERROR_TARGET_INVALID;
2896         }
2897
2898         if (arm7_9->has_vector_catch) {
2899                 struct reg *vector_catch = &arm7_9->eice_cache
2900                                 ->reg_list[EICE_VEC_CATCH];
2901
2902                 if (!vector_catch->valid)
2903                         embeddedice_read_reg(vector_catch);
2904                 buf_set_u32(vector_catch->value, 2, 1, enable);
2905                 embeddedice_store_reg(vector_catch);
2906         } else {
2907                 /* TODO: allow optional high vectors and/or BKPT_HARD */
2908                 if (enable)
2909                         breakpoint_add(target, 8, 4, BKPT_SOFT);
2910                 else
2911                         breakpoint_remove(target, 8);
2912         }
2913
2914         return ERROR_OK;
2915 }
2916
2917 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
2918 {
2919         int retval = ERROR_OK;
2920         struct arm *arm = &arm7_9->arm;
2921
2922         arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2923
2924         if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2925                 return retval;
2926
2927         /* caller must have allocated via calloc(), so everything's zeroed */
2928
2929         arm7_9->wp_available_max = 2;
2930
2931         arm7_9->fast_memory_access = false;
2932         arm7_9->dcc_downloads = false;
2933
2934         arm->arch_info = arm7_9;
2935         arm->read_core_reg = arm7_9_read_core_reg;
2936         arm->write_core_reg = arm7_9_write_core_reg;
2937         arm->full_context = arm7_9_full_context;
2938         arm->setup_semihosting = arm7_9_setup_semihosting;
2939
2940         retval = arm_init_arch_info(target, arm);
2941         if (retval != ERROR_OK)
2942                 return retval;
2943
2944         return target_register_timer_callback(arm7_9_handle_target_request,
2945                         1, 1, target);
2946 }
2947
2948 static const struct command_registration arm7_9_any_command_handlers[] = {
2949         {
2950                 "dbgrq",
2951                 .handler = handle_arm7_9_dbgrq_command,
2952                 .mode = COMMAND_ANY,
2953                 .usage = "['enable'|'disable']",
2954                 .help = "use EmbeddedICE dbgrq instead of breakpoint "
2955                         "for target halt requests",
2956         },
2957         {
2958                 "fast_memory_access",
2959                 .handler = handle_arm7_9_fast_memory_access_command,
2960                 .mode = COMMAND_ANY,
2961                 .usage = "['enable'|'disable']",
2962                 .help = "use fast memory accesses instead of slower "
2963                         "but potentially safer accesses",
2964         },
2965         {
2966                 "dcc_downloads",
2967                 .handler = handle_arm7_9_dcc_downloads_command,
2968                 .mode = COMMAND_ANY,
2969                 .usage = "['enable'|'disable']",
2970                 .help = "use DCC downloads for larger memory writes",
2971         },
2972         COMMAND_REGISTRATION_DONE
2973 };
2974 const struct command_registration arm7_9_command_handlers[] = {
2975         {
2976                 .chain = arm_command_handlers,
2977         },
2978         {
2979                 .chain = etm_command_handlers,
2980         },
2981         {
2982                 .name = "arm7_9",
2983                 .mode = COMMAND_ANY,
2984                 .help = "arm7/9 specific commands",
2985                 .usage = "",
2986                 .chain = arm7_9_any_command_handlers,
2987         },
2988         COMMAND_REGISTRATION_DONE
2989 };