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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2008 by Hongtao Zheng                                   *
  12  *   hontor@126.com                                                        *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  ***************************************************************************/
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include "replacements.h"
  34
  35 #include "embeddedice.h"
  36 #include "target.h"
  37 #include "target_request.h"
  38 #include "armv4_5.h"
  39 #include "arm_jtag.h"
  40 #include "jtag.h"
  41 #include "log.h"
  42 #include "arm7_9_common.h"
  43 #include "breakpoints.h"
  44 #include "time_support.h"
  45 #include "arm_simulator.h"
  46
  47 #include <stdlib.h>
  48 #include <string.h>
  49 #include <unistd.h>
  50
  51 #include <sys/types.h>
  52 #include <sys/stat.h>
  53 #include <sys/time.h>
  54 #include <errno.h>
  55
  56 int arm7_9_debug_entry(target_t *target);
  57 int arm7_9_enable_sw_bkpts(struct target_s *target);
  58
  59 /* command handler forward declarations */
  60 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  61 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  62 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  63 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  64 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  65 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  66 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  67 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  68
  69
  70 static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
  71 {
  72         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
  73         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  74         arm7_9->sw_breakpoints_added = 0;
  75         arm7_9->wp0_used = 0;
  76         arm7_9->wp1_used = arm7_9->wp1_used_default;
  77         arm7_9->wp_available = arm7_9->wp_available_max;
  78
  79         return jtag_execute_queue();
  80 }
  81
  82 /* set up embedded ice registers */
  83 static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
  84 {
  85         if (arm7_9->sw_breakpoints_added)
  86         {
  87                 return ERROR_OK;
  88         }
  89         if (arm7_9->wp_available < 1)
  90         {
  91                 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
  92                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  93         }
  94         arm7_9->wp_available--;
  95
  96         /* pick a breakpoint unit */
  97         if (!arm7_9->wp0_used)
  98         {
  99                 arm7_9->sw_breakpoints_added=1;
 100                 arm7_9->wp0_used = 3;
 101         } else if (!arm7_9->wp1_used)
 102         {
 103                 arm7_9->sw_breakpoints_added=2;
 104                 arm7_9->wp1_used = 3;
 105         }
 106         else
 107         {
 108                 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
 109                 return ERROR_FAIL;
 110         }
 111
 112         if (arm7_9->sw_breakpoints_added==1)
 113         {
 114                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
 115                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
 116                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
 117                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 118                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 119         }
 120         else if (arm7_9->sw_breakpoints_added==2)
 121         {
 122                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
 123                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
 124                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
 125                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 126                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 127         }
 128         else
 129         {
 130                 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
 131                 return ERROR_FAIL;
 132         }
 133
 134         return jtag_execute_queue();
 135 }
 136
 137 /* set things up after a reset / on startup */
 138 int arm7_9_setup(target_t *target)
 139 {
 140         armv4_5_common_t *armv4_5 = target->arch_info;
 141         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 142
 143         return arm7_9_clear_watchpoints(arm7_9);
 144 }
 145
 146
 147 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
 148 {
 149         armv4_5_common_t *armv4_5 = target->arch_info;
 150         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 151
 152         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 153         {
 154                 return -1;
 155         }
 156
 157         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 158         {
 159                 return -1;
 160         }
 161
 162         *armv4_5_p = armv4_5;
 163         *arm7_9_p = arm7_9;
 164
 165         return ERROR_OK;
 166 }
 167
 168 /* we set up the breakpoint even if it is already set. Some action, e.g. reset
 169  * might have erased the values in embedded ice
 170  */
 171 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 172 {
 173         armv4_5_common_t *armv4_5 = target->arch_info;
 174         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 175         int retval=ERROR_OK;
 176
 177         if (target->state != TARGET_HALTED)
 178         {
 179                 LOG_WARNING("target not halted");
 180                 return ERROR_TARGET_NOT_HALTED;
 181         }
 182
 183         if (breakpoint->type == BKPT_HARD)
 184         {
 185                 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
 186                 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 187                 if (breakpoint->set==1)
 188                 {
 189                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
 190                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 191                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
 192                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 193                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 194                 }
 195                 else if (breakpoint->set==2)
 196                 {
 197                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
 198                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 199                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
 200                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 201                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 202                 }
 203                 else
 204                 {
 205                         LOG_ERROR("BUG: no hardware comparator available");
 206                         return ERROR_OK;
 207                 }
 208
 209                 retval=jtag_execute_queue();
 210         }
 211         else if (breakpoint->type == BKPT_SOFT)
 212         {
 213                 if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
 214                         return retval;
 215
 216                 /* did we already set this breakpoint? */
 217                 if (breakpoint->set)
 218                         return ERROR_OK;
 219
 220                 if (breakpoint->length == 4)
 221                 {
 222                         u32 verify = 0xffffffff;
 223                         /* keep the original instruction in target endianness */
 224                         if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 225                         {
 226                                 return retval;
 227                         }
 228                         /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 229                         if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
 230                         {
 231                                 return retval;
 232                         }
 233
 234                         if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify)) != ERROR_OK)
 235                         {
 236                                 return retval;
 237                         }
 238                         if (verify != arm7_9->arm_bkpt)
 239                         {
 240                                 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
 241                                 return ERROR_OK;
 242                         }
 243                 }
 244                 else
 245                 {
 246                         u16 verify = 0xffff;
 247                         /* keep the original instruction in target endianness */
 248                         if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 249                         {
 250                                 return retval;
 251                         }
 252                         /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
 253                         if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
 254                         {
 255                                 return retval;
 256                         }
 257
 258                         if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify)) != ERROR_OK)
 259                         {
 260                                 return retval;
 261                         }
 262                         if (verify != arm7_9->thumb_bkpt)
 263                         {
 264                                 LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
 265                                 return ERROR_OK;
 266                         }
 267                 }
 268                 breakpoint->set = 1;
 269         }
 270
 271         return retval;
 272
 273 }
 274
 275 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 276 {
 277         int retval = ERROR_OK;
 278
 279         armv4_5_common_t *armv4_5 = target->arch_info;
 280         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 281
 282         if (!breakpoint->set)
 283         {
 284                 LOG_WARNING("breakpoint not set");
 285                 return ERROR_OK;
 286         }
 287
 288         if (breakpoint->type == BKPT_HARD)
 289         {
 290                 if (breakpoint->set == 1)
 291                 {
 292                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 293                         arm7_9->wp0_used = 0;
 294                 }
 295                 else if (breakpoint->set == 2)
 296                 {
 297                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 298                         arm7_9->wp1_used = 0;
 299                 }
 300                 retval = jtag_execute_queue();
 301                 breakpoint->set = 0;
 302         }
 303         else
 304         {
 305                 /* restore original instruction (kept in target endianness) */
 306                 if (breakpoint->length == 4)
 307                 {
 308                         u32 current_instr;
 309                         /* check that user program as not modified breakpoint instruction */
 310                         if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr)) != ERROR_OK)
 311                         {
 312                                 return retval;
 313                         }
 314                         if (current_instr==arm7_9->arm_bkpt)
 315                                 if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 316                                 {
 317                                         return retval;
 318                                 }
 319                 }
 320                 else
 321                 {
 322                         u16 current_instr;
 323                         /* check that user program as not modified breakpoint instruction */
 324                         if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr)) != ERROR_OK)
 325                         {
 326                                 return retval;
 327                         }
 328                         if (current_instr==arm7_9->thumb_bkpt)
 329                                 if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 330                                 {
 331                                         return retval;
 332                                 }
 333                 }
 334                 breakpoint->set = 0;
 335         }
 336
 337         return retval;
 338 }
 339
 340 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 341 {
 342         armv4_5_common_t *armv4_5 = target->arch_info;
 343         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 344
 345         if (target->state != TARGET_HALTED)
 346         {
 347                 LOG_WARNING("target not halted");
 348                 return ERROR_TARGET_NOT_HALTED;
 349         }
 350
 351         if (arm7_9->breakpoint_count==0)
 352         {
 353                 /* make sure we don't have any dangling breakpoints. This is vital upon
 354                  * GDB connect/disconnect
 355                  */
 356                 arm7_9_clear_watchpoints(arm7_9);
 357         }
 358
 359         if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
 360         {
 361                 LOG_INFO("no watchpoint unit available for hardware breakpoint");
 362                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 363         }
 364
 365         if ((breakpoint->length != 2) && (breakpoint->length != 4))
 366         {
 367                 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 368                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 369         }
 370
 371         if (breakpoint->type == BKPT_HARD)
 372         {
 373                 arm7_9->wp_available--;
 374
 375                 if (!arm7_9->wp0_used)
 376                 {
 377                         arm7_9->wp0_used = 1;
 378                         breakpoint->set = 1;
 379                 }
 380                 else if (!arm7_9->wp1_used)
 381                 {
 382                         arm7_9->wp1_used = 1;
 383                         breakpoint->set = 2;
 384                 }
 385                 else
 386                 {
 387                         LOG_ERROR("BUG: no hardware comparator available");
 388                 }
 389         }
 390
 391
 392         arm7_9->breakpoint_count++;
 393
 394         return arm7_9_set_breakpoint(target, breakpoint);
 395 }
 396
 397 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 398 {
 399         int retval = ERROR_OK;
 400         armv4_5_common_t *armv4_5 = target->arch_info;
 401         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 402
 403         if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
 404         {
 405                 return retval;
 406         }
 407
 408         if (breakpoint->type == BKPT_HARD)
 409                 arm7_9->wp_available++;
 410
 411         arm7_9->breakpoint_count--;
 412         if (arm7_9->breakpoint_count==0)
 413         {
 414                 /* make sure we don't have any dangling breakpoints */
 415                 if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
 416                 {
 417                         return retval;
 418                 }
 419         }
 420
 421         return ERROR_OK;
 422 }
 423
 424 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 425 {
 426         int retval = ERROR_OK;
 427         armv4_5_common_t *armv4_5 = target->arch_info;
 428         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 429         int rw_mask = 1;
 430         u32 mask;
 431
 432         mask = watchpoint->length - 1;
 433
 434         if (target->state != TARGET_HALTED)
 435         {
 436                 LOG_WARNING("target not halted");
 437                 return ERROR_TARGET_NOT_HALTED;
 438         }
 439
 440         if (watchpoint->rw == WPT_ACCESS)
 441                 rw_mask = 0;
 442         else
 443                 rw_mask = 1;
 444
 445         if (!arm7_9->wp0_used)
 446         {
 447                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
 448                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 449                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
 450                 if( watchpoint->mask != 0xffffffffu )
 451                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
 452                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 453                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 454
 455                 if((retval = jtag_execute_queue()) != ERROR_OK)
 456                 {
 457                         return retval;
 458                 }
 459                 watchpoint->set = 1;
 460                 arm7_9->wp0_used = 2;
 461         }
 462         else if (!arm7_9->wp1_used)
 463         {
 464                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
 465                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 466                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
 467                 if( watchpoint->mask != 0xffffffffu )
 468                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
 469                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 470                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 471
 472                 if((retval = jtag_execute_queue()) != ERROR_OK)
 473                 {
 474                         return retval;
 475                 }
 476                 watchpoint->set = 2;
 477                 arm7_9->wp1_used = 2;
 478         }
 479         else
 480         {
 481                 LOG_ERROR("BUG: no hardware comparator available");
 482                 return ERROR_OK;
 483         }
 484
 485         return ERROR_OK;
 486 }
 487
 488 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 489 {
 490         int retval = ERROR_OK;
 491         armv4_5_common_t *armv4_5 = target->arch_info;
 492         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 493
 494         if (target->state != TARGET_HALTED)
 495         {
 496                 LOG_WARNING("target not halted");
 497                 return ERROR_TARGET_NOT_HALTED;
 498         }
 499
 500         if (!watchpoint->set)
 501         {
 502                 LOG_WARNING("breakpoint not set");
 503                 return ERROR_OK;
 504         }
 505
 506         if (watchpoint->set == 1)
 507         {
 508                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 509                 if((retval = jtag_execute_queue()) != ERROR_OK)
 510                 {
 511                         return retval;
 512                 }
 513                 arm7_9->wp0_used = 0;
 514         }
 515         else if (watchpoint->set == 2)
 516         {
 517                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 518                 if((retval = jtag_execute_queue()) != ERROR_OK)
 519                 {
 520                         return retval;
 521                 }
 522                 arm7_9->wp1_used = 0;
 523         }
 524         watchpoint->set = 0;
 525
 526         return ERROR_OK;
 527 }
 528
 529 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 530 {
 531         armv4_5_common_t *armv4_5 = target->arch_info;
 532         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 533
 534         if (target->state != TARGET_HALTED)
 535         {
 536                 LOG_WARNING("target not halted");
 537                 return ERROR_TARGET_NOT_HALTED;
 538         }
 539
 540         if (arm7_9->wp_available < 1)
 541         {
 542                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 543         }
 544
 545         if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
 546         {
 547                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 548         }
 549
 550         arm7_9->wp_available--;
 551
 552         return ERROR_OK;
 553 }
 554
 555 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 556 {
 557         int retval = ERROR_OK;
 558         armv4_5_common_t *armv4_5 = target->arch_info;
 559         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 560
 561         if (watchpoint->set)
 562         {
 563                 if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
 564                 {
 565                         return retval;
 566                 }
 567         }
 568
 569         arm7_9->wp_available++;
 570
 571         return ERROR_OK;
 572 }
 573
 574
 575
 576
 577 int arm7_9_execute_sys_speed(struct target_s *target)
 578 {
 579         int retval;
 580
 581         armv4_5_common_t *armv4_5 = target->arch_info;
 582         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 583         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 584         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 585
 586         /* set RESTART instruction */
 587         jtag_add_end_state(TAP_RTI);
 588         if (arm7_9->need_bypass_before_restart) {
 589                 arm7_9->need_bypass_before_restart = 0;
 590                 arm_jtag_set_instr(jtag_info, 0xf, NULL);
 591         }
 592         arm_jtag_set_instr(jtag_info, 0x4, NULL);
 593
 594         long long then=timeval_ms();
 595         int timeout;
 596         while (!(timeout=((timeval_ms()-then)>1000)))
 597         {
 598                 /* read debug status register */
 599                 embeddedice_read_reg(dbg_stat);
 600                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 601                         return retval;
 602                 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 603                                    && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 604                         break;
 605                 if (debug_level>=3)
 606                 {
 607                         alive_sleep(100);
 608                 } else
 609                 {
 610                         keep_alive();
 611                 }
 612         }
 613         if (timeout)
 614         {
 615                 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 616                 return ERROR_TARGET_TIMEOUT;
 617         }
 618
 619         return ERROR_OK;
 620 }
 621
 622 int arm7_9_execute_fast_sys_speed(struct target_s *target)
 623 {
 624         static int set=0;
 625         static u8 check_value[4], check_mask[4];
 626
 627         armv4_5_common_t *armv4_5 = target->arch_info;
 628         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 629         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 630         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 631
 632         /* set RESTART instruction */
 633         jtag_add_end_state(TAP_RTI);
 634         if (arm7_9->need_bypass_before_restart) {
 635                 arm7_9->need_bypass_before_restart = 0;
 636                 arm_jtag_set_instr(jtag_info, 0xf, NULL);
 637         }
 638         arm_jtag_set_instr(jtag_info, 0x4, NULL);
 639
 640         if (!set)
 641         {
 642                 /* check for DBGACK and SYSCOMP set (others don't care) */
 643
 644                 /* NB! These are constants that must be available until after next jtag_execute() and
 645                    we evaluate the values upon first execution in lieu of setting up these constants
 646                    during early setup.
 647                 */
 648                 buf_set_u32(check_value, 0, 32, 0x9);
 649                 buf_set_u32(check_mask, 0, 32, 0x9);
 650                 set=1;
 651         }
 652
 653         /* read debug status register */
 654         embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
 655
 656         return ERROR_OK;
 657 }
 658
 659 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
 660 {
 661         armv4_5_common_t *armv4_5 = target->arch_info;
 662         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 663         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 664         u32 *data;
 665         int i, retval = ERROR_OK;
 666
 667         data = malloc(size * (sizeof(u32)));
 668
 669         retval = embeddedice_receive(jtag_info, data, size);
 670
 671         for (i = 0; i < size; i++)
 672         {
 673                 h_u32_to_le(buffer + (i * 4), data[i]);
 674         }
 675
 676         free(data);
 677
 678         return retval;
 679 }
 680
 681 int arm7_9_handle_target_request(void *priv)
 682 {
 683         int retval = ERROR_OK;
 684         target_t *target = priv;
 685         if (!target->type->examined)
 686                 return ERROR_OK;
 687         armv4_5_common_t *armv4_5 = target->arch_info;
 688         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 689         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 690         reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
 691
 692
 693         if (!target->dbg_msg_enabled)
 694                 return ERROR_OK;
 695
 696         if (target->state == TARGET_RUNNING)
 697         {
 698                 /* read DCC control register */
 699                 embeddedice_read_reg(dcc_control);
 700                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 701                 {
 702                         return retval;
 703                 }
 704
 705                 /* check W bit */
 706                 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
 707                 {
 708                         u32 request;
 709
 710                         if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
 711                         {
 712                                 return retval;
 713                         }
 714                         if ((retval = target_request(target, request)) != ERROR_OK)
 715                         {
 716                                 return retval;
 717                         }
 718                 }
 719         }
 720
 721         return ERROR_OK;
 722 }
 723
 724 int arm7_9_poll(target_t *target)
 725 {
 726         int retval;
 727         armv4_5_common_t *armv4_5 = target->arch_info;
 728         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 729         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 730
 731         /* read debug status register */
 732         embeddedice_read_reg(dbg_stat);
 733         if ((retval = jtag_execute_queue()) != ERROR_OK)
 734         {
 735                 return retval;
 736         }
 737
 738         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 739         {
 740 /*              LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
 741                 if (target->state == TARGET_UNKNOWN)
 742                 {
 743                         target->state = TARGET_RUNNING;
 744                         LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
 745                 }
 746                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 747                 {
 748                         int check_pc=0;
 749                         if (target->state == TARGET_RESET)
 750                         {
 751                                 if (target->reset_halt)
 752                                 {
 753                                         if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
 754                                         {
 755                                                 check_pc = 1;
 756                                         }
 757                                 }
 758                         }
 759
 760                         target->state = TARGET_HALTED;
 761
 762                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 763                                 return retval;
 764
 765                         if (check_pc)
 766                         {
 767                                 reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
 768                                 u32 t=*((u32 *)reg->value);
 769                                 if (t!=0)
 770                                 {
 771                                         LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
 772                                 }
 773                         }
 774
 775                         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 776                         {
 777                                 return retval;
 778                         }
 779                 }
 780                 if (target->state == TARGET_DEBUG_RUNNING)
 781                 {
 782                         target->state = TARGET_HALTED;
 783                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 784                                 return retval;
 785
 786                         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
 787                         {
 788                                 return retval;
 789                         }
 790                 }
 791                 if (target->state != TARGET_HALTED)
 792                 {
 793                         LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
 794                 }
 795         }
 796         else
 797         {
 798                 if (target->state != TARGET_DEBUG_RUNNING)
 799                         target->state = TARGET_RUNNING;
 800         }
 801
 802         return ERROR_OK;
 803 }
 804
 805 /*
 806   Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
 807   in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
 808   while the core is held in reset(SRST). It isn't possible to program the halt
 809   condition once reset was asserted, hence a hook that allows the target to set
 810   up its reset-halt condition prior to asserting reset.
 811 */
 812
 813 int arm7_9_assert_reset(target_t *target)
 814 {
 815         armv4_5_common_t *armv4_5 = target->arch_info;
 816         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 817         LOG_DEBUG("target->state: %s",
 818                   Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
 819
 820         if (!(jtag_reset_config & RESET_HAS_SRST))
 821         {
 822                 LOG_ERROR("Can't assert SRST");
 823                 return ERROR_FAIL;
 824         }
 825
 826         if (target->reset_halt)
 827         {
 828                 /*
 829                  * Some targets do not support communication while SRST is asserted. We need to
 830                  * set up the reset vector catch here.
 831                  *
 832                  * If TRST is asserted, then these settings will be reset anyway, so setting them
 833                  * here is harmless.
 834                  */
 835                 if (arm7_9->has_vector_catch)
 836                 {
 837                         /* program vector catch register to catch reset vector */
 838                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
 839                 }
 840                 else
 841                 {
 842                         /* program watchpoint unit to match on reset vector address */
 843                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
 844                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
 845                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
 846                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 847                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 848                 }
 849         }
 850
 851         /* here we should issue a srst only, but we may have to assert trst as well */
 852         if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 853         {
 854                 jtag_add_reset(1, 1);
 855         } else
 856         {
 857                 jtag_add_reset(0, 1);
 858         }
 859
 860
 861         target->state = TARGET_RESET;
 862         jtag_add_sleep(50000);
 863
 864         armv4_5_invalidate_core_regs(target);
 865
 866     if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
 867         {
 868                 /* debug entry was already prepared in arm7_9_assert_reset() */
 869                 target->debug_reason = DBG_REASON_DBGRQ;
 870         }
 871
 872         return ERROR_OK;
 873
 874 }
 875
 876 int arm7_9_deassert_reset(target_t *target)
 877 {
 878         int retval=ERROR_OK;
 879         LOG_DEBUG("target->state: %s",
 880                   Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
 881
 882
 883         /* deassert reset lines */
 884         jtag_add_reset(0, 0);
 885
 886         if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
 887         {
 888                 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
 889                 /* set up embedded ice registers again */
 890                 if ((retval=target->type->examine(target))!=ERROR_OK)
 891                         return retval;
 892
 893                 if ((retval=target_poll(target))!=ERROR_OK)
 894                 {
 895                         return retval;
 896                 }
 897
 898                 if ((retval=target_halt(target))!=ERROR_OK)
 899                 {
 900                         return retval;
 901                 }
 902
 903         }
 904         return retval;
 905 }
 906
 907 int arm7_9_clear_halt(target_t *target)
 908 {
 909         armv4_5_common_t *armv4_5 = target->arch_info;
 910         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 911         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 912
 913         /* we used DBGRQ only if we didn't come out of reset */
 914         if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
 915         {
 916                 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
 917                  */
 918                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 919                 embeddedice_store_reg(dbg_ctrl);
 920         }
 921         else
 922         {
 923                 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
 924                 {
 925                         /* if we came out of reset, and vector catch is supported, we used
 926                          * vector catch to enter debug state
 927                          * restore the register in that case
 928                          */
 929                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
 930                 }
 931                 else
 932                 {
 933                         /* restore registers if watchpoint unit 0 was in use
 934                          */
 935                         if (arm7_9->wp0_used)
 936                         {
 937                                 if (arm7_9->debug_entry_from_reset)
 938                                 {
 939                                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
 940                                 }
 941                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
 942                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
 943                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
 944                         }
 945                         /* control value always has to be restored, as it was either disabled,
 946                          * or enabled with possibly different bits
 947                          */
 948                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 949                 }
 950         }
 951
 952         return ERROR_OK;
 953 }
 954
 955 int arm7_9_soft_reset_halt(struct target_s *target)
 956 {
 957         armv4_5_common_t *armv4_5 = target->arch_info;
 958         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 959         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 960         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 961         int i;
 962         int retval;
 963
 964         if ((retval=target_halt(target))!=ERROR_OK)
 965                 return retval;
 966
 967         long long then=timeval_ms();
 968         int timeout;
 969         while (!(timeout=((timeval_ms()-then)>1000)))
 970         {
 971                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
 972                         break;
 973                 embeddedice_read_reg(dbg_stat);
 974                 if ((retval=jtag_execute_queue())!=ERROR_OK)
 975                         return retval;
 976                 if (debug_level>=3)
 977                 {
 978                         alive_sleep(100);
 979                 } else
 980                 {
 981                         keep_alive();
 982                 }
 983         }
 984         if (timeout)
 985         {
 986                 LOG_ERROR("Failed to halt CPU after 1 sec");
 987                 return ERROR_TARGET_TIMEOUT;
 988         }
 989         target->state = TARGET_HALTED;
 990
 991         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 992          * ensure that DBGRQ is cleared
 993          */
 994         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 995         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 996         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 997         embeddedice_store_reg(dbg_ctrl);
 998
 999         if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1000         {
1001                 return retval;
1002         }
1003
1004         /* if the target is in Thumb state, change to ARM state */
1005         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1006         {
1007                 u32 r0_thumb, pc_thumb;
1008                 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1009                 /* Entered debug from Thumb mode */
1010                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1011                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1012         }
1013
1014         /* all register content is now invalid */
1015         if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
1016         {
1017                 return retval;
1018         }
1019
1020         /* SVC, ARM state, IRQ and FIQ disabled */
1021         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
1022         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
1023         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1024
1025         /* start fetching from 0x0 */
1026         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
1027         armv4_5->core_cache->reg_list[15].dirty = 1;
1028         armv4_5->core_cache->reg_list[15].valid = 1;
1029
1030         armv4_5->core_mode = ARMV4_5_MODE_SVC;
1031         armv4_5->core_state = ARMV4_5_STATE_ARM;
1032
1033         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1034                 return ERROR_FAIL;
1035
1036         /* reset registers */
1037         for (i = 0; i <= 14; i++)
1038         {
1039                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
1040                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1041                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1042         }
1043
1044         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1045         {
1046                 return retval;
1047         }
1048
1049         return ERROR_OK;
1050 }
1051
1052 int arm7_9_halt(target_t *target)
1053 {
1054         if (target->state==TARGET_RESET)
1055         {
1056                 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1057                 return ERROR_OK;
1058         }
1059
1060         armv4_5_common_t *armv4_5 = target->arch_info;
1061         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1062         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1063
1064         LOG_DEBUG("target->state: %s",
1065                   Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
1066
1067         if (target->state == TARGET_HALTED)
1068         {
1069                 LOG_DEBUG("target was already halted");
1070                 return ERROR_OK;
1071         }
1072
1073         if (target->state == TARGET_UNKNOWN)
1074         {
1075                 LOG_WARNING("target was in unknown state when halt was requested");
1076         }
1077
1078         if (arm7_9->use_dbgrq)
1079         {
1080                 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1081                  */
1082                 if (arm7_9->set_special_dbgrq) {
1083                         arm7_9->set_special_dbgrq(target);
1084                 } else {
1085                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1086                         embeddedice_store_reg(dbg_ctrl);
1087                 }
1088         }
1089         else
1090         {
1091                 /* program watchpoint unit to match on any address
1092                  */
1093                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1094                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1095                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1096                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1097         }
1098
1099         target->debug_reason = DBG_REASON_DBGRQ;
1100
1101         return ERROR_OK;
1102 }
1103
1104 int arm7_9_debug_entry(target_t *target)
1105 {
1106         int i;
1107         u32 context[16];
1108         u32* context_p[16];
1109         u32 r0_thumb, pc_thumb;
1110         u32 cpsr;
1111         int retval;
1112         /* get pointers to arch-specific information */
1113         armv4_5_common_t *armv4_5 = target->arch_info;
1114         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1115         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1116         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1117
1118 #ifdef _DEBUG_ARM7_9_
1119         LOG_DEBUG("-");
1120 #endif
1121
1122         if (arm7_9->pre_debug_entry)
1123                 arm7_9->pre_debug_entry(target);
1124
1125         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1126          * ensure that DBGRQ is cleared
1127          */
1128         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1129         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1130         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1131         embeddedice_store_reg(dbg_ctrl);
1132
1133         if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1134         {
1135                 return retval;
1136         }
1137
1138         if ((retval = jtag_execute_queue()) != ERROR_OK)
1139         {
1140                 return retval;
1141         }
1142
1143         if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1144                 return retval;
1145
1146
1147         if (target->state != TARGET_HALTED)
1148         {
1149                 LOG_WARNING("target not halted");
1150                 return ERROR_TARGET_NOT_HALTED;
1151         }
1152
1153         /* if the target is in Thumb state, change to ARM state */
1154         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1155         {
1156                 LOG_DEBUG("target entered debug from Thumb state");
1157                 /* Entered debug from Thumb mode */
1158                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1159                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1160                 LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1161         }
1162         else
1163         {
1164                 LOG_DEBUG("target entered debug from ARM state");
1165                 /* Entered debug from ARM mode */
1166                 armv4_5->core_state = ARMV4_5_STATE_ARM;
1167         }
1168
1169         for (i = 0; i < 16; i++)
1170                 context_p[i] = &context[i];
1171         /* save core registers (r0 - r15 of current core mode) */
1172         arm7_9->read_core_regs(target, 0xffff, context_p);
1173
1174         arm7_9->read_xpsr(target, &cpsr, 0);
1175
1176         if ((retval = jtag_execute_queue()) != ERROR_OK)
1177                 return retval;
1178
1179         /* if the core has been executing in Thumb state, set the T bit */
1180         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1181                 cpsr |= 0x20;
1182
1183         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1184         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1185         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1186
1187         armv4_5->core_mode = cpsr & 0x1f;
1188
1189         if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1190         {
1191                 target->state = TARGET_UNKNOWN;
1192                 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1193                 return ERROR_TARGET_FAILURE;
1194         }
1195
1196         LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1197
1198         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1199         {
1200                 LOG_DEBUG("thumb state, applying fixups");
1201                 context[0] = r0_thumb;
1202                 context[15] = pc_thumb;
1203         } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1204         {
1205                 /* adjust value stored by STM */
1206                 context[15] -= 3 * 4;
1207         }
1208
1209         if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1210                         || (target->debug_reason == DBG_REASON_SINGLESTEP)
1211                         || (target->debug_reason == DBG_REASON_WATCHPOINT)
1212                         || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1213                         || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1214                 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1215         else if (target->debug_reason == DBG_REASON_DBGRQ)
1216                 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1217         else
1218         {
1219                 LOG_ERROR("unknown debug reason: %i", target->debug_reason);
1220         }
1221
1222         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1223                 return ERROR_FAIL;
1224
1225         for (i=0; i<=15; i++)
1226         {
1227                 LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
1228                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1229                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1230                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1231         }
1232
1233         LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
1234
1235         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1236                 return ERROR_FAIL;
1237
1238         /* exceptions other than USR & SYS have a saved program status register */
1239         if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1240         {
1241                 u32 spsr;
1242                 arm7_9->read_xpsr(target, &spsr, 1);
1243                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1244                 {
1245                         return retval;
1246                 }
1247                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1248                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1249                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1250         }
1251
1252         /* r0 and r15 (pc) have to be restored later */
1253         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1254         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1255
1256         if ((retval = jtag_execute_queue()) != ERROR_OK)
1257                 return retval;
1258
1259         if (arm7_9->post_debug_entry)
1260                 arm7_9->post_debug_entry(target);
1261
1262         return ERROR_OK;
1263 }
1264
1265 int arm7_9_full_context(target_t *target)
1266 {
1267         int i;
1268         int retval;
1269         armv4_5_common_t *armv4_5 = target->arch_info;
1270         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1271
1272         LOG_DEBUG("-");
1273
1274         if (target->state != TARGET_HALTED)
1275         {
1276                 LOG_WARNING("target not halted");
1277                 return ERROR_TARGET_NOT_HALTED;
1278         }
1279
1280         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1281                 return ERROR_FAIL;
1282
1283         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1284          * SYS shares registers with User, so we don't touch SYS
1285          */
1286         for(i = 0; i < 6; i++)
1287         {
1288                 u32 mask = 0;
1289                 u32* reg_p[16];
1290                 int j;
1291                 int valid = 1;
1292
1293                 /* check if there are invalid registers in the current mode
1294                  */
1295                 for (j = 0; j <= 16; j++)
1296                 {
1297                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1298                                 valid = 0;
1299                 }
1300
1301                 if (!valid)
1302                 {
1303                         u32 tmp_cpsr;
1304
1305                         /* change processor mode (and mask T bit) */
1306                         tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1307                         tmp_cpsr |= armv4_5_number_to_mode(i);
1308                         tmp_cpsr &= ~0x20;
1309                         arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1310
1311                         for (j = 0; j < 15; j++)
1312                         {
1313                                 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1314                                 {
1315                                         reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1316                                         mask |= 1 << j;
1317                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1318                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1319                                 }
1320                         }
1321
1322                         /* if only the PSR is invalid, mask is all zeroes */
1323                         if (mask)
1324                                 arm7_9->read_core_regs(target, mask, reg_p);
1325
1326                         /* check if the PSR has to be read */
1327                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1328                         {
1329                                 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1330                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1331                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1332                         }
1333                 }
1334         }
1335
1336         /* restore processor mode (mask T bit) */
1337         arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1338
1339         if ((retval = jtag_execute_queue()) != ERROR_OK)
1340         {
1341                 return retval;
1342         }
1343         return ERROR_OK;
1344 }
1345
1346 int arm7_9_restore_context(target_t *target)
1347 {
1348         armv4_5_common_t *armv4_5 = target->arch_info;
1349         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1350         reg_t *reg;
1351         armv4_5_core_reg_t *reg_arch_info;
1352         enum armv4_5_mode current_mode = armv4_5->core_mode;
1353         int i, j;
1354         int dirty;
1355         int mode_change;
1356
1357         LOG_DEBUG("-");
1358
1359         if (target->state != TARGET_HALTED)
1360         {
1361                 LOG_WARNING("target not halted");
1362                 return ERROR_TARGET_NOT_HALTED;
1363         }
1364
1365         if (arm7_9->pre_restore_context)
1366                 arm7_9->pre_restore_context(target);
1367
1368         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1369                 return ERROR_FAIL;
1370
1371         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1372          * SYS shares registers with User, so we don't touch SYS
1373          */
1374         for (i = 0; i < 6; i++)
1375         {
1376                 LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1377                 dirty = 0;
1378                 mode_change = 0;
1379                 /* check if there are dirty registers in the current mode
1380                 */
1381                 for (j = 0; j <= 16; j++)
1382                 {
1383                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1384                         reg_arch_info = reg->arch_info;
1385                         if (reg->dirty == 1)
1386                         {
1387                                 if (reg->valid == 1)
1388                                 {
1389                                         dirty = 1;
1390                                         LOG_DEBUG("examining dirty reg: %s", reg->name);
1391                                         if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1392                                                 && (reg_arch_info->mode != current_mode)
1393                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1394                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1395                                         {
1396                                                 mode_change = 1;
1397                                                 LOG_DEBUG("require mode change");
1398                                         }
1399                                 }
1400                                 else
1401                                 {
1402                                         LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1403                                 }
1404                         }
1405                 }
1406
1407                 if (dirty)
1408                 {
1409                         u32 mask = 0x0;
1410                         int num_regs = 0;
1411                         u32 regs[16];
1412
1413                         if (mode_change)
1414                         {
1415                                 u32 tmp_cpsr;
1416
1417                                 /* change processor mode (mask T bit) */
1418                                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1419                                 tmp_cpsr |= armv4_5_number_to_mode(i);
1420                                 tmp_cpsr &= ~0x20;
1421                                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1422                                 current_mode = armv4_5_number_to_mode(i);
1423                         }
1424
1425                         for (j = 0; j <= 14; j++)
1426                         {
1427                                 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1428                                 reg_arch_info = reg->arch_info;
1429
1430
1431                                 if (reg->dirty == 1)
1432                                 {
1433                                         regs[j] = buf_get_u32(reg->value, 0, 32);
1434                                         mask |= 1 << j;
1435                                         num_regs++;
1436                                         reg->dirty = 0;
1437                                         reg->valid = 1;
1438                                         LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1439                                 }
1440                         }
1441
1442                         if (mask)
1443                         {
1444                                 arm7_9->write_core_regs(target, mask, regs);
1445                         }
1446
1447                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1448                         reg_arch_info = reg->arch_info;
1449                         if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1450                         {
1451                                 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1452                                 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1453                         }
1454                 }
1455         }
1456
1457         if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1458         {
1459                 /* restore processor mode (mask T bit) */
1460                 u32 tmp_cpsr;
1461
1462                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1463                 tmp_cpsr |= armv4_5_number_to_mode(i);
1464                 tmp_cpsr &= ~0x20;
1465                 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1466                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1467         }
1468         else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1469         {
1470                 /* CPSR has been changed, full restore necessary (mask T bit) */
1471                 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1472                 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1473                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1474                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1475         }
1476
1477         /* restore PC */
1478         LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1479         arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1480         armv4_5->core_cache->reg_list[15].dirty = 0;
1481
1482         if (arm7_9->post_restore_context)
1483                 arm7_9->post_restore_context(target);
1484
1485         return ERROR_OK;
1486 }
1487
1488 int arm7_9_restart_core(struct target_s *target)
1489 {
1490         armv4_5_common_t *armv4_5 = target->arch_info;
1491         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1492         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1493
1494         /* set RESTART instruction */
1495         jtag_add_end_state(TAP_RTI);
1496         if (arm7_9->need_bypass_before_restart) {
1497                 arm7_9->need_bypass_before_restart = 0;
1498                 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1499         }
1500         arm_jtag_set_instr(jtag_info, 0x4, NULL);
1501
1502         jtag_add_runtest(1, TAP_RTI);
1503         return jtag_execute_queue();
1504 }
1505
1506 void arm7_9_enable_watchpoints(struct target_s *target)
1507 {
1508         watchpoint_t *watchpoint = target->watchpoints;
1509
1510         while (watchpoint)
1511         {
1512                 if (watchpoint->set == 0)
1513                         arm7_9_set_watchpoint(target, watchpoint);
1514                 watchpoint = watchpoint->next;
1515         }
1516 }
1517
1518 void arm7_9_enable_breakpoints(struct target_s *target)
1519 {
1520         breakpoint_t *breakpoint = target->breakpoints;
1521
1522         /* set any pending breakpoints */
1523         while (breakpoint)
1524         {
1525                 arm7_9_set_breakpoint(target, breakpoint);
1526                 breakpoint = breakpoint->next;
1527         }
1528 }
1529
1530
1531 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1532 {
1533         armv4_5_common_t *armv4_5 = target->arch_info;
1534         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1535         breakpoint_t *breakpoint = target->breakpoints;
1536         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1537         int err, retval = ERROR_OK;
1538
1539         LOG_DEBUG("-");
1540
1541         if (target->state != TARGET_HALTED)
1542         {
1543                 LOG_WARNING("target not halted");
1544                 return ERROR_TARGET_NOT_HALTED;
1545         }
1546
1547         if (!debug_execution)
1548         {
1549                 target_free_all_working_areas(target);
1550         }
1551
1552         /* current = 1: continue on current pc, otherwise continue at <address> */
1553         if (!current)
1554                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1555
1556         /* the front-end may request us not to handle breakpoints */
1557         if (handle_breakpoints)
1558         {
1559                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1560                 {
1561                         LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1562                         if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1563                         {
1564                                 return retval;
1565                         }
1566
1567                         LOG_DEBUG("enable single-step");
1568                         arm7_9->enable_single_step(target);
1569
1570                         target->debug_reason = DBG_REASON_SINGLESTEP;
1571
1572                         if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1573                         {
1574                                 return retval;
1575                         }
1576
1577                         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1578                                 arm7_9->branch_resume(target);
1579                         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1580                         {
1581                                 arm7_9->branch_resume_thumb(target);
1582                         }
1583                         else
1584                         {
1585                                 LOG_ERROR("unhandled core state");
1586                                 return ERROR_FAIL;
1587                         }
1588
1589                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1590                         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1591                         err = arm7_9_execute_sys_speed(target);
1592
1593                         LOG_DEBUG("disable single-step");
1594                         arm7_9->disable_single_step(target);
1595
1596                         if (err != ERROR_OK)
1597                         {
1598                                 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1599                                 {
1600                                         return retval;
1601                                 }
1602                                 target->state = TARGET_UNKNOWN;
1603                                 return err;
1604                         }
1605
1606                         arm7_9_debug_entry(target);
1607                         LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1608
1609                         LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1610                         if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1611                         {
1612                                 return retval;
1613                         }
1614                 }
1615         }
1616
1617         /* enable any pending breakpoints and watchpoints */
1618         arm7_9_enable_breakpoints(target);
1619         arm7_9_enable_watchpoints(target);
1620
1621         if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1622         {
1623                 return retval;
1624         }
1625
1626         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1627         {
1628                 arm7_9->branch_resume(target);
1629         }
1630         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1631         {
1632                 arm7_9->branch_resume_thumb(target);
1633         }
1634         else
1635         {
1636                 LOG_ERROR("unhandled core state");
1637                 return ERROR_FAIL;
1638         }
1639
1640         /* deassert DBGACK and INTDIS */
1641         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1642         /* INTDIS only when we really resume, not during debug execution */
1643         if (!debug_execution)
1644                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1645         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1646
1647         if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1648         {
1649                 return retval;
1650         }
1651
1652         target->debug_reason = DBG_REASON_NOTHALTED;
1653
1654         if (!debug_execution)
1655         {
1656                 /* registers are now invalid */
1657                 armv4_5_invalidate_core_regs(target);
1658                 target->state = TARGET_RUNNING;
1659                 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1660                 {
1661                         return retval;
1662                 }
1663         }
1664         else
1665         {
1666                 target->state = TARGET_DEBUG_RUNNING;
1667                 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1668                 {
1669                         return retval;
1670                 }
1671         }
1672
1673         LOG_DEBUG("target resumed");
1674
1675         return ERROR_OK;
1676 }
1677
1678 void arm7_9_enable_eice_step(target_t *target)
1679 {
1680         armv4_5_common_t *armv4_5 = target->arch_info;
1681         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1682         int retval;
1683
1684         u32 current_pc;
1685         current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1686
1687         u32 next_pc;
1688         if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1689         {
1690                 u32 current_opcode;
1691                 target_read_u32(target, current_pc, &current_opcode);
1692                 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1693                 return retval;
1694         }
1695
1696         if(next_pc != current_pc)
1697         {
1698                 /* setup an inverse breakpoint on the current PC
1699                 * - comparator 1 matches the current address
1700                 * - rangeout from comparator 1 is connected to comparator 0 rangein
1701                 * - comparator 0 matches any address, as long as rangein is low */
1702                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1703                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1704                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1705                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
1706                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
1707                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1708                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1709                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1710                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1711         }
1712         else
1713         {
1714                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1715                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1716                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
1717                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
1718                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
1719                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1720                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1721                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1722                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1723         }
1724 }
1725
1726 void arm7_9_disable_eice_step(target_t *target)
1727 {
1728         armv4_5_common_t *armv4_5 = target->arch_info;
1729         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1730
1731         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1732         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1733         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1734         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1735         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1736         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1737         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1738         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1739         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1740 }
1741
1742 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1743 {
1744         armv4_5_common_t *armv4_5 = target->arch_info;
1745         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1746         breakpoint_t *breakpoint = NULL;
1747         int err, retval;
1748
1749         if (target->state != TARGET_HALTED)
1750         {
1751                 LOG_WARNING("target not halted");
1752                 return ERROR_TARGET_NOT_HALTED;
1753         }
1754
1755         /* current = 1: continue on current pc, otherwise continue at <address> */
1756         if (!current)
1757                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1758
1759         /* the front-end may request us not to handle breakpoints */
1760         if (handle_breakpoints)
1761                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1762                         if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1763                         {
1764                                 return retval;
1765                         }
1766
1767         target->debug_reason = DBG_REASON_SINGLESTEP;
1768
1769         if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1770         {
1771                 return retval;
1772         }
1773
1774         arm7_9->enable_single_step(target);
1775
1776         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1777         {
1778                 arm7_9->branch_resume(target);
1779         }
1780         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1781         {
1782                 arm7_9->branch_resume_thumb(target);
1783         }
1784         else
1785         {
1786                 LOG_ERROR("unhandled core state");
1787                 return ERROR_FAIL;
1788         }
1789
1790         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1791         {
1792                 return retval;
1793         }
1794
1795         err = arm7_9_execute_sys_speed(target);
1796         arm7_9->disable_single_step(target);
1797
1798         /* registers are now invalid */
1799         armv4_5_invalidate_core_regs(target);
1800
1801         if (err != ERROR_OK)
1802         {
1803                 target->state = TARGET_UNKNOWN;
1804         } else {
1805                 arm7_9_debug_entry(target);
1806                 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1807                 {
1808                         return retval;
1809                 }
1810                 LOG_DEBUG("target stepped");
1811         }
1812
1813         if (breakpoint)
1814                 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1815                 {
1816                         return retval;
1817                 }
1818
1819         return err;
1820
1821 }
1822
1823 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1824 {
1825         u32* reg_p[16];
1826         u32 value;
1827         int retval;
1828         armv4_5_common_t *armv4_5 = target->arch_info;
1829         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1830
1831         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1832                 return ERROR_FAIL;
1833
1834         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1835
1836         if ((num < 0) || (num > 16))
1837                 return ERROR_INVALID_ARGUMENTS;
1838
1839         if ((mode != ARMV4_5_MODE_ANY)
1840                         && (mode != armv4_5->core_mode)
1841                         && (reg_mode != ARMV4_5_MODE_ANY))
1842         {
1843                 u32 tmp_cpsr;
1844
1845                 /* change processor mode (mask T bit) */
1846                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1847                 tmp_cpsr |= mode;
1848                 tmp_cpsr &= ~0x20;
1849                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1850         }
1851
1852         if ((num >= 0) && (num <= 15))
1853         {
1854                 /* read a normal core register */
1855                 reg_p[num] = &value;
1856
1857                 arm7_9->read_core_regs(target, 1 << num, reg_p);
1858         }
1859         else
1860         {
1861                 /* read a program status register
1862                  * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1863                  */
1864                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1865                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1866
1867                 arm7_9->read_xpsr(target, &value, spsr);
1868         }
1869
1870         if ((retval = jtag_execute_queue()) != ERROR_OK)
1871         {
1872                 return retval;
1873         }
1874
1875         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1876         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1877         buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1878
1879         if ((mode != ARMV4_5_MODE_ANY)
1880                         && (mode != armv4_5->core_mode)
1881                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1882                 /* restore processor mode (mask T bit) */
1883                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1884         }
1885
1886         return ERROR_OK;
1887
1888 }
1889
1890 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1891 {
1892         u32 reg[16];
1893         armv4_5_common_t *armv4_5 = target->arch_info;
1894         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1895
1896         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1897                 return ERROR_FAIL;
1898
1899         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1900
1901         if ((num < 0) || (num > 16))
1902                 return ERROR_INVALID_ARGUMENTS;
1903
1904         if ((mode != ARMV4_5_MODE_ANY)
1905                         && (mode != armv4_5->core_mode)
1906                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1907                 u32 tmp_cpsr;
1908
1909                 /* change processor mode (mask T bit) */
1910                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1911                 tmp_cpsr |= mode;
1912                 tmp_cpsr &= ~0x20;
1913                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1914         }
1915
1916         if ((num >= 0) && (num <= 15))
1917         {
1918                 /* write a normal core register */
1919                 reg[num] = value;
1920
1921                 arm7_9->write_core_regs(target, 1 << num, reg);
1922         }
1923         else
1924         {
1925                 /* write a program status register
1926                 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1927                 */
1928                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1929                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1930
1931                 /* if we're writing the CPSR, mask the T bit */
1932                 if (!spsr)
1933                         value &= ~0x20;
1934
1935                 arm7_9->write_xpsr(target, value, spsr);
1936         }
1937
1938         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1939         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1940
1941         if ((mode != ARMV4_5_MODE_ANY)
1942                         && (mode != armv4_5->core_mode)
1943                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1944                 /* restore processor mode (mask T bit) */
1945                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1946         }
1947
1948         return jtag_execute_queue();
1949 }
1950
1951 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1952 {
1953         armv4_5_common_t *armv4_5 = target->arch_info;
1954         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1955
1956         u32 reg[16];
1957         int num_accesses = 0;
1958         int thisrun_accesses;
1959         int i;
1960         u32 cpsr;
1961         int retval;
1962         int last_reg = 0;
1963
1964         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1965
1966         if (target->state != TARGET_HALTED)
1967         {
1968                 LOG_WARNING("target not halted");
1969                 return ERROR_TARGET_NOT_HALTED;
1970         }
1971
1972         /* sanitize arguments */
1973         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1974                 return ERROR_INVALID_ARGUMENTS;
1975
1976         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1977                 return ERROR_TARGET_UNALIGNED_ACCESS;
1978
1979         /* load the base register with the address of the first word */
1980         reg[0] = address;
1981         arm7_9->write_core_regs(target, 0x1, reg);
1982
1983         int j=0;
1984
1985         switch (size)
1986         {
1987                 case 4:
1988                         while (num_accesses < count)
1989                         {
1990                                 u32 reg_list;
1991                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1992                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1993
1994                                 if (last_reg <= thisrun_accesses)
1995                                         last_reg = thisrun_accesses;
1996
1997                                 arm7_9->load_word_regs(target, reg_list);
1998
1999                                 /* fast memory reads are only safe when the target is running
2000                                  * from a sufficiently high clock (32 kHz is usually too slow)
2001                                  */
2002                                 if (arm7_9->fast_memory_access)
2003                                         arm7_9_execute_fast_sys_speed(target);
2004                                 else
2005                                         arm7_9_execute_sys_speed(target);
2006
2007                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2008
2009                                 /* advance buffer, count number of accesses */
2010                                 buffer += thisrun_accesses * 4;
2011                                 num_accesses += thisrun_accesses;
2012
2013                                 if ((j++%1024)==0)
2014                                 {
2015                                         keep_alive();
2016                                 }
2017                         }
2018                         break;
2019                 case 2:
2020                         while (num_accesses < count)
2021                         {
2022                                 u32 reg_list;
2023                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2024                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2025
2026                                 for (i = 1; i <= thisrun_accesses; i++)
2027                                 {
2028                                         if (i > last_reg)
2029                                                 last_reg = i;
2030                                         arm7_9->load_hword_reg(target, i);
2031                                         /* fast memory reads are only safe when the target is running
2032                                          * from a sufficiently high clock (32 kHz is usually too slow)
2033                                          */
2034                                         if (arm7_9->fast_memory_access)
2035                                                 retval = arm7_9_execute_fast_sys_speed(target);
2036                                         else
2037                                                 retval = arm7_9_execute_sys_speed(target);
2038                                         if(retval != ERROR_OK)
2039                                         {
2040                                                 return retval;
2041                                         }
2042
2043                                 }
2044
2045                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2046
2047                                 /* advance buffer, count number of accesses */
2048                                 buffer += thisrun_accesses * 2;
2049                                 num_accesses += thisrun_accesses;
2050
2051                                 if ((j++%1024)==0)
2052                                 {
2053                                         keep_alive();
2054                                 }
2055                         }
2056                         break;
2057                 case 1:
2058                         while (num_accesses < count)
2059                         {
2060                                 u32 reg_list;
2061                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2062                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2063
2064                                 for (i = 1; i <= thisrun_accesses; i++)
2065                                 {
2066                                         if (i > last_reg)
2067                                                 last_reg = i;
2068                                         arm7_9->load_byte_reg(target, i);
2069                                         /* fast memory reads are only safe when the target is running
2070                                          * from a sufficiently high clock (32 kHz is usually too slow)
2071                                          */
2072                                         if (arm7_9->fast_memory_access)
2073                                                 retval = arm7_9_execute_fast_sys_speed(target);
2074                                         else
2075                                                 retval = arm7_9_execute_sys_speed(target);
2076                                         if(retval != ERROR_OK)
2077                                         {
2078                                                 return retval;
2079                                         }
2080                                 }
2081
2082                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2083
2084                                 /* advance buffer, count number of accesses */
2085                                 buffer += thisrun_accesses * 1;
2086                                 num_accesses += thisrun_accesses;
2087
2088                                 if ((j++%1024)==0)
2089                                 {
2090                                         keep_alive();
2091                                 }
2092                         }
2093                         break;
2094                 default:
2095                         LOG_ERROR("BUG: we shouldn't get here");
2096                         exit(-1);
2097                         break;
2098         }
2099
2100         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2101                 return ERROR_FAIL;
2102
2103         for (i=0; i<=last_reg; i++)
2104                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2105
2106         arm7_9->read_xpsr(target, &cpsr, 0);
2107         if ((retval = jtag_execute_queue()) != ERROR_OK)
2108         {
2109                 LOG_ERROR("JTAG error while reading cpsr");
2110                 return ERROR_TARGET_DATA_ABORT;
2111         }
2112
2113         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2114         {
2115                 LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2116
2117                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2118
2119                 return ERROR_TARGET_DATA_ABORT;
2120         }
2121
2122         return ERROR_OK;
2123 }
2124
2125 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
2126 {
2127         armv4_5_common_t *armv4_5 = target->arch_info;
2128         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2129         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2130
2131         u32 reg[16];
2132         int num_accesses = 0;
2133         int thisrun_accesses;
2134         int i;
2135         u32 cpsr;
2136         int retval;
2137         int last_reg = 0;
2138
2139 #ifdef _DEBUG_ARM7_9_
2140         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2141 #endif
2142
2143         if (target->state != TARGET_HALTED)
2144         {
2145                 LOG_WARNING("target not halted");
2146                 return ERROR_TARGET_NOT_HALTED;
2147         }
2148
2149         /* sanitize arguments */
2150         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2151                 return ERROR_INVALID_ARGUMENTS;
2152
2153         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2154                 return ERROR_TARGET_UNALIGNED_ACCESS;
2155
2156         /* load the base register with the address of the first word */
2157         reg[0] = address;
2158         arm7_9->write_core_regs(target, 0x1, reg);
2159
2160         /* Clear DBGACK, to make sure memory fetches work as expected */
2161         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2162         embeddedice_store_reg(dbg_ctrl);
2163
2164         switch (size)
2165         {
2166                 case 4:
2167                         while (num_accesses < count)
2168                         {
2169                                 u32 reg_list;
2170                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2171                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2172
2173                                 for (i = 1; i <= thisrun_accesses; i++)
2174                                 {
2175                                         if (i > last_reg)
2176                                                 last_reg = i;
2177                                         reg[i] = target_buffer_get_u32(target, buffer);
2178                                         buffer += 4;
2179                                 }
2180
2181                                 arm7_9->write_core_regs(target, reg_list, reg);
2182
2183                                 arm7_9->store_word_regs(target, reg_list);
2184
2185                                 /* fast memory writes are only safe when the target is running
2186                                  * from a sufficiently high clock (32 kHz is usually too slow)
2187                                  */
2188                                 if (arm7_9->fast_memory_access)
2189                                         retval = arm7_9_execute_fast_sys_speed(target);
2190                                 else
2191                                         retval = arm7_9_execute_sys_speed(target);
2192                                 if(retval != ERROR_OK)
2193                                 {
2194                                         return retval;
2195                                 }
2196
2197                                 num_accesses += thisrun_accesses;
2198                         }
2199                         break;
2200                 case 2:
2201                         while (num_accesses < count)
2202                         {
2203                                 u32 reg_list;
2204                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2205                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2206
2207                                 for (i = 1; i <= thisrun_accesses; i++)
2208                                 {
2209                                         if (i > last_reg)
2210                                                 last_reg = i;
2211                                         reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2212                                         buffer += 2;
2213                                 }
2214
2215                                 arm7_9->write_core_regs(target, reg_list, reg);
2216
2217                                 for (i = 1; i <= thisrun_accesses; i++)
2218                                 {
2219                                         arm7_9->store_hword_reg(target, i);
2220
2221                                         /* fast memory writes are only safe when the target is running
2222                                          * from a sufficiently high clock (32 kHz is usually too slow)
2223                                          */
2224                                         if (arm7_9->fast_memory_access)
2225                                                 retval = arm7_9_execute_fast_sys_speed(target);
2226                                         else
2227                                                 retval = arm7_9_execute_sys_speed(target);
2228                                         if(retval != ERROR_OK)
2229                                         {
2230                                                 return retval;
2231                                         }
2232                                 }
2233
2234                                 num_accesses += thisrun_accesses;
2235                         }
2236                         break;
2237                 case 1:
2238                         while (num_accesses < count)
2239                         {
2240                                 u32 reg_list;
2241                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2242                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2243
2244                                 for (i = 1; i <= thisrun_accesses; i++)
2245                                 {
2246                                         if (i > last_reg)
2247                                                 last_reg = i;
2248                                         reg[i] = *buffer++ & 0xff;
2249                                 }
2250
2251                                 arm7_9->write_core_regs(target, reg_list, reg);
2252
2253                                 for (i = 1; i <= thisrun_accesses; i++)
2254                                 {
2255                                         arm7_9->store_byte_reg(target, i);
2256                                         /* fast memory writes are only safe when the target is running
2257                                          * from a sufficiently high clock (32 kHz is usually too slow)
2258                                          */
2259                                         if (arm7_9->fast_memory_access)
2260                                                 retval = arm7_9_execute_fast_sys_speed(target);
2261                                         else
2262                                                 retval = arm7_9_execute_sys_speed(target);
2263                                         if(retval != ERROR_OK)
2264                                         {
2265                                                 return retval;
2266                                         }
2267
2268                                 }
2269
2270                                 num_accesses += thisrun_accesses;
2271                         }
2272                         break;
2273                 default:
2274                         LOG_ERROR("BUG: we shouldn't get here");
2275                         exit(-1);
2276                         break;
2277         }
2278
2279         /* Re-Set DBGACK */
2280         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2281         embeddedice_store_reg(dbg_ctrl);
2282
2283         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2284                 return ERROR_FAIL;
2285
2286         for (i=0; i<=last_reg; i++)
2287                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2288
2289         arm7_9->read_xpsr(target, &cpsr, 0);
2290         if ((retval = jtag_execute_queue()) != ERROR_OK)
2291         {
2292                 LOG_ERROR("JTAG error while reading cpsr");
2293                 return ERROR_TARGET_DATA_ABORT;
2294         }
2295
2296         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2297         {
2298                 LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2299
2300                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2301
2302                 return ERROR_TARGET_DATA_ABORT;
2303         }
2304
2305         return ERROR_OK;
2306 }
2307
2308 static int dcc_count;
2309 static u8 *dcc_buffer;
2310
2311
2312 static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
2313 {
2314         int retval = ERROR_OK;
2315         armv4_5_common_t *armv4_5 = target->arch_info;
2316         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2317
2318         if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
2319                 return retval;
2320
2321         int little=target->endianness==TARGET_LITTLE_ENDIAN;
2322         int count=dcc_count;
2323         u8 *buffer=dcc_buffer;
2324         if (count>2)
2325         {
2326                 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2327                    core function repeated.
2328                  */
2329                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2330                 buffer+=4;
2331
2332                 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2333                 u8 reg_addr = ice_reg->addr & 0x1f;
2334                 int chain_pos = ice_reg->jtag_info->chain_pos;
2335
2336                 embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
2337                 buffer += (count-2)*4;
2338
2339                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2340         } else
2341         {
2342                 int i;
2343                 for (i = 0; i < count; i++)
2344                 {
2345                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2346                         buffer += 4;
2347                 }
2348         }
2349
2350         if((retval = target_halt(target))!= ERROR_OK)
2351         {
2352                 return retval;
2353         }
2354         return target_wait_state(target, TARGET_HALTED, 500);
2355 }
2356
2357
2358 static const u32 dcc_code[] =
2359 {
2360         /* MRC      TST         BNE         MRC         STR         B */
2361         0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2362 };
2363
2364 int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info));
2365
2366
2367 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2368 {
2369         int retval;
2370         armv4_5_common_t *armv4_5 = target->arch_info;
2371         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2372         int i;
2373
2374         if (!arm7_9->dcc_downloads)
2375                 return target->type->write_memory(target, address, 4, count, buffer);
2376
2377         /* regrab previously allocated working_area, or allocate a new one */
2378         if (!arm7_9->dcc_working_area)
2379         {
2380                 u8 dcc_code_buf[6 * 4];
2381
2382                 /* make sure we have a working area */
2383                 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2384                 {
2385                         LOG_INFO("no working area available, falling back to memory writes");
2386                         return target->type->write_memory(target, address, 4, count, buffer);
2387                 }
2388
2389                 /* copy target instructions to target endianness */
2390                 for (i = 0; i < 6; i++)
2391                 {
2392                         target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2393                 }
2394
2395                 /* write DCC code to working area */
2396                 if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2397                 {
2398                         return retval;
2399                 }
2400         }
2401
2402         armv4_5_algorithm_t armv4_5_info;
2403         reg_param_t reg_params[1];
2404
2405         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2406         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2407         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2408
2409         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2410
2411         buf_set_u32(reg_params[0].value, 0, 32, address);
2412
2413         //armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
2414         // int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
2415         dcc_count=count;
2416         dcc_buffer=buffer;
2417         retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2418                         arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
2419
2420         if (retval==ERROR_OK)
2421         {
2422                 u32 endaddress=buf_get_u32(reg_params[0].value, 0, 32);
2423                 if (endaddress!=(address+count*4))
2424                 {
2425                         LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress);
2426                         retval=ERROR_FAIL;
2427                 }
2428         }
2429
2430         destroy_reg_param(&reg_params[0]);
2431
2432         return retval;
2433 }
2434
2435 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2436 {
2437         working_area_t *crc_algorithm;
2438         armv4_5_algorithm_t armv4_5_info;
2439         reg_param_t reg_params[2];
2440         int retval;
2441
2442         u32 arm7_9_crc_code[] = {
2443                 0xE1A02000,                             /* mov          r2, r0 */
2444                 0xE3E00000,                             /* mov          r0, #0xffffffff */
2445                 0xE1A03001,                             /* mov          r3, r1 */
2446                 0xE3A04000,                             /* mov          r4, #0 */
2447                 0xEA00000B,                             /* b            ncomp */
2448                                                                 /* nbyte: */
2449                 0xE7D21004,                             /* ldrb r1, [r2, r4] */
2450                 0xE59F7030,                             /* ldr          r7, CRC32XOR */
2451                 0xE0200C01,                             /* eor          r0, r0, r1, asl 24 */
2452                 0xE3A05000,                             /* mov          r5, #0 */
2453                                                                 /* loop: */
2454                 0xE3500000,                             /* cmp          r0, #0 */
2455                 0xE1A06080,                             /* mov          r6, r0, asl #1 */
2456                 0xE2855001,                             /* add          r5, r5, #1 */
2457                 0xE1A00006,                             /* mov          r0, r6 */
2458                 0xB0260007,                             /* eorlt        r0, r6, r7 */
2459                 0xE3550008,                             /* cmp          r5, #8 */
2460                 0x1AFFFFF8,                             /* bne          loop */
2461                 0xE2844001,                             /* add          r4, r4, #1 */
2462                                                                 /* ncomp: */
2463                 0xE1540003,                             /* cmp          r4, r3 */
2464                 0x1AFFFFF1,                             /* bne          nbyte */
2465                                                                 /* end: */
2466                 0xEAFFFFFE,                             /* b            end */
2467                 0x04C11DB7                              /* CRC32XOR:    .word 0x04C11DB7 */
2468         };
2469
2470         int i;
2471
2472         if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2473         {
2474                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2475         }
2476
2477         /* convert flash writing code into a buffer in target endianness */
2478         for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2479         {
2480                 if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]))!=ERROR_OK)
2481                 {
2482                         return retval;
2483                 }
2484         }
2485
2486         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2487         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2488         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2489
2490         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2491         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2492
2493         buf_set_u32(reg_params[0].value, 0, 32, address);
2494         buf_set_u32(reg_params[1].value, 0, 32, count);
2495
2496         if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2497                 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2498         {
2499                 LOG_ERROR("error executing arm7_9 crc algorithm");
2500                 destroy_reg_param(&reg_params[0]);
2501                 destroy_reg_param(&reg_params[1]);
2502                 target_free_working_area(target, crc_algorithm);
2503                 return retval;
2504         }
2505
2506         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2507
2508         destroy_reg_param(&reg_params[0]);
2509         destroy_reg_param(&reg_params[1]);
2510
2511         target_free_working_area(target, crc_algorithm);
2512
2513         return ERROR_OK;
2514 }
2515
2516 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
2517 {
2518         working_area_t *erase_check_algorithm;
2519         reg_param_t reg_params[3];
2520         armv4_5_algorithm_t armv4_5_info;
2521         int retval;
2522         int i;
2523
2524         u32 erase_check_code[] =
2525         {
2526                                                 /* loop: */
2527                 0xe4d03001,             /* ldrb r3, [r0], #1    */
2528                 0xe0022003,             /* and r2, r2, r3               */
2529                 0xe2511001,     /* subs r1, r1, #1              */
2530                 0x1afffffb,             /* bne loop                             */
2531                                                 /* end: */
2532                 0xeafffffe              /* b end                                */
2533         };
2534
2535         /* make sure we have a working area */
2536         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
2537         {
2538                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2539         }
2540
2541         /* convert flash writing code into a buffer in target endianness */
2542         for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
2543                 if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK)
2544                 {
2545                         return retval;
2546                 }
2547
2548         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2549         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2550         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2551
2552         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
2553         buf_set_u32(reg_params[0].value, 0, 32, address);
2554
2555         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2556         buf_set_u32(reg_params[1].value, 0, 32, count);
2557
2558         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
2559         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2560
2561         if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
2562                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
2563         {
2564                 destroy_reg_param(&reg_params[0]);
2565                 destroy_reg_param(&reg_params[1]);
2566                 destroy_reg_param(&reg_params[2]);
2567                 target_free_working_area(target, erase_check_algorithm);
2568                 return 0;
2569         }
2570
2571         *blank = buf_get_u32(reg_params[2].value, 0, 32);
2572
2573         destroy_reg_param(&reg_params[0]);
2574         destroy_reg_param(&reg_params[1]);
2575         destroy_reg_param(&reg_params[2]);
2576
2577         target_free_working_area(target, erase_check_algorithm);
2578
2579         return ERROR_OK;
2580 }
2581
2582 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2583 {
2584         command_t *arm7_9_cmd;
2585
2586         arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2587
2588         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2589         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2590
2591         register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2592
2593         register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2594                 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2595         register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2596                  COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2597         register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2598                  COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2599         register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2600                 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2601
2602         armv4_5_register_commands(cmd_ctx);
2603
2604         etm_register_commands(cmd_ctx);
2605
2606         return ERROR_OK;
2607 }
2608
2609 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2610 {
2611         u32 value;
2612         int spsr;
2613         int retval;
2614         target_t *target = get_current_target(cmd_ctx);
2615         armv4_5_common_t *armv4_5;
2616         arm7_9_common_t *arm7_9;
2617
2618         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2619         {
2620                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2621                 return ERROR_OK;
2622         }
2623
2624         if (target->state != TARGET_HALTED)
2625         {
2626                 command_print(cmd_ctx, "can't write registers while running");
2627                 return ERROR_OK;
2628         }
2629
2630         if (argc < 2)
2631         {
2632                 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2633                 return ERROR_OK;
2634         }
2635
2636         value = strtoul(args[0], NULL, 0);
2637         spsr = strtol(args[1], NULL, 0);
2638
2639         /* if we're writing the CPSR, mask the T bit */
2640         if (!spsr)
2641                 value &= ~0x20;
2642
2643         arm7_9->write_xpsr(target, value, spsr);
2644         if ((retval = jtag_execute_queue()) != ERROR_OK)
2645         {
2646                 LOG_ERROR("JTAG error while writing to xpsr");
2647                 return retval;
2648         }
2649
2650         return ERROR_OK;
2651 }
2652
2653 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2654 {
2655         u32 value;
2656         int rotate;
2657         int spsr;
2658         int retval;
2659         target_t *target = get_current_target(cmd_ctx);
2660         armv4_5_common_t *armv4_5;
2661         arm7_9_common_t *arm7_9;
2662
2663         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2664         {
2665                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2666                 return ERROR_OK;
2667         }
2668
2669         if (target->state != TARGET_HALTED)
2670         {
2671                 command_print(cmd_ctx, "can't write registers while running");
2672                 return ERROR_OK;
2673         }
2674
2675         if (argc < 3)
2676         {
2677                 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2678                 return ERROR_OK;
2679         }
2680
2681         value = strtoul(args[0], NULL, 0);
2682         rotate = strtol(args[1], NULL, 0);
2683         spsr = strtol(args[2], NULL, 0);
2684
2685         arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2686         if ((retval = jtag_execute_queue()) != ERROR_OK)
2687         {
2688                 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2689                 return retval;
2690         }
2691
2692         return ERROR_OK;
2693 }
2694
2695 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2696 {
2697         u32 value;
2698         u32 mode;
2699         int num;
2700         target_t *target = get_current_target(cmd_ctx);
2701         armv4_5_common_t *armv4_5;
2702         arm7_9_common_t *arm7_9;
2703
2704         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2705         {
2706                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2707                 return ERROR_OK;
2708         }
2709
2710         if (target->state != TARGET_HALTED)
2711         {
2712                 command_print(cmd_ctx, "can't write registers while running");
2713                 return ERROR_OK;
2714         }
2715
2716         if (argc < 3)
2717         {
2718                 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2719                 return ERROR_OK;
2720         }
2721
2722         num = strtol(args[0], NULL, 0);
2723         mode = strtoul(args[1], NULL, 0);
2724         value = strtoul(args[2], NULL, 0);
2725
2726         return arm7_9_write_core_reg(target, num, mode, value);
2727
2728 }
2729
2730
2731 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2732 {
2733         target_t *target = get_current_target(cmd_ctx);
2734         armv4_5_common_t *armv4_5;
2735         arm7_9_common_t *arm7_9;
2736
2737         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2738         {
2739                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2740                 return ERROR_OK;
2741         }
2742
2743         if (argc > 0)
2744         {
2745                 if (strcmp("enable", args[0]) == 0)
2746                 {
2747                         arm7_9->use_dbgrq = 1;
2748                 }
2749                 else if (strcmp("disable", args[0]) == 0)
2750                 {
2751                         arm7_9->use_dbgrq = 0;
2752                 }
2753                 else
2754                 {
2755                         command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2756                 }
2757         }
2758
2759         command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2760
2761         return ERROR_OK;
2762 }
2763
2764 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2765 {
2766         target_t *target = get_current_target(cmd_ctx);
2767         armv4_5_common_t *armv4_5;
2768         arm7_9_common_t *arm7_9;
2769
2770         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2771         {
2772                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2773                 return ERROR_OK;
2774         }
2775
2776         if (argc > 0)
2777         {
2778                 if (strcmp("enable", args[0]) == 0)
2779                 {
2780                         arm7_9->fast_memory_access = 1;
2781                 }
2782                 else if (strcmp("disable", args[0]) == 0)
2783                 {
2784                         arm7_9->fast_memory_access = 0;
2785                 }
2786                 else
2787                 {
2788                         command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2789                 }
2790         }
2791
2792         command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2793
2794         return ERROR_OK;
2795 }
2796
2797 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2798 {
2799         target_t *target = get_current_target(cmd_ctx);
2800         armv4_5_common_t *armv4_5;
2801         arm7_9_common_t *arm7_9;
2802
2803         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2804         {
2805                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2806                 return ERROR_OK;
2807         }
2808
2809         if (argc > 0)
2810         {
2811                 if (strcmp("enable", args[0]) == 0)
2812                 {
2813                         arm7_9->dcc_downloads = 1;
2814                 }
2815                 else if (strcmp("disable", args[0]) == 0)
2816                 {
2817                         arm7_9->dcc_downloads = 0;
2818                 }
2819                 else
2820                 {
2821                         command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2822                 }
2823         }
2824
2825         command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2826
2827         return ERROR_OK;
2828 }
2829
2830 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2831 {
2832         int retval = ERROR_OK;
2833         armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2834
2835         arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2836
2837         if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2838         {
2839                 return retval;
2840         }
2841
2842         arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
2843         arm7_9->wp_available_max = 2;
2844         arm7_9->sw_breakpoints_added = 0;
2845         arm7_9->breakpoint_count = 0;
2846         arm7_9->wp0_used = 0;
2847         arm7_9->wp1_used = 0;
2848         arm7_9->wp1_used_default = 0;
2849         arm7_9->use_dbgrq = 0;
2850
2851         arm7_9->etm_ctx = NULL;
2852         arm7_9->has_single_step = 0;
2853         arm7_9->has_monitor_mode = 0;
2854         arm7_9->has_vector_catch = 0;
2855
2856         arm7_9->debug_entry_from_reset = 0;
2857
2858         arm7_9->dcc_working_area = NULL;
2859
2860         arm7_9->fast_memory_access = fast_and_dangerous;
2861         arm7_9->dcc_downloads = fast_and_dangerous;
2862
2863         arm7_9->need_bypass_before_restart = 0;
2864
2865         armv4_5->arch_info = arm7_9;
2866         armv4_5->read_core_reg = arm7_9_read_core_reg;
2867         armv4_5->write_core_reg = arm7_9_write_core_reg;
2868         armv4_5->full_context = arm7_9_full_context;
2869
2870         if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
2871         {
2872                 return retval;
2873         }
2874
2875         if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
2876         {
2877                 return retval;
2878         }
2879
2880         return ERROR_OK;
2881 }