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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "embeddedice.h"
  27 #include "target.h"
  28 #include "armv4_5.h"
  29 #include "arm_jtag.h"
  30 #include "jtag.h"
  31 #include "log.h"
  32 #include "arm7_9_common.h"
  33 #include "breakpoints.h"
  34
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <unistd.h>
  38
  39 #include <sys/types.h>
  40 #include <sys/stat.h>
  41 #include <sys/time.h>
  42 #include <errno.h>
  43
  44 int arm7_9_debug_entry(target_t *target);
  45 int arm7_9_enable_sw_bkpts(struct target_s *target);
  46
  47 /* command handler forward declarations */
  48 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  55 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  56 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  57
  58 int arm7_9_reinit_embeddedice(target_t *target)
  59 {
  60         armv4_5_common_t *armv4_5 = target->arch_info;
  61         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  62
  63         breakpoint_t *breakpoint = target->breakpoints;
  64
  65         arm7_9->wp_available = 2;
  66         arm7_9->wp0_used = 0;
  67         arm7_9->wp1_used = 0;
  68
  69         /* mark all hardware breakpoints as unset */
  70         while (breakpoint)
  71         {
  72                 if (breakpoint->type == BKPT_HARD)
  73                 {
  74                         breakpoint->set = 0;
  75                 }
  76                 breakpoint = breakpoint->next;
  77         }
  78
  79         if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
  80         {
  81                 arm7_9->sw_bkpts_enabled = 0;
  82                 arm7_9_enable_sw_bkpts(target);
  83         }
  84
  85         arm7_9->reinit_embeddedice = 0;
  86
  87         return ERROR_OK;
  88 }
  89
  90 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
  91 {
  92         target_t *target = priv;
  93         armv4_5_common_t *armv4_5 = target->arch_info;
  94         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  95
  96         /* a test-logic reset occured
  97          * the EmbeddedICE registers have been reset
  98          * hardware breakpoints have been cleared
  99          */
 100         if (event == JTAG_TRST_ASSERTED)
 101         {
 102                 arm7_9->reinit_embeddedice = 1;
 103         }
 104
 105         return ERROR_OK;
 106 }
 107
 108 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
 109 {
 110         armv4_5_common_t *armv4_5 = target->arch_info;
 111         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 112
 113         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 114         {
 115                 return -1;
 116         }
 117
 118         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 119         {
 120                 return -1;
 121         }
 122
 123         *armv4_5_p = armv4_5;
 124         *arm7_9_p = arm7_9;
 125
 126         return ERROR_OK;
 127 }
 128
 129 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 130 {
 131         armv4_5_common_t *armv4_5 = target->arch_info;
 132         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 133
 134         if (target->state != TARGET_HALTED)
 135         {
 136                 WARNING("target not halted");
 137                 return ERROR_TARGET_NOT_HALTED;
 138         }
 139
 140         if (arm7_9->force_hw_bkpts)
 141                 breakpoint->type = BKPT_HARD;
 142
 143         if (breakpoint->set)
 144         {
 145                 WARNING("breakpoint already set");
 146                 return ERROR_OK;
 147         }
 148
 149         if (breakpoint->type == BKPT_HARD)
 150         {
 151                 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
 152                 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 153                 if (!arm7_9->wp0_used)
 154                 {
 155                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
 156                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 157                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
 158                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 159                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 160
 161                         jtag_execute_queue();
 162                         arm7_9->wp0_used = 1;
 163                         breakpoint->set = 1;
 164                 }
 165                 else if (!arm7_9->wp1_used)
 166                 {
 167                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
 168                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 169                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
 170                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 171                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 172
 173                         jtag_execute_queue();
 174                         arm7_9->wp1_used = 1;
 175                         breakpoint->set = 2;
 176                 }
 177                 else
 178                 {
 179                         ERROR("BUG: no hardware comparator available");
 180                         return ERROR_OK;
 181                 }
 182         }
 183         else if (breakpoint->type == BKPT_SOFT)
 184         {
 185                 if (breakpoint->length == 4)
 186                 {
 187                         /* keep the original instruction in target endianness */
 188                         target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 189                         /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 190                         target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
 191                 }
 192                 else
 193                 {
 194                         /* keep the original instruction in target endianness */
 195                         target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 196                         /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 197                         target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt);
 198                 }
 199                 breakpoint->set = 1;
 200         }
 201
 202         return ERROR_OK;
 203
 204 }
 205
 206 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 207 {
 208         armv4_5_common_t *armv4_5 = target->arch_info;
 209         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 210
 211         if (target->state != TARGET_HALTED)
 212         {
 213                 WARNING("target not halted");
 214                 return ERROR_TARGET_NOT_HALTED;
 215         }
 216
 217         if (!breakpoint->set)
 218         {
 219                 WARNING("breakpoint not set");
 220                 return ERROR_OK;
 221         }
 222
 223         if (breakpoint->type == BKPT_HARD)
 224         {
 225                 if (breakpoint->set == 1)
 226                 {
 227                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 228                         jtag_execute_queue();
 229                         arm7_9->wp0_used = 0;
 230                 }
 231                 else if (breakpoint->set == 2)
 232                 {
 233                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 234                         jtag_execute_queue();
 235                         arm7_9->wp1_used = 0;
 236                 }
 237                 breakpoint->set = 0;
 238         }
 239         else
 240         {
 241                 /* restore original instruction (kept in target endianness) */
 242                 if (breakpoint->length == 4)
 243                 {
 244                         target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 245                 }
 246                 else
 247                 {
 248                         target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 249                 }
 250                 breakpoint->set = 0;
 251         }
 252
 253         return ERROR_OK;
 254 }
 255
 256 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 257 {
 258         armv4_5_common_t *armv4_5 = target->arch_info;
 259         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 260
 261         if (target->state != TARGET_HALTED)
 262         {
 263                 WARNING("target not halted");
 264                 return ERROR_TARGET_NOT_HALTED;
 265         }
 266
 267         if (arm7_9->force_hw_bkpts)
 268         {
 269                 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
 270                 breakpoint->type = BKPT_HARD;
 271         }
 272
 273         if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
 274         {
 275                 INFO("sw breakpoint requested, but software breakpoints not enabled");
 276                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 277         }
 278
 279         if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
 280         {
 281                 INFO("no watchpoint unit available for hardware breakpoint");
 282                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 283         }
 284
 285         if ((breakpoint->length != 2) && (breakpoint->length != 4))
 286         {
 287                 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 288                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 289         }
 290
 291         if (breakpoint->type == BKPT_HARD)
 292                 arm7_9->wp_available--;
 293
 294         return ERROR_OK;
 295 }
 296
 297 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 298 {
 299         armv4_5_common_t *armv4_5 = target->arch_info;
 300         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 301
 302         if (target->state != TARGET_HALTED)
 303         {
 304                 WARNING("target not halted");
 305                 return ERROR_TARGET_NOT_HALTED;
 306         }
 307
 308         if (breakpoint->set)
 309         {
 310                 arm7_9_unset_breakpoint(target, breakpoint);
 311         }
 312
 313         if (breakpoint->type == BKPT_HARD)
 314                 arm7_9->wp_available++;
 315
 316         return ERROR_OK;
 317 }
 318
 319 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 320 {
 321         armv4_5_common_t *armv4_5 = target->arch_info;
 322         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 323         int rw_mask = 1;
 324         u32 mask;
 325
 326         mask = watchpoint->length - 1;
 327
 328         if (target->state != TARGET_HALTED)
 329         {
 330                 WARNING("target not halted");
 331                 return ERROR_TARGET_NOT_HALTED;
 332         }
 333
 334         if (watchpoint->rw == WPT_ACCESS)
 335                 rw_mask = 0;
 336         else
 337                 rw_mask = 1;
 338
 339         if (!arm7_9->wp0_used)
 340         {
 341                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
 342                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 343                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
 344                 if( watchpoint->mask != 0xffffffffu )
 345                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
 346                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 347                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 348
 349                 jtag_execute_queue();
 350                 watchpoint->set = 1;
 351                 arm7_9->wp0_used = 2;
 352         }
 353         else if (!arm7_9->wp1_used)
 354         {
 355                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
 356                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 357                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
 358                 if( watchpoint->mask != 0xffffffffu )
 359                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
 360                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 361                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 362
 363                 jtag_execute_queue();
 364                 watchpoint->set = 2;
 365                 arm7_9->wp1_used = 2;
 366         }
 367         else
 368         {
 369                 ERROR("BUG: no hardware comparator available");
 370                 return ERROR_OK;
 371         }
 372
 373         return ERROR_OK;
 374 }
 375
 376 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 377 {
 378         armv4_5_common_t *armv4_5 = target->arch_info;
 379         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 380
 381         if (target->state != TARGET_HALTED)
 382         {
 383                 WARNING("target not halted");
 384                 return ERROR_TARGET_NOT_HALTED;
 385         }
 386
 387         if (!watchpoint->set)
 388         {
 389                 WARNING("breakpoint not set");
 390                 return ERROR_OK;
 391         }
 392
 393         if (watchpoint->set == 1)
 394         {
 395                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 396                 jtag_execute_queue();
 397                 arm7_9->wp0_used = 0;
 398         }
 399         else if (watchpoint->set == 2)
 400         {
 401                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 402                 jtag_execute_queue();
 403                 arm7_9->wp1_used = 0;
 404         }
 405         watchpoint->set = 0;
 406
 407         return ERROR_OK;
 408 }
 409
 410 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 411 {
 412         armv4_5_common_t *armv4_5 = target->arch_info;
 413         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 414
 415         if (target->state != TARGET_HALTED)
 416         {
 417                 WARNING("target not halted");
 418                 return ERROR_TARGET_NOT_HALTED;
 419         }
 420
 421         if (arm7_9->wp_available < 1)
 422         {
 423                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 424         }
 425
 426         if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
 427         {
 428                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 429         }
 430
 431         arm7_9->wp_available--;
 432
 433         return ERROR_OK;
 434 }
 435
 436 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 437 {
 438         armv4_5_common_t *armv4_5 = target->arch_info;
 439         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 440
 441         if (target->state != TARGET_HALTED)
 442         {
 443                 WARNING("target not halted");
 444                 return ERROR_TARGET_NOT_HALTED;
 445         }
 446
 447         if (watchpoint->set)
 448         {
 449                 arm7_9_unset_watchpoint(target, watchpoint);
 450         }
 451
 452         arm7_9->wp_available++;
 453
 454         return ERROR_OK;
 455 }
 456
 457 int arm7_9_enable_sw_bkpts(struct target_s *target)
 458 {
 459         armv4_5_common_t *armv4_5 = target->arch_info;
 460         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 461         int retval;
 462
 463         if (arm7_9->sw_bkpts_enabled)
 464                 return ERROR_OK;
 465
 466         if (arm7_9->wp_available < 1)
 467         {
 468                 WARNING("can't enable sw breakpoints with no watchpoint unit available");
 469                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 470         }
 471         arm7_9->wp_available--;
 472
 473         if (!arm7_9->wp0_used)
 474         {
 475                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
 476                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
 477                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
 478                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 479                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 480                 arm7_9->sw_bkpts_enabled = 1;
 481                 arm7_9->wp0_used = 3;
 482         }
 483         else if (!arm7_9->wp1_used)
 484         {
 485                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
 486                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
 487                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
 488                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 489                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 490                 arm7_9->sw_bkpts_enabled = 2;
 491                 arm7_9->wp1_used = 3;
 492         }
 493         else
 494         {
 495                 ERROR("BUG: both watchpoints used, but wp_available >= 1");
 496                 exit(-1);
 497         }
 498
 499         if ((retval = jtag_execute_queue()) != ERROR_OK)
 500         {
 501                 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
 502                 exit(-1);
 503         };
 504
 505         return ERROR_OK;
 506 }
 507
 508 int arm7_9_disable_sw_bkpts(struct target_s *target)
 509 {
 510         armv4_5_common_t *armv4_5 = target->arch_info;
 511         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 512
 513         if (!arm7_9->sw_bkpts_enabled)
 514                 return ERROR_OK;
 515
 516         if (arm7_9->sw_bkpts_enabled == 1)
 517         {
 518                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 519                 arm7_9->sw_bkpts_enabled = 0;
 520                 arm7_9->wp0_used = 0;
 521                 arm7_9->wp_available++;
 522         }
 523         else if (arm7_9->sw_bkpts_enabled == 2)
 524         {
 525                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 526                 arm7_9->sw_bkpts_enabled = 0;
 527                 arm7_9->wp1_used = 0;
 528                 arm7_9->wp_available++;
 529         }
 530
 531         return ERROR_OK;
 532 }
 533
 534 int arm7_9_execute_sys_speed(struct target_s *target)
 535 {
 536         int timeout;
 537         int retval;
 538
 539         armv4_5_common_t *armv4_5 = target->arch_info;
 540         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 541         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 542         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 543
 544         /* set RESTART instruction */
 545         jtag_add_end_state(TAP_RTI);
 546         arm_jtag_set_instr(jtag_info, 0x4);
 547
 548         for (timeout=0; timeout<50; timeout++)
 549         {
 550                 /* read debug status register */
 551                 embeddedice_read_reg(dbg_stat);
 552                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 553                         return retval;
 554                 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 555                                    && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 556                         break;
 557                 usleep(100000);
 558         }
 559         if (timeout == 50)
 560         {
 561                 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 562                 return ERROR_TARGET_TIMEOUT;
 563         }
 564
 565         return ERROR_OK;
 566 }
 567
 568 int arm7_9_execute_fast_sys_speed(struct target_s *target)
 569 {
 570         u8 check_value[4], check_mask[4];
 571
 572         armv4_5_common_t *armv4_5 = target->arch_info;
 573         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 574         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 575         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 576
 577         /* set RESTART instruction */
 578         jtag_add_end_state(TAP_RTI);
 579         arm_jtag_set_instr(jtag_info, 0x4);
 580
 581         /* check for DBGACK and SYSCOMP set (others don't care) */
 582         buf_set_u32(check_value, 0, 32, 0x9);
 583         buf_set_u32(check_mask, 0, 32, 0x9);
 584
 585         /* read debug status register */
 586         embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
 587
 588         return ERROR_OK;
 589 }
 590
 591 enum target_state arm7_9_poll(target_t *target)
 592 {
 593         int retval;
 594         armv4_5_common_t *armv4_5 = target->arch_info;
 595         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 596         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 597
 598         if (arm7_9->reinit_embeddedice)
 599         {
 600                 arm7_9_reinit_embeddedice(target);
 601         }
 602
 603         /* read debug status register */
 604         embeddedice_read_reg(dbg_stat);
 605         if ((retval = jtag_execute_queue()) != ERROR_OK)
 606         {
 607                 switch (retval)
 608                 {
 609                         case ERROR_JTAG_QUEUE_FAILED:
 610                                 ERROR("JTAG queue failed while reading EmbeddedICE status register");
 611                                 exit(-1);
 612                                 break;
 613                         default:
 614                                 break;
 615                 }
 616         }
 617
 618         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 619         {
 620                 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
 621                 if ((target->state == TARGET_UNKNOWN))
 622                 {
 623                         WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
 624                         target->state = TARGET_RUNNING;
 625                 }
 626                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 627                 {
 628                         target->state = TARGET_HALTED;
 629                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 630                                 return retval;
 631
 632                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 633                 }
 634                 if (target->state == TARGET_DEBUG_RUNNING)
 635                 {
 636                         target->state = TARGET_HALTED;
 637                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 638                                 return retval;
 639
 640                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 641                 }
 642         }
 643         else
 644         {
 645                 if (target->state != TARGET_DEBUG_RUNNING)
 646                         target->state = TARGET_RUNNING;
 647         }
 648
 649         return target->state;
 650 }
 651
 652 int arm7_9_assert_reset(target_t *target)
 653 {
 654         int retval;
 655
 656         DEBUG("target->state: %s", target_state_strings[target->state]);
 657
 658         if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
 659         {
 660                 /* if the target wasn't running, there might be working areas allocated */
 661                 target_free_all_working_areas(target);
 662
 663                 /* assert SRST and TRST */
 664                 /* system would get ouf sync if we didn't reset test-logic, too */
 665                 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
 666                 {
 667                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 668                         {
 669                                 WARNING("can't assert srst");
 670                                 return retval;
 671                         }
 672                         else
 673                         {
 674                                 ERROR("unknown error");
 675                                 exit(-1);
 676                         }
 677                 }
 678                 jtag_add_sleep(5000);
 679                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 680                 {
 681                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 682                         {
 683                                 WARNING("srst resets test logic, too");
 684                                 retval = jtag_add_reset(1, 1);
 685                         }
 686                 }
 687         }
 688         else
 689         {
 690                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 691                 {
 692                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 693                         {
 694                                 WARNING("srst resets test logic, too");
 695                                 retval = jtag_add_reset(1, 1);
 696                         }
 697
 698                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 699                         {
 700                                 WARNING("can't assert srst");
 701                                 return retval;
 702                         }
 703                         else if (retval != ERROR_OK)
 704                         {
 705                                 ERROR("unknown error");
 706                                 exit(-1);
 707                         }
 708                 }
 709         }
 710
 711         target->state = TARGET_RESET;
 712         jtag_add_sleep(50000);
 713
 714         armv4_5_invalidate_core_regs(target);
 715
 716         return ERROR_OK;
 717
 718 }
 719
 720 int arm7_9_deassert_reset(target_t *target)
 721 {
 722         DEBUG("target->state: %s", target_state_strings[target->state]);
 723
 724         /* deassert reset lines */
 725         jtag_add_reset(0, 0);
 726
 727         return ERROR_OK;
 728
 729 }
 730
 731 int arm7_9_clear_halt(target_t *target)
 732 {
 733         armv4_5_common_t *armv4_5 = target->arch_info;
 734         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 735         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 736
 737         if (arm7_9->use_dbgrq)
 738         {
 739                 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
 740                  */
 741                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 742                 embeddedice_store_reg(dbg_ctrl);
 743         }
 744         else
 745         {
 746                 /* restore registers if watchpoint unit 0 was in use
 747                  */
 748                 if (arm7_9->wp0_used)
 749                 {
 750                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
 751                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
 752                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
 753                 }
 754                 /* control value always has to be restored, as it was either disabled,
 755                  * or enabled with possibly different bits
 756                  */
 757                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 758         }
 759
 760         return ERROR_OK;
 761 }
 762
 763 int arm7_9_soft_reset_halt(struct target_s *target)
 764 {
 765         armv4_5_common_t *armv4_5 = target->arch_info;
 766         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 767         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 768         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 769         int i;
 770
 771         if (target->state == TARGET_RUNNING)
 772         {
 773                 target->type->halt(target);
 774         }
 775
 776         while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
 777         {
 778                 embeddedice_read_reg(dbg_stat);
 779                 jtag_execute_queue();
 780         }
 781         target->state = TARGET_HALTED;
 782
 783         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 784          * ensure that DBGRQ is cleared
 785          */
 786         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 787         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 788         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 789         embeddedice_store_reg(dbg_ctrl);
 790
 791         arm7_9_clear_halt(target);
 792
 793         /* if the target is in Thumb state, change to ARM state */
 794         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
 795         {
 796                 u32 r0_thumb, pc_thumb;
 797                 DEBUG("target entered debug from Thumb state, changing to ARM");
 798                 /* Entered debug from Thumb mode */
 799                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
 800                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
 801         }
 802
 803         /* all register content is now invalid */
 804         armv4_5_invalidate_core_regs(target);
 805
 806         /* SVC, ARM state, IRQ and FIQ disabled */
 807         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 808         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 809         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 810
 811         /* start fetching from 0x0 */
 812         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 813         armv4_5->core_cache->reg_list[15].dirty = 1;
 814         armv4_5->core_cache->reg_list[15].valid = 1;
 815
 816         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 817         armv4_5->core_state = ARMV4_5_STATE_ARM;
 818
 819         /* reset registers */
 820         for (i = 0; i <= 14; i++)
 821         {
 822                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
 823                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
 824                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 825         }
 826
 827         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 828
 829         return ERROR_OK;
 830 }
 831
 832 int arm7_9_halt(target_t *target)
 833 {
 834         armv4_5_common_t *armv4_5 = target->arch_info;
 835         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 836         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 837
 838         DEBUG("target->state: %s", target_state_strings[target->state]);
 839
 840         if (target->state == TARGET_HALTED)
 841         {
 842                 WARNING("target was already halted");
 843                 return ERROR_TARGET_ALREADY_HALTED;
 844         }
 845
 846         if (target->state == TARGET_UNKNOWN)
 847         {
 848                 WARNING("target was in unknown state when halt was requested");
 849         }
 850
 851         if ((target->state == TARGET_RESET) && (jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_srst))
 852         {
 853                 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 854                 return ERROR_TARGET_FAILURE;
 855         }
 856
 857         if (arm7_9->use_dbgrq)
 858         {
 859                 /* program EmbeddedICE Debug Control Register to assert DBGRQ
 860                  */
 861                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
 862                 embeddedice_store_reg(dbg_ctrl);
 863         }
 864         else
 865         {
 866                 /* program watchpoint unit to match on any address
 867                  */
 868                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
 869                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
 870                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
 871                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
 872         }
 873
 874         target->debug_reason = DBG_REASON_DBGRQ;
 875
 876         return ERROR_OK;
 877 }
 878
 879 int arm7_9_debug_entry(target_t *target)
 880 {
 881         int i;
 882         u32 context[16];
 883         u32* context_p[16];
 884         u32 r0_thumb, pc_thumb;
 885         u32 cpsr;
 886         int retval;
 887         /* get pointers to arch-specific information */
 888         armv4_5_common_t *armv4_5 = target->arch_info;
 889         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 890         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 891         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 892
 893 #ifdef _DEBUG_ARM7_9_
 894         DEBUG("");
 895 #endif
 896
 897         if (arm7_9->pre_debug_entry)
 898                 arm7_9->pre_debug_entry(target);
 899
 900         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 901          * ensure that DBGRQ is cleared
 902          */
 903         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 904         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 905         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 906         embeddedice_store_reg(dbg_ctrl);
 907
 908         arm7_9_clear_halt(target);
 909
 910         if ((retval = jtag_execute_queue()) != ERROR_OK)
 911         {
 912                 switch (retval)
 913                 {
 914                         case ERROR_JTAG_QUEUE_FAILED:
 915                                 ERROR("JTAG queue failed while writing EmbeddedICE control register");
 916                                 exit(-1);
 917                                 break;
 918                         default:
 919                                 break;
 920                 }
 921         }
 922
 923         if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
 924                 return retval;
 925
 926
 927         if (target->state != TARGET_HALTED)
 928         {
 929                 WARNING("target not halted");
 930                 return ERROR_TARGET_NOT_HALTED;
 931         }
 932
 933         /* if the target is in Thumb state, change to ARM state */
 934         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
 935         {
 936                 DEBUG("target entered debug from Thumb state");
 937                 /* Entered debug from Thumb mode */
 938                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
 939                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
 940                 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
 941         }
 942         else
 943         {
 944                 DEBUG("target entered debug from ARM state");
 945                 /* Entered debug from ARM mode */
 946                 armv4_5->core_state = ARMV4_5_STATE_ARM;
 947         }
 948
 949         for (i = 0; i < 16; i++)
 950                 context_p[i] = &context[i];
 951         /* save core registers (r0 - r15 of current core mode) */
 952         arm7_9->read_core_regs(target, 0xffff, context_p);
 953
 954         arm7_9->read_xpsr(target, &cpsr, 0);
 955
 956         if ((retval = jtag_execute_queue()) != ERROR_OK)
 957                 return retval;
 958
 959         /* if the core has been executing in Thumb state, set the T bit */
 960         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 961                 cpsr |= 0x20;
 962
 963         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
 964         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
 965         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 966
 967         armv4_5->core_mode = cpsr & 0x1f;
 968
 969         if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
 970         {
 971                 target->state = TARGET_UNKNOWN;
 972                 ERROR("cpsr contains invalid mode value - communication failure");
 973                 return ERROR_TARGET_FAILURE;
 974         }
 975
 976         DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
 977
 978         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 979         {
 980                 DEBUG("thumb state, applying fixups");
 981                 context[0] = r0_thumb;
 982                 context[15] = pc_thumb;
 983         } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 984         {
 985                 /* adjust value stored by STM */
 986                 context[15] -= 3 * 4;
 987         }
 988
 989         if ((target->debug_reason == DBG_REASON_BREAKPOINT)
 990                         || (target->debug_reason == DBG_REASON_SINGLESTEP)
 991                         || (target->debug_reason == DBG_REASON_WATCHPOINT)
 992                         || (target->debug_reason == DBG_REASON_WPTANDBKPT)
 993                         || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
 994                 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 995         else if (target->debug_reason == DBG_REASON_DBGRQ)
 996                 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 997         else
 998         {
 999                 ERROR("unknown debug reason: %i", target->debug_reason);
1000         }
1001
1002
1003         for (i=0; i<=15; i++)
1004         {
1005                 DEBUG("r%i: 0x%8.8x", i, context[i]);
1006                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1007                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1008                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1009         }
1010
1011         DEBUG("entered debug state at PC 0x%x", context[15]);
1012
1013         /* exceptions other than USR & SYS have a saved program status register */
1014         if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1015         {
1016                 u32 spsr;
1017                 arm7_9->read_xpsr(target, &spsr, 1);
1018                 jtag_execute_queue();
1019                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1020                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1021                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1022         }
1023
1024         /* r0 and r15 (pc) have to be restored later */
1025         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1026         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
1027
1028         if ((retval = jtag->execute_queue()) != ERROR_OK)
1029                 return retval;
1030
1031         if (arm7_9->post_debug_entry)
1032                 arm7_9->post_debug_entry(target);
1033
1034         return ERROR_OK;
1035 }
1036
1037 int arm7_9_full_context(target_t *target)
1038 {
1039         int i;
1040         int retval;
1041         armv4_5_common_t *armv4_5 = target->arch_info;
1042         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1043
1044         DEBUG("");
1045
1046         if (target->state != TARGET_HALTED)
1047         {
1048                 WARNING("target not halted");
1049                 return ERROR_TARGET_NOT_HALTED;
1050         }
1051
1052         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1053          * SYS shares registers with User, so we don't touch SYS
1054          */
1055         for(i = 0; i < 6; i++)
1056         {
1057                 u32 mask = 0;
1058                 u32* reg_p[16];
1059                 int j;
1060                 int valid = 1;
1061
1062                 /* check if there are invalid registers in the current mode
1063                  */
1064                 for (j = 0; j <= 16; j++)
1065                 {
1066                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1067                                 valid = 0;
1068                 }
1069
1070                 if (!valid)
1071                 {
1072                         u32 tmp_cpsr;
1073
1074                         /* change processor mode (and mask T bit) */
1075                         tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1076                         tmp_cpsr |= armv4_5_number_to_mode(i);
1077                         tmp_cpsr &= ~0x20;
1078                         arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1079
1080                         for (j = 0; j < 15; j++)
1081                         {
1082                                 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1083                                 {
1084                                         reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1085                                         mask |= 1 << j;
1086                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1087                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1088                                 }
1089                         }
1090
1091                         /* if only the PSR is invalid, mask is all zeroes */
1092                         if (mask)
1093                                 arm7_9->read_core_regs(target, mask, reg_p);
1094
1095                         /* check if the PSR has to be read */
1096                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1097                         {
1098                                 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1099                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1100                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1101                         }
1102                 }
1103         }
1104
1105         /* restore processor mode (mask T bit) */
1106         arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1107
1108         if ((retval = jtag_execute_queue()) != ERROR_OK)
1109         {
1110                 ERROR("JTAG failure");
1111                 exit(-1);
1112         }
1113         return ERROR_OK;
1114 }
1115
1116 int arm7_9_restore_context(target_t *target)
1117 {
1118         armv4_5_common_t *armv4_5 = target->arch_info;
1119         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1120         reg_t *reg;
1121         armv4_5_core_reg_t *reg_arch_info;
1122         enum armv4_5_mode current_mode = armv4_5->core_mode;
1123         int i, j;
1124         int dirty;
1125         int mode_change;
1126
1127         DEBUG("");
1128
1129         if (target->state != TARGET_HALTED)
1130         {
1131                 WARNING("target not halted");
1132                 return ERROR_TARGET_NOT_HALTED;
1133         }
1134
1135         if (arm7_9->pre_restore_context)
1136                 arm7_9->pre_restore_context(target);
1137
1138         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1139          * SYS shares registers with User, so we don't touch SYS
1140          */
1141         for (i = 0; i < 6; i++)
1142         {
1143                 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1144                 dirty = 0;
1145                 mode_change = 0;
1146                 /* check if there are dirty registers in the current mode
1147                 */
1148                 for (j = 0; j <= 16; j++)
1149                 {
1150                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1151                         reg_arch_info = reg->arch_info;
1152                         if (reg->dirty == 1)
1153                         {
1154                                 if (reg->valid == 1)
1155                                 {
1156                                         dirty = 1;
1157                                         DEBUG("examining dirty reg: %s", reg->name);
1158                                         if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1159                                                 && (reg_arch_info->mode != current_mode)
1160                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1161                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1162                                         {
1163                                                 mode_change = 1;
1164                                                 DEBUG("require mode change");
1165                                         }
1166                                 }
1167                                 else
1168                                 {
1169                                         ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1170                                         exit(-1);
1171                                 }
1172                         }
1173                 }
1174
1175                 if (dirty)
1176                 {
1177                         u32 mask = 0x0;
1178                         int num_regs = 0;
1179                         u32 regs[16];
1180
1181                         if (mode_change)
1182                         {
1183                                 u32 tmp_cpsr;
1184
1185                                 /* change processor mode (mask T bit) */
1186                                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1187                                 tmp_cpsr |= armv4_5_number_to_mode(i);
1188                                 tmp_cpsr &= ~0x20;
1189                                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1190                                 current_mode = armv4_5_number_to_mode(i);
1191                         }
1192
1193                         for (j = 0; j <= 14; j++)
1194                         {
1195                                 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1196                                 reg_arch_info = reg->arch_info;
1197
1198
1199                                 if (reg->dirty == 1)
1200                                 {
1201                                         regs[j] = buf_get_u32(reg->value, 0, 32);
1202                                         mask |= 1 << j;
1203                                         num_regs++;
1204                                         reg->dirty = 0;
1205                                         reg->valid = 1;
1206                                         DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1207                                 }
1208                         }
1209
1210                         if (mask)
1211                         {
1212                                 arm7_9->write_core_regs(target, mask, regs);
1213                         }
1214
1215                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1216                         reg_arch_info = reg->arch_info;
1217                         if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1218                         {
1219                                 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1220                                 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1221                         }
1222                 }
1223         }
1224
1225         if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1226         {
1227                 /* restore processor mode (mask T bit) */
1228                 u32 tmp_cpsr;
1229
1230                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1231                 tmp_cpsr |= armv4_5_number_to_mode(i);
1232                 tmp_cpsr &= ~0x20;
1233                 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1234                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1235         }
1236         else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1237         {
1238                 /* CPSR has been changed, full restore necessary (mask T bit) */
1239                 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1240                 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1241                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1242                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1243         }
1244
1245         /* restore PC */
1246         DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1247         arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1248         armv4_5->core_cache->reg_list[15].dirty = 0;
1249
1250         if (arm7_9->post_restore_context)
1251                 arm7_9->post_restore_context(target);
1252
1253         return ERROR_OK;
1254 }
1255
1256 int arm7_9_restart_core(struct target_s *target)
1257 {
1258         armv4_5_common_t *armv4_5 = target->arch_info;
1259         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1260         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1261
1262         /* set RESTART instruction */
1263         jtag_add_end_state(TAP_RTI);
1264         arm_jtag_set_instr(jtag_info, 0x4);
1265
1266         jtag_add_runtest(1, TAP_RTI);
1267         if ((jtag_execute_queue()) != ERROR_OK)
1268         {
1269                 exit(-1);
1270         }
1271
1272         return ERROR_OK;
1273 }
1274
1275 void arm7_9_enable_watchpoints(struct target_s *target)
1276 {
1277         watchpoint_t *watchpoint = target->watchpoints;
1278
1279         while (watchpoint)
1280         {
1281                 if (watchpoint->set == 0)
1282                         arm7_9_set_watchpoint(target, watchpoint);
1283                 watchpoint = watchpoint->next;
1284         }
1285 }
1286
1287 void arm7_9_enable_breakpoints(struct target_s *target)
1288 {
1289         breakpoint_t *breakpoint = target->breakpoints;
1290
1291         /* set any pending breakpoints */
1292         while (breakpoint)
1293         {
1294                 if (breakpoint->set == 0)
1295                         arm7_9_set_breakpoint(target, breakpoint);
1296                 breakpoint = breakpoint->next;
1297         }
1298 }
1299
1300 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1301 {
1302         breakpoint_t *breakpoint = target->breakpoints;
1303         watchpoint_t *watchpoint = target->watchpoints;
1304
1305         /* set any pending breakpoints */
1306         while (breakpoint)
1307         {
1308                 if (breakpoint->set != 0)
1309                         arm7_9_unset_breakpoint(target, breakpoint);
1310                 breakpoint = breakpoint->next;
1311         }
1312
1313         while (watchpoint)
1314         {
1315                 if (watchpoint->set != 0)
1316                         arm7_9_unset_watchpoint(target, watchpoint);
1317                 watchpoint = watchpoint->next;
1318         }
1319 }
1320
1321 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1322 {
1323         armv4_5_common_t *armv4_5 = target->arch_info;
1324         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1325         breakpoint_t *breakpoint = target->breakpoints;
1326         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1327
1328         DEBUG("");
1329
1330         if (target->state != TARGET_HALTED)
1331         {
1332                 WARNING("target not halted");
1333                 return ERROR_TARGET_NOT_HALTED;
1334         }
1335
1336         if (!debug_execution)
1337         {
1338                 target_free_all_working_areas(target);
1339         }
1340
1341         /* current = 1: continue on current pc, otherwise continue at <address> */
1342         if (!current)
1343                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1344
1345         /* the front-end may request us not to handle breakpoints */
1346         if (handle_breakpoints)
1347         {
1348                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1349                 {
1350                         DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1351                         arm7_9_unset_breakpoint(target, breakpoint);
1352
1353                         DEBUG("enable single-step");
1354                         arm7_9->enable_single_step(target);
1355
1356                         target->debug_reason = DBG_REASON_SINGLESTEP;
1357
1358                         arm7_9_restore_context(target);
1359
1360                         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1361                                 arm7_9->branch_resume(target);
1362                         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1363                         {
1364                                 arm7_9->branch_resume_thumb(target);
1365                         }
1366                         else
1367                         {
1368                                 ERROR("unhandled core state");
1369                                 exit(-1);
1370                         }
1371
1372                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1373                         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1374                         arm7_9_execute_sys_speed(target);
1375
1376                         DEBUG("disable single-step");
1377                         arm7_9->disable_single_step(target);
1378
1379                         arm7_9_debug_entry(target);
1380                         DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1381
1382                         DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1383                         arm7_9_set_breakpoint(target, breakpoint);
1384                 }
1385         }
1386
1387         /* enable any pending breakpoints and watchpoints */
1388         arm7_9_enable_breakpoints(target);
1389         arm7_9_enable_watchpoints(target);
1390
1391         arm7_9_restore_context(target);
1392
1393         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1394         {
1395                 arm7_9->branch_resume(target);
1396         }
1397         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1398         {
1399                 arm7_9->branch_resume_thumb(target);
1400         }
1401         else
1402         {
1403                 ERROR("unhandled core state");
1404                 exit(-1);
1405         }
1406
1407         /* deassert DBGACK and INTDIS */
1408         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1409         /* INTDIS only when we really resume, not during debug execution */
1410         if (!debug_execution)
1411                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1412         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1413
1414         arm7_9_restart_core(target);
1415
1416         target->debug_reason = DBG_REASON_NOTHALTED;
1417
1418         if (!debug_execution)
1419         {
1420                 /* registers are now invalid */
1421                 armv4_5_invalidate_core_regs(target);
1422                 target->state = TARGET_RUNNING;
1423                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1424         }
1425         else
1426         {
1427                 target->state = TARGET_DEBUG_RUNNING;
1428                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1429         }
1430
1431         DEBUG("target resumed");
1432
1433         return ERROR_OK;
1434 }
1435
1436 void arm7_9_enable_eice_step(target_t *target)
1437 {
1438         armv4_5_common_t *armv4_5 = target->arch_info;
1439         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1440
1441         /* setup an inverse breakpoint on the current PC
1442         * - comparator 1 matches the current address
1443         * - rangeout from comparator 1 is connected to comparator 0 rangein
1444         * - comparator 0 matches any address, as long as rangein is low */
1445         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1446         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1447         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1448         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1449         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1450         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1451         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1452         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1453         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1454 }
1455
1456 void arm7_9_disable_eice_step(target_t *target)
1457 {
1458         armv4_5_common_t *armv4_5 = target->arch_info;
1459         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1460
1461         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1462         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1463         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1464         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1465         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1466         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1467         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1468         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1469         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1470 }
1471
1472 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1473 {
1474         armv4_5_common_t *armv4_5 = target->arch_info;
1475         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1476         breakpoint_t *breakpoint = NULL;
1477
1478         if (target->state != TARGET_HALTED)
1479         {
1480                 WARNING("target not halted");
1481                 return ERROR_TARGET_NOT_HALTED;
1482         }
1483
1484         /* current = 1: continue on current pc, otherwise continue at <address> */
1485         if (!current)
1486                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1487
1488         /* the front-end may request us not to handle breakpoints */
1489         if (handle_breakpoints)
1490                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1491                         arm7_9_unset_breakpoint(target, breakpoint);
1492
1493         target->debug_reason = DBG_REASON_SINGLESTEP;
1494
1495         arm7_9_restore_context(target);
1496
1497         arm7_9->enable_single_step(target);
1498
1499         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1500         {
1501                 arm7_9->branch_resume(target);
1502         }
1503         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1504         {
1505                 arm7_9->branch_resume_thumb(target);
1506         }
1507         else
1508         {
1509                 ERROR("unhandled core state");
1510                 exit(-1);
1511         }
1512
1513         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1514
1515         arm7_9_execute_sys_speed(target);
1516         arm7_9->disable_single_step(target);
1517
1518         /* registers are now invalid */
1519         armv4_5_invalidate_core_regs(target);
1520
1521         arm7_9_debug_entry(target);
1522
1523         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1524
1525         if (breakpoint)
1526                 arm7_9_set_breakpoint(target, breakpoint);
1527
1528         DEBUG("target stepped");
1529
1530         return ERROR_OK;
1531
1532 }
1533
1534 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1535 {
1536         u32* reg_p[16];
1537         u32 value;
1538         int retval;
1539         armv4_5_common_t *armv4_5 = target->arch_info;
1540         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1541         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1542
1543         if ((num < 0) || (num > 16))
1544                 return ERROR_INVALID_ARGUMENTS;
1545
1546         if ((mode != ARMV4_5_MODE_ANY)
1547                         && (mode != armv4_5->core_mode)
1548                         && (reg_mode != ARMV4_5_MODE_ANY))
1549         {
1550                 u32 tmp_cpsr;
1551
1552                 /* change processor mode (mask T bit) */
1553                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1554                 tmp_cpsr |= mode;
1555                 tmp_cpsr &= ~0x20;
1556                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1557         }
1558
1559         if ((num >= 0) && (num <= 15))
1560         {
1561                 /* read a normal core register */
1562                 reg_p[num] = &value;
1563
1564                 arm7_9->read_core_regs(target, 1 << num, reg_p);
1565         }
1566         else
1567         {
1568                 /* read a program status register
1569                  * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1570                  */
1571                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1572                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1573
1574                 arm7_9->read_xpsr(target, &value, spsr);
1575         }
1576
1577         if ((retval = jtag_execute_queue()) != ERROR_OK)
1578         {
1579                 ERROR("JTAG failure");
1580                 exit(-1);
1581         }
1582
1583         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1584         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1585         buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1586
1587         if ((mode != ARMV4_5_MODE_ANY)
1588                         && (mode != armv4_5->core_mode)
1589                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1590                 /* restore processor mode (mask T bit) */
1591                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1592         }
1593
1594         return ERROR_OK;
1595
1596 }
1597
1598 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1599 {
1600         u32 reg[16];
1601         int retval;
1602         armv4_5_common_t *armv4_5 = target->arch_info;
1603         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1604         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1605
1606         if ((num < 0) || (num > 16))
1607                 return ERROR_INVALID_ARGUMENTS;
1608
1609         if ((mode != ARMV4_5_MODE_ANY)
1610                         && (mode != armv4_5->core_mode)
1611                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1612                 u32 tmp_cpsr;
1613
1614                 /* change processor mode (mask T bit) */
1615                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1616                 tmp_cpsr |= mode;
1617                 tmp_cpsr &= ~0x20;
1618                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1619         }
1620
1621         if ((num >= 0) && (num <= 15))
1622         {
1623                 /* write a normal core register */
1624                 reg[num] = value;
1625
1626                 arm7_9->write_core_regs(target, 1 << num, reg);
1627         }
1628         else
1629         {
1630                 /* write a program status register
1631                 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1632                 */
1633                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1634                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1635
1636                 /* if we're writing the CPSR, mask the T bit */
1637                 if (!spsr)
1638                         value &= ~0x20;
1639
1640                 arm7_9->write_xpsr(target, value, spsr);
1641         }
1642
1643         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1644         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1645
1646         if ((mode != ARMV4_5_MODE_ANY)
1647                         && (mode != armv4_5->core_mode)
1648                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1649                 /* restore processor mode (mask T bit) */
1650                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1651         }
1652
1653         if ((retval = jtag_execute_queue()) != ERROR_OK)
1654         {
1655                 ERROR("JTAG failure");
1656                 exit(-1);
1657         }
1658
1659         return ERROR_OK;
1660
1661 }
1662
1663 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1664 {
1665         armv4_5_common_t *armv4_5 = target->arch_info;
1666         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1667
1668         u32 reg[16];
1669         int num_accesses = 0;
1670         int thisrun_accesses;
1671         int i;
1672         u32 cpsr;
1673         int retval;
1674         int last_reg = 0;
1675
1676         DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1677
1678         if (target->state != TARGET_HALTED)
1679         {
1680                 WARNING("target not halted");
1681                 return ERROR_TARGET_NOT_HALTED;
1682         }
1683
1684         /* sanitize arguments */
1685         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1686                 return ERROR_INVALID_ARGUMENTS;
1687
1688         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1689                 return ERROR_TARGET_UNALIGNED_ACCESS;
1690
1691         /* load the base register with the address of the first word */
1692         reg[0] = address;
1693         arm7_9->write_core_regs(target, 0x1, reg);
1694
1695         switch (size)
1696         {
1697                 case 4:
1698                         while (num_accesses < count)
1699                         {
1700                                 u32 reg_list;
1701                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1702                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1703
1704                                 if (last_reg <= thisrun_accesses)
1705                                         last_reg = thisrun_accesses;
1706
1707                                 arm7_9->load_word_regs(target, reg_list);
1708
1709                                 /* fast memory reads are only safe when the target is running
1710                                  * from a sufficiently high clock (32 kHz is usually too slow)
1711                                  */
1712                                 if (arm7_9->fast_memory_access)
1713                                         arm7_9_execute_fast_sys_speed(target);
1714                                 else
1715                                         arm7_9_execute_sys_speed(target);
1716
1717                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1718
1719                                 /* advance buffer, count number of accesses */
1720                                 buffer += thisrun_accesses * 4;
1721                                 num_accesses += thisrun_accesses;
1722                         }
1723                         break;
1724                 case 2:
1725                         while (num_accesses < count)
1726                         {
1727                                 u32 reg_list;
1728                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1729                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1730
1731                                 for (i = 1; i <= thisrun_accesses; i++)
1732                                 {
1733                                         if (i > last_reg)
1734                                                 last_reg = i;
1735                                         arm7_9->load_hword_reg(target, i);
1736                                         /* fast memory reads are only safe when the target is running
1737                                          * from a sufficiently high clock (32 kHz is usually too slow)
1738                                          */
1739                                         if (arm7_9->fast_memory_access)
1740                                                 arm7_9_execute_fast_sys_speed(target);
1741                                         else
1742                                                 arm7_9_execute_sys_speed(target);
1743                                 }
1744
1745                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1746
1747                                 /* advance buffer, count number of accesses */
1748                                 buffer += thisrun_accesses * 2;
1749                                 num_accesses += thisrun_accesses;
1750                         }
1751                         break;
1752                 case 1:
1753                         while (num_accesses < count)
1754                         {
1755                                 u32 reg_list;
1756                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1757                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1758
1759                                 for (i = 1; i <= thisrun_accesses; i++)
1760                                 {
1761                                         if (i > last_reg)
1762                                                 last_reg = i;
1763                                         arm7_9->load_byte_reg(target, i);
1764                                         /* fast memory reads are only safe when the target is running
1765                                          * from a sufficiently high clock (32 kHz is usually too slow)
1766                                          */
1767                                         if (arm7_9->fast_memory_access)
1768                                                 arm7_9_execute_fast_sys_speed(target);
1769                                         else
1770                                                 arm7_9_execute_sys_speed(target);
1771                                 }
1772
1773                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1774
1775                                 /* advance buffer, count number of accesses */
1776                                 buffer += thisrun_accesses * 1;
1777                                 num_accesses += thisrun_accesses;
1778                         }
1779                         break;
1780                 default:
1781                         ERROR("BUG: we shouldn't get here");
1782                         exit(-1);
1783                         break;
1784         }
1785
1786         for (i=0; i<=last_reg; i++)
1787                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1788
1789         arm7_9->read_xpsr(target, &cpsr, 0);
1790         if ((retval = jtag_execute_queue()) != ERROR_OK)
1791         {
1792                 ERROR("JTAG error while reading cpsr");
1793                 exit(-1);
1794         }
1795
1796         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1797         {
1798                 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1799
1800                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1801
1802                 return ERROR_TARGET_DATA_ABORT;
1803         }
1804
1805         return ERROR_OK;
1806 }
1807
1808 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1809 {
1810         armv4_5_common_t *armv4_5 = target->arch_info;
1811         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1812         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1813
1814         u32 reg[16];
1815         int num_accesses = 0;
1816         int thisrun_accesses;
1817         int i;
1818         u32 cpsr;
1819         int retval;
1820         int last_reg = 0;
1821
1822         DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1823
1824         if (target->state != TARGET_HALTED)
1825         {
1826                 WARNING("target not halted");
1827                 return ERROR_TARGET_NOT_HALTED;
1828         }
1829
1830         /* sanitize arguments */
1831         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1832                 return ERROR_INVALID_ARGUMENTS;
1833
1834         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1835                 return ERROR_TARGET_UNALIGNED_ACCESS;
1836
1837         /* load the base register with the address of the first word */
1838         reg[0] = address;
1839         arm7_9->write_core_regs(target, 0x1, reg);
1840
1841         /* Clear DBGACK, to make sure memory fetches work as expected */
1842         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1843         embeddedice_store_reg(dbg_ctrl);
1844
1845         switch (size)
1846         {
1847                 case 4:
1848                         while (num_accesses < count)
1849                         {
1850                                 u32 reg_list;
1851                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1852                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1853
1854                                 for (i = 1; i <= thisrun_accesses; i++)
1855                                 {
1856                                         if (i > last_reg)
1857                                                 last_reg = i;
1858                                         reg[i] = target_buffer_get_u32(target, buffer);
1859                                         buffer += 4;
1860                                 }
1861
1862                                 arm7_9->write_core_regs(target, reg_list, reg);
1863
1864                                 arm7_9->store_word_regs(target, reg_list);
1865
1866                                 /* fast memory writes are only safe when the target is running
1867                                  * from a sufficiently high clock (32 kHz is usually too slow)
1868                                  */
1869                                 if (arm7_9->fast_memory_access)
1870                                         arm7_9_execute_fast_sys_speed(target);
1871                                 else
1872                                         arm7_9_execute_sys_speed(target);
1873
1874                                 num_accesses += thisrun_accesses;
1875                         }
1876                         break;
1877                 case 2:
1878                         while (num_accesses < count)
1879                         {
1880                                 u32 reg_list;
1881                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1882                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1883
1884                                 for (i = 1; i <= thisrun_accesses; i++)
1885                                 {
1886                                         if (i > last_reg)
1887                                                 last_reg = i;
1888                                         reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1889                                         buffer += 2;
1890                                 }
1891
1892                                 arm7_9->write_core_regs(target, reg_list, reg);
1893
1894                                 for (i = 1; i <= thisrun_accesses; i++)
1895                                 {
1896                                         arm7_9->store_hword_reg(target, i);
1897
1898                                         /* fast memory writes are only safe when the target is running
1899                                          * from a sufficiently high clock (32 kHz is usually too slow)
1900                                          */
1901                                         if (arm7_9->fast_memory_access)
1902                                                 arm7_9_execute_fast_sys_speed(target);
1903                                         else
1904                                                 arm7_9_execute_sys_speed(target);
1905                                 }
1906
1907                                 num_accesses += thisrun_accesses;
1908                         }
1909                         break;
1910                 case 1:
1911                         while (num_accesses < count)
1912                         {
1913                                 u32 reg_list;
1914                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1915                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1916
1917                                 for (i = 1; i <= thisrun_accesses; i++)
1918                                 {
1919                                         if (i > last_reg)
1920                                                 last_reg = i;
1921                                         reg[i] = *buffer++ & 0xff;
1922                                 }
1923
1924                                 arm7_9->write_core_regs(target, reg_list, reg);
1925
1926                                 for (i = 1; i <= thisrun_accesses; i++)
1927                                 {
1928                                         arm7_9->store_byte_reg(target, i);
1929                                         /* fast memory writes are only safe when the target is running
1930                                          * from a sufficiently high clock (32 kHz is usually too slow)
1931                                          */
1932                                         if (arm7_9->fast_memory_access)
1933                                                 arm7_9_execute_fast_sys_speed(target);
1934                                         else
1935                                                 arm7_9_execute_sys_speed(target);
1936                                 }
1937
1938                                 num_accesses += thisrun_accesses;
1939                         }
1940                         break;
1941                 default:
1942                         ERROR("BUG: we shouldn't get here");
1943                         exit(-1);
1944                         break;
1945         }
1946
1947         /* Re-Set DBGACK */
1948         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1949         embeddedice_store_reg(dbg_ctrl);
1950
1951         for (i=0; i<=last_reg; i++)
1952                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1953
1954         arm7_9->read_xpsr(target, &cpsr, 0);
1955         if ((retval = jtag_execute_queue()) != ERROR_OK)
1956         {
1957                 ERROR("JTAG error while reading cpsr");
1958                 exit(-1);
1959         }
1960
1961         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1962         {
1963                 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1964
1965                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1966
1967                 return ERROR_TARGET_DATA_ABORT;
1968         }
1969
1970         return ERROR_OK;
1971 }
1972
1973 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
1974 {
1975         armv4_5_common_t *armv4_5 = target->arch_info;
1976         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1977         enum armv4_5_state core_state = armv4_5->core_state;
1978         u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
1979         u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
1980         u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1981         int i;
1982
1983         u32 dcc_code[] =
1984         {
1985                 /* MRC      TST         BNE         MRC         STR         B */
1986                 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1987         };
1988
1989         if (!arm7_9->dcc_downloads)
1990                 return target->type->write_memory(target, address, 4, count, buffer);
1991
1992         /* regrab previously allocated working_area, or allocate a new one */
1993         if (!arm7_9->dcc_working_area)
1994         {
1995                 u8 dcc_code_buf[6 * 4];
1996
1997                 /* make sure we have a working area */
1998                 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
1999                 {
2000                         INFO("no working area available, falling back to memory writes");
2001                         return target->type->write_memory(target, address, 4, count, buffer);
2002                 }
2003
2004                 /* copy target instructions to target endianness */
2005                 for (i = 0; i < 6; i++)
2006                 {
2007                         target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2008                 }
2009
2010                 /* write DCC code to working area */
2011                 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2012         }
2013
2014         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2015         armv4_5->core_cache->reg_list[0].valid = 1;
2016         armv4_5->core_cache->reg_list[0].dirty = 1;
2017         armv4_5->core_state = ARMV4_5_STATE_ARM;
2018
2019         arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2020
2021         for (i = 0; i < count; i++)
2022         {
2023                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
2024                 buffer += 4;
2025         }
2026
2027         target->type->halt(target);
2028
2029         while (target->state != TARGET_HALTED)
2030                 target->type->poll(target);
2031
2032         /* restore target state */
2033         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2034         armv4_5->core_cache->reg_list[0].valid = 1;
2035         armv4_5->core_cache->reg_list[0].dirty = 1;
2036         buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2037         armv4_5->core_cache->reg_list[1].valid = 1;
2038         armv4_5->core_cache->reg_list[1].dirty = 1;
2039         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2040         armv4_5->core_cache->reg_list[15].valid = 1;
2041         armv4_5->core_cache->reg_list[15].dirty = 1;
2042         armv4_5->core_state = core_state;
2043
2044         return ERROR_OK;
2045 }
2046
2047 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2048 {
2049         command_t *arm7_9_cmd;
2050
2051         arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2052
2053         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2054         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2055
2056         register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2057
2058         register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2059         register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2060         register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2061                 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2062         register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2063                  COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2064         register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2065                  COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2066         register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2067                 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2068
2069         armv4_5_register_commands(cmd_ctx);
2070
2071         return ERROR_OK;
2072 }
2073
2074 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2075 {
2076         u32 value;
2077         int spsr;
2078         int retval;
2079         target_t *target = get_current_target(cmd_ctx);
2080         armv4_5_common_t *armv4_5;
2081         arm7_9_common_t *arm7_9;
2082
2083         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2084         {
2085                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2086                 return ERROR_OK;
2087         }
2088
2089         if (target->state != TARGET_HALTED)
2090         {
2091                 command_print(cmd_ctx, "can't write registers while running");
2092                 return ERROR_OK;
2093         }
2094
2095         if (argc < 2)
2096         {
2097                 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2098                 return ERROR_OK;
2099         }
2100
2101         value = strtoul(args[0], NULL, 0);
2102         spsr = strtol(args[1], NULL, 0);
2103
2104         /* if we're writing the CPSR, mask the T bit */
2105         if (!spsr)
2106                 value &= ~0x20;
2107
2108         arm7_9->write_xpsr(target, value, spsr);
2109         if ((retval = jtag_execute_queue()) != ERROR_OK)
2110         {
2111                 ERROR("JTAG error while writing to xpsr");
2112                 exit(-1);
2113         }
2114
2115         return ERROR_OK;
2116 }
2117
2118 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2119 {
2120         u32 value;
2121         int rotate;
2122         int spsr;
2123         int retval;
2124         target_t *target = get_current_target(cmd_ctx);
2125         armv4_5_common_t *armv4_5;
2126         arm7_9_common_t *arm7_9;
2127
2128         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2129         {
2130                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2131                 return ERROR_OK;
2132         }
2133
2134         if (target->state != TARGET_HALTED)
2135         {
2136                 command_print(cmd_ctx, "can't write registers while running");
2137                 return ERROR_OK;
2138         }
2139
2140         if (argc < 3)
2141         {
2142                 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2143                 return ERROR_OK;
2144         }
2145
2146         value = strtoul(args[0], NULL, 0);
2147         rotate = strtol(args[1], NULL, 0);
2148         spsr = strtol(args[2], NULL, 0);
2149
2150         arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2151         if ((retval = jtag_execute_queue()) != ERROR_OK)
2152         {
2153                 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2154                 exit(-1);
2155         }
2156
2157         return ERROR_OK;
2158 }
2159
2160 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2161 {
2162         u32 value;
2163         u32 mode;
2164         int num;
2165         target_t *target = get_current_target(cmd_ctx);
2166         armv4_5_common_t *armv4_5;
2167         arm7_9_common_t *arm7_9;
2168
2169         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2170         {
2171                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2172                 return ERROR_OK;
2173         }
2174
2175         if (target->state != TARGET_HALTED)
2176         {
2177                 command_print(cmd_ctx, "can't write registers while running");
2178                 return ERROR_OK;
2179         }
2180
2181         if (argc < 3)
2182         {
2183                 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2184                 return ERROR_OK;
2185         }
2186
2187         num = strtol(args[0], NULL, 0);
2188         mode = strtoul(args[1], NULL, 0);
2189         value = strtoul(args[2], NULL, 0);
2190
2191         arm7_9_write_core_reg(target, num, mode, value);
2192
2193         return ERROR_OK;
2194 }
2195
2196 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2197 {
2198         target_t *target = get_current_target(cmd_ctx);
2199         armv4_5_common_t *armv4_5;
2200         arm7_9_common_t *arm7_9;
2201
2202         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2203         {
2204                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2205                 return ERROR_OK;
2206         }
2207
2208         if (argc == 0)
2209         {
2210                 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2211                 return ERROR_OK;
2212         }
2213
2214         if (strcmp("enable", args[0]) == 0)
2215         {
2216                 if (arm7_9->sw_bkpts_use_wp)
2217                 {
2218                         arm7_9_enable_sw_bkpts(target);
2219                 }
2220                 else
2221                 {
2222                         arm7_9->sw_bkpts_enabled = 1;
2223                 }
2224         }
2225         else if (strcmp("disable", args[0]) == 0)
2226         {
2227                 if (arm7_9->sw_bkpts_use_wp)
2228                 {
2229                         arm7_9_disable_sw_bkpts(target);
2230                 }
2231                 else
2232                 {
2233                         arm7_9->sw_bkpts_enabled = 0;
2234                 }
2235         }
2236         else
2237         {
2238                 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2239         }
2240
2241         command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2242
2243         return ERROR_OK;
2244 }
2245
2246 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2247 {
2248         target_t *target = get_current_target(cmd_ctx);
2249         armv4_5_common_t *armv4_5;
2250         arm7_9_common_t *arm7_9;
2251
2252         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2253         {
2254                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2255                 return ERROR_OK;
2256         }
2257
2258         if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2259         {
2260                 arm7_9->force_hw_bkpts = 1;
2261                 if (arm7_9->sw_bkpts_use_wp)
2262                 {
2263                         arm7_9_disable_sw_bkpts(target);
2264                 }
2265         }
2266         else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2267         {
2268                 arm7_9->force_hw_bkpts = 0;
2269         }
2270         else
2271         {
2272                 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2273         }
2274
2275         command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2276
2277         return ERROR_OK;
2278 }
2279
2280 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2281 {
2282         target_t *target = get_current_target(cmd_ctx);
2283         armv4_5_common_t *armv4_5;
2284         arm7_9_common_t *arm7_9;
2285
2286         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2287         {
2288                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2289                 return ERROR_OK;
2290         }
2291
2292         if (argc > 0)
2293         {
2294                 if (strcmp("enable", args[0]) == 0)
2295                 {
2296                         arm7_9->use_dbgrq = 1;
2297                 }
2298                 else if (strcmp("disable", args[0]) == 0)
2299                 {
2300                         arm7_9->use_dbgrq = 0;
2301                 }
2302                 else
2303                 {
2304                         command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2305                 }
2306         }
2307
2308         command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2309
2310         return ERROR_OK;
2311 }
2312
2313 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2314 {
2315         target_t *target = get_current_target(cmd_ctx);
2316         armv4_5_common_t *armv4_5;
2317         arm7_9_common_t *arm7_9;
2318
2319         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2320         {
2321                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2322                 return ERROR_OK;
2323         }
2324
2325         if (argc > 0)
2326         {
2327                 if (strcmp("enable", args[0]) == 0)
2328                 {
2329                         arm7_9->fast_memory_access = 1;
2330                 }
2331                 else if (strcmp("disable", args[0]) == 0)
2332                 {
2333                         arm7_9->fast_memory_access = 0;
2334                 }
2335                 else
2336                 {
2337                         command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2338                 }
2339         }
2340
2341         command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2342
2343         return ERROR_OK;
2344 }
2345
2346 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2347 {
2348         target_t *target = get_current_target(cmd_ctx);
2349         armv4_5_common_t *armv4_5;
2350         arm7_9_common_t *arm7_9;
2351
2352         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2353         {
2354                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2355                 return ERROR_OK;
2356         }
2357
2358         if (argc > 0)
2359         {
2360                 if (strcmp("enable", args[0]) == 0)
2361                 {
2362                         arm7_9->dcc_downloads = 1;
2363                 }
2364                 else if (strcmp("disable", args[0]) == 0)
2365                 {
2366                         arm7_9->dcc_downloads = 0;
2367                 }
2368                 else
2369                 {
2370                         command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2371                 }
2372         }
2373
2374         command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2375
2376         return ERROR_OK;
2377 }
2378
2379 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2380 {
2381         armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2382
2383         arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2384
2385         arm_jtag_setup_connection(&arm7_9->jtag_info);
2386         arm7_9->wp_available = 2;
2387         arm7_9->wp0_used = 0;
2388         arm7_9->wp1_used = 0;
2389         arm7_9->force_hw_bkpts = 0;
2390         arm7_9->use_dbgrq = 0;
2391         arm7_9->has_etm = 0;
2392
2393         arm7_9->reinit_embeddedice = 0;
2394
2395         arm7_9->dcc_working_area = NULL;
2396
2397         arm7_9->fast_memory_access = 0;
2398         arm7_9->dcc_downloads = 0;
2399
2400         jtag_register_event_callback(arm7_9_jtag_callback, target);
2401
2402         armv4_5->arch_info = arm7_9;
2403         armv4_5->read_core_reg = arm7_9_read_core_reg;
2404         armv4_5->write_core_reg = arm7_9_write_core_reg;
2405         armv4_5->full_context = arm7_9_full_context;
2406
2407         armv4_5_init_arch_info(target, armv4_5);
2408
2409         return ERROR_OK;
2410 }