git.gag.com Git - fw/openocd/blob - src/target/arm7_9_common.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "embeddedice.h"
  27 #include "target.h"
  28 #include "target_request.h"
  29 #include "armv4_5.h"
  30 #include "arm_jtag.h"
  31 #include "jtag.h"
  32 #include "log.h"
  33 #include "arm7_9_common.h"
  34 #include "breakpoints.h"
  35
  36 #include <stdlib.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39
  40 #include <sys/types.h>
  41 #include <sys/stat.h>
  42 #include <sys/time.h>
  43 #include <errno.h>
  44
  45 int arm7_9_debug_entry(target_t *target);
  46 int arm7_9_enable_sw_bkpts(struct target_s *target);
  47
  48 /* command handler forward declarations */
  49 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  55 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  56 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  57 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  58 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  59
  60 int arm7_9_reinit_embeddedice(target_t *target)
  61 {
  62         armv4_5_common_t *armv4_5 = target->arch_info;
  63         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  64
  65         breakpoint_t *breakpoint = target->breakpoints;
  66
  67         arm7_9->wp_available = 2;
  68         arm7_9->wp0_used = 0;
  69         arm7_9->wp1_used = 0;
  70
  71         /* mark all hardware breakpoints as unset */
  72         while (breakpoint)
  73         {
  74                 if (breakpoint->type == BKPT_HARD)
  75                 {
  76                         breakpoint->set = 0;
  77                 }
  78                 breakpoint = breakpoint->next;
  79         }
  80
  81         if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
  82         {
  83                 arm7_9->sw_bkpts_enabled = 0;
  84                 arm7_9_enable_sw_bkpts(target);
  85         }
  86
  87         arm7_9->reinit_embeddedice = 0;
  88
  89         return ERROR_OK;
  90 }
  91
  92 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
  93 {
  94         target_t *target = priv;
  95         armv4_5_common_t *armv4_5 = target->arch_info;
  96         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  97
  98         /* a test-logic reset occured
  99          * the EmbeddedICE registers have been reset
 100          * hardware breakpoints have been cleared
 101          */
 102         if (event == JTAG_TRST_ASSERTED)
 103         {
 104                 arm7_9->reinit_embeddedice = 1;
 105         }
 106
 107         return ERROR_OK;
 108 }
 109
 110 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
 111 {
 112         armv4_5_common_t *armv4_5 = target->arch_info;
 113         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 114
 115         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 116         {
 117                 return -1;
 118         }
 119
 120         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 121         {
 122                 return -1;
 123         }
 124
 125         *armv4_5_p = armv4_5;
 126         *arm7_9_p = arm7_9;
 127
 128         return ERROR_OK;
 129 }
 130
 131 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 132 {
 133         armv4_5_common_t *armv4_5 = target->arch_info;
 134         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 135
 136         if (target->state != TARGET_HALTED)
 137         {
 138                 WARNING("target not halted");
 139                 return ERROR_TARGET_NOT_HALTED;
 140         }
 141
 142         if (arm7_9->force_hw_bkpts)
 143                 breakpoint->type = BKPT_HARD;
 144
 145         if (breakpoint->set)
 146         {
 147                 WARNING("breakpoint already set");
 148                 return ERROR_OK;
 149         }
 150
 151         if (breakpoint->type == BKPT_HARD)
 152         {
 153                 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
 154                 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 155                 if (!arm7_9->wp0_used)
 156                 {
 157                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
 158                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 159                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
 160                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 161                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 162
 163                         jtag_execute_queue();
 164                         arm7_9->wp0_used = 1;
 165                         breakpoint->set = 1;
 166                 }
 167                 else if (!arm7_9->wp1_used)
 168                 {
 169                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
 170                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 171                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
 172                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 173                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 174
 175                         jtag_execute_queue();
 176                         arm7_9->wp1_used = 1;
 177                         breakpoint->set = 2;
 178                 }
 179                 else
 180                 {
 181                         ERROR("BUG: no hardware comparator available");
 182                         return ERROR_OK;
 183                 }
 184         }
 185         else if (breakpoint->type == BKPT_SOFT)
 186         {
 187                 if (breakpoint->length == 4)
 188                 {
 189                         u32 verify = 0xffffffff;
 190                         /* keep the original instruction in target endianness */
 191                         target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 192                         /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 193                         target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
 194
 195                         target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
 196                         if (verify != arm7_9->arm_bkpt)
 197                         {
 198                                 ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
 199                                 return ERROR_OK;
 200                         }
 201                 }
 202                 else
 203                 {
 204                         u16 verify = 0xffff;
 205                         /* keep the original instruction in target endianness */
 206                         target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 207                         /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
 208                         target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
 209
 210                         target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
 211                         if (verify != arm7_9->thumb_bkpt)
 212                         {
 213                                 ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
 214                                 return ERROR_OK;
 215                         }
 216                 }
 217                 breakpoint->set = 1;
 218         }
 219
 220         return ERROR_OK;
 221
 222 }
 223
 224 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 225 {
 226         armv4_5_common_t *armv4_5 = target->arch_info;
 227         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 228
 229         if (target->state != TARGET_HALTED)
 230         {
 231                 WARNING("target not halted");
 232                 return ERROR_TARGET_NOT_HALTED;
 233         }
 234
 235         if (!breakpoint->set)
 236         {
 237                 WARNING("breakpoint not set");
 238                 return ERROR_OK;
 239         }
 240
 241         if (breakpoint->type == BKPT_HARD)
 242         {
 243                 if (breakpoint->set == 1)
 244                 {
 245                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 246                         jtag_execute_queue();
 247                         arm7_9->wp0_used = 0;
 248                 }
 249                 else if (breakpoint->set == 2)
 250                 {
 251                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 252                         jtag_execute_queue();
 253                         arm7_9->wp1_used = 0;
 254                 }
 255                 breakpoint->set = 0;
 256         }
 257         else
 258         {
 259                 /* restore original instruction (kept in target endianness) */
 260                 if (breakpoint->length == 4)
 261                 {
 262                         u32 current_instr;
 263                         /* check that user program as not modified breakpoint instruction */
 264                         target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
 265                         if (current_instr==arm7_9->arm_bkpt)
 266                                 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 267                 }
 268                 else
 269                 {
 270                         u16 current_instr;
 271                         /* check that user program as not modified breakpoint instruction */
 272                         target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
 273                         if (current_instr==arm7_9->thumb_bkpt)
 274                                 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 275                 }
 276                 breakpoint->set = 0;
 277         }
 278
 279         return ERROR_OK;
 280 }
 281
 282 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 283 {
 284         armv4_5_common_t *armv4_5 = target->arch_info;
 285         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 286
 287         if (target->state != TARGET_HALTED)
 288         {
 289                 WARNING("target not halted");
 290                 return ERROR_TARGET_NOT_HALTED;
 291         }
 292
 293         if (arm7_9->force_hw_bkpts)
 294         {
 295                 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
 296                 breakpoint->type = BKPT_HARD;
 297         }
 298
 299         if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
 300         {
 301                 INFO("sw breakpoint requested, but software breakpoints not enabled");
 302                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 303         }
 304
 305         if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
 306         {
 307                 INFO("no watchpoint unit available for hardware breakpoint");
 308                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 309         }
 310
 311         if ((breakpoint->length != 2) && (breakpoint->length != 4))
 312         {
 313                 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 314                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 315         }
 316
 317         if (breakpoint->type == BKPT_HARD)
 318                 arm7_9->wp_available--;
 319
 320         return ERROR_OK;
 321 }
 322
 323 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 324 {
 325         armv4_5_common_t *armv4_5 = target->arch_info;
 326         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 327
 328         if (target->state != TARGET_HALTED)
 329         {
 330                 WARNING("target not halted");
 331                 return ERROR_TARGET_NOT_HALTED;
 332         }
 333
 334         if (breakpoint->set)
 335         {
 336                 arm7_9_unset_breakpoint(target, breakpoint);
 337         }
 338
 339         if (breakpoint->type == BKPT_HARD)
 340                 arm7_9->wp_available++;
 341
 342         return ERROR_OK;
 343 }
 344
 345 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 346 {
 347         armv4_5_common_t *armv4_5 = target->arch_info;
 348         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 349         int rw_mask = 1;
 350         u32 mask;
 351
 352         mask = watchpoint->length - 1;
 353
 354         if (target->state != TARGET_HALTED)
 355         {
 356                 WARNING("target not halted");
 357                 return ERROR_TARGET_NOT_HALTED;
 358         }
 359
 360         if (watchpoint->rw == WPT_ACCESS)
 361                 rw_mask = 0;
 362         else
 363                 rw_mask = 1;
 364
 365         if (!arm7_9->wp0_used)
 366         {
 367                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
 368                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 369                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
 370                 if( watchpoint->mask != 0xffffffffu )
 371                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
 372                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 373                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 374
 375                 jtag_execute_queue();
 376                 watchpoint->set = 1;
 377                 arm7_9->wp0_used = 2;
 378         }
 379         else if (!arm7_9->wp1_used)
 380         {
 381                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
 382                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 383                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
 384                 if( watchpoint->mask != 0xffffffffu )
 385                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
 386                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 387                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 388
 389                 jtag_execute_queue();
 390                 watchpoint->set = 2;
 391                 arm7_9->wp1_used = 2;
 392         }
 393         else
 394         {
 395                 ERROR("BUG: no hardware comparator available");
 396                 return ERROR_OK;
 397         }
 398
 399         return ERROR_OK;
 400 }
 401
 402 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 403 {
 404         armv4_5_common_t *armv4_5 = target->arch_info;
 405         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 406
 407         if (target->state != TARGET_HALTED)
 408         {
 409                 WARNING("target not halted");
 410                 return ERROR_TARGET_NOT_HALTED;
 411         }
 412
 413         if (!watchpoint->set)
 414         {
 415                 WARNING("breakpoint not set");
 416                 return ERROR_OK;
 417         }
 418
 419         if (watchpoint->set == 1)
 420         {
 421                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 422                 jtag_execute_queue();
 423                 arm7_9->wp0_used = 0;
 424         }
 425         else if (watchpoint->set == 2)
 426         {
 427                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 428                 jtag_execute_queue();
 429                 arm7_9->wp1_used = 0;
 430         }
 431         watchpoint->set = 0;
 432
 433         return ERROR_OK;
 434 }
 435
 436 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 437 {
 438         armv4_5_common_t *armv4_5 = target->arch_info;
 439         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 440
 441         if (target->state != TARGET_HALTED)
 442         {
 443                 WARNING("target not halted");
 444                 return ERROR_TARGET_NOT_HALTED;
 445         }
 446
 447         if (arm7_9->wp_available < 1)
 448         {
 449                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 450         }
 451
 452         if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
 453         {
 454                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 455         }
 456
 457         arm7_9->wp_available--;
 458
 459         return ERROR_OK;
 460 }
 461
 462 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 463 {
 464         armv4_5_common_t *armv4_5 = target->arch_info;
 465         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 466
 467         if (target->state != TARGET_HALTED)
 468         {
 469                 WARNING("target not halted");
 470                 return ERROR_TARGET_NOT_HALTED;
 471         }
 472
 473         if (watchpoint->set)
 474         {
 475                 arm7_9_unset_watchpoint(target, watchpoint);
 476         }
 477
 478         arm7_9->wp_available++;
 479
 480         return ERROR_OK;
 481 }
 482
 483 int arm7_9_enable_sw_bkpts(struct target_s *target)
 484 {
 485         armv4_5_common_t *armv4_5 = target->arch_info;
 486         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 487         int retval;
 488
 489         if (arm7_9->sw_bkpts_enabled)
 490                 return ERROR_OK;
 491
 492         if (arm7_9->wp_available < 1)
 493         {
 494                 WARNING("can't enable sw breakpoints with no watchpoint unit available");
 495                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 496         }
 497         arm7_9->wp_available--;
 498
 499         if (!arm7_9->wp0_used)
 500         {
 501                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
 502                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
 503                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
 504                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 505                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 506                 arm7_9->sw_bkpts_enabled = 1;
 507                 arm7_9->wp0_used = 3;
 508         }
 509         else if (!arm7_9->wp1_used)
 510         {
 511                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
 512                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
 513                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
 514                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 515                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 516                 arm7_9->sw_bkpts_enabled = 2;
 517                 arm7_9->wp1_used = 3;
 518         }
 519         else
 520         {
 521                 ERROR("BUG: both watchpoints used, but wp_available >= 1");
 522                 exit(-1);
 523         }
 524
 525         if ((retval = jtag_execute_queue()) != ERROR_OK)
 526         {
 527                 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
 528                 exit(-1);
 529         };
 530
 531         return ERROR_OK;
 532 }
 533
 534 int arm7_9_disable_sw_bkpts(struct target_s *target)
 535 {
 536         armv4_5_common_t *armv4_5 = target->arch_info;
 537         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 538
 539         if (!arm7_9->sw_bkpts_enabled)
 540                 return ERROR_OK;
 541
 542         if (arm7_9->sw_bkpts_enabled == 1)
 543         {
 544                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 545                 arm7_9->sw_bkpts_enabled = 0;
 546                 arm7_9->wp0_used = 0;
 547                 arm7_9->wp_available++;
 548         }
 549         else if (arm7_9->sw_bkpts_enabled == 2)
 550         {
 551                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 552                 arm7_9->sw_bkpts_enabled = 0;
 553                 arm7_9->wp1_used = 0;
 554                 arm7_9->wp_available++;
 555         }
 556
 557         return ERROR_OK;
 558 }
 559
 560 int arm7_9_execute_sys_speed(struct target_s *target)
 561 {
 562         int timeout;
 563         int retval;
 564
 565         armv4_5_common_t *armv4_5 = target->arch_info;
 566         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 567         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 568         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 569
 570         /* set RESTART instruction */
 571         jtag_add_end_state(TAP_RTI);
 572         arm_jtag_set_instr(jtag_info, 0x4, NULL);
 573
 574         for (timeout=0; timeout<50; timeout++)
 575         {
 576                 /* read debug status register */
 577                 embeddedice_read_reg(dbg_stat);
 578                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 579                         return retval;
 580                 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 581                                    && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 582                         break;
 583                 usleep(100000);
 584         }
 585         if (timeout == 50)
 586         {
 587                 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 588                 return ERROR_TARGET_TIMEOUT;
 589         }
 590
 591         return ERROR_OK;
 592 }
 593
 594 int arm7_9_execute_fast_sys_speed(struct target_s *target)
 595 {
 596         static int set=0;
 597         static u8 check_value[4], check_mask[4];
 598
 599         armv4_5_common_t *armv4_5 = target->arch_info;
 600         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 601         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 602         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 603
 604         /* set RESTART instruction */
 605         jtag_add_end_state(TAP_RTI);
 606         arm_jtag_set_instr(jtag_info, 0x4, NULL);
 607
 608         if (!set)
 609         {
 610                 /* check for DBGACK and SYSCOMP set (others don't care) */
 611
 612                 /* NB! These are constants that must be available until after next jtag_execute() and
 613                    we evaluate the values upon first execution in lieu of setting up these constants
 614                    during early setup.
 615                 */
 616                 buf_set_u32(check_value, 0, 32, 0x9);
 617                 buf_set_u32(check_mask, 0, 32, 0x9);
 618                 set=1;
 619         }
 620
 621         /* read debug status register */
 622         embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
 623
 624         return ERROR_OK;
 625 }
 626
 627 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
 628 {
 629         armv4_5_common_t *armv4_5 = target->arch_info;
 630         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 631         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 632         u32 *data;
 633         int i;
 634
 635         data = malloc(size * (sizeof(u32)));
 636
 637         embeddedice_receive(jtag_info, data, size);
 638
 639         for (i = 0; i < size; i++)
 640         {
 641                 h_u32_to_le(buffer + (i * 4), data[i]);
 642         }
 643
 644         free(data);
 645
 646         return ERROR_OK;
 647 }
 648
 649 int arm7_9_handle_target_request(void *priv)
 650 {
 651         target_t *target = priv;
 652         armv4_5_common_t *armv4_5 = target->arch_info;
 653         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 654         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 655         reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
 656
 657         if (!target->dbg_msg_enabled)
 658                 return ERROR_OK;
 659
 660         if (target->state == TARGET_RUNNING)
 661         {
 662                 /* read DCC control register */
 663                 embeddedice_read_reg(dcc_control);
 664                 jtag_execute_queue();
 665
 666                 /* check W bit */
 667                 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
 668                 {
 669                         u32 request;
 670
 671                         embeddedice_receive(jtag_info, &request, 1);
 672                         target_request(target, request);
 673                 }
 674         }
 675
 676         return ERROR_OK;
 677 }
 678
 679 int arm7_9_poll(target_t *target)
 680 {
 681         int retval;
 682         armv4_5_common_t *armv4_5 = target->arch_info;
 683         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 684         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 685
 686         if (arm7_9->reinit_embeddedice)
 687         {
 688                 arm7_9_reinit_embeddedice(target);
 689         }
 690
 691         /* read debug status register */
 692         embeddedice_read_reg(dbg_stat);
 693         if ((retval = jtag_execute_queue()) != ERROR_OK)
 694         {
 695                 return retval;
 696         }
 697
 698         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 699         {
 700                 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
 701                 if (target->state == TARGET_UNKNOWN)
 702                 {
 703                         target->state = TARGET_RUNNING;
 704                         WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
 705                 }
 706                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 707                 {
 708                         target->state = TARGET_HALTED;
 709                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 710                                 return retval;
 711
 712                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 713                 }
 714                 if (target->state == TARGET_DEBUG_RUNNING)
 715                 {
 716                         target->state = TARGET_HALTED;
 717                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 718                                 return retval;
 719
 720                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 721                 }
 722                 if (target->state != TARGET_HALTED)
 723                 {
 724                         WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
 725                 }
 726         }
 727         else
 728         {
 729                 if (target->state != TARGET_DEBUG_RUNNING)
 730                         target->state = TARGET_RUNNING;
 731         }
 732
 733         return ERROR_OK;
 734 }
 735
 736 int arm7_9_assert_reset(target_t *target)
 737 {
 738         int retval;
 739
 740         DEBUG("target->state: %s", target_state_strings[target->state]);
 741
 742         if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
 743         {
 744                 /* if the target wasn't running, there might be working areas allocated */
 745                 target_free_all_working_areas(target);
 746
 747                 /* assert SRST and TRST */
 748                 /* system would get ouf sync if we didn't reset test-logic, too */
 749                 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
 750                 {
 751                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 752                         {
 753                                 WARNING("can't assert srst");
 754                                 return retval;
 755                         }
 756                         else
 757                         {
 758                                 ERROR("unknown error");
 759                                 exit(-1);
 760                         }
 761                 }
 762                 jtag_add_sleep(5000);
 763                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 764                 {
 765                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 766                         {
 767                                 retval = jtag_add_reset(1, 1);
 768                         }
 769                 }
 770         }
 771         else
 772         {
 773                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 774                 {
 775                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 776                         {
 777                                 retval = jtag_add_reset(1, 1);
 778                         }
 779
 780                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 781                         {
 782                                 WARNING("can't assert srst");
 783                                 return retval;
 784                         }
 785                         else if (retval != ERROR_OK)
 786                         {
 787                                 ERROR("unknown error");
 788                                 exit(-1);
 789                         }
 790                 }
 791         }
 792
 793         target->state = TARGET_RESET;
 794         jtag_add_sleep(50000);
 795
 796         armv4_5_invalidate_core_regs(target);
 797
 798         return ERROR_OK;
 799
 800 }
 801
 802 int arm7_9_deassert_reset(target_t *target)
 803 {
 804         DEBUG("target->state: %s", target_state_strings[target->state]);
 805
 806         /* deassert reset lines */
 807         jtag_add_reset(0, 0);
 808
 809         return ERROR_OK;
 810 }
 811
 812 int arm7_9_clear_halt(target_t *target)
 813 {
 814         armv4_5_common_t *armv4_5 = target->arch_info;
 815         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 816         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 817
 818         /* we used DBGRQ only if we didn't come out of reset */
 819         if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
 820         {
 821                 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
 822                  */
 823                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 824                 embeddedice_store_reg(dbg_ctrl);
 825         }
 826         else
 827         {
 828                 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
 829                 {
 830                         /* if we came out of reset, and vector catch is supported, we used
 831                          * vector catch to enter debug state
 832                          * restore the register in that case
 833                          */
 834                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
 835                 }
 836                 else
 837                 {
 838                         /* restore registers if watchpoint unit 0 was in use
 839                          */
 840                         if (arm7_9->wp0_used)
 841                         {
 842                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
 843                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
 844                                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
 845                         }
 846                         /* control value always has to be restored, as it was either disabled,
 847                          * or enabled with possibly different bits
 848                          */
 849                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 850                 }
 851         }
 852
 853         return ERROR_OK;
 854 }
 855
 856 int arm7_9_soft_reset_halt(struct target_s *target)
 857 {
 858         armv4_5_common_t *armv4_5 = target->arch_info;
 859         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 860         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 861         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 862         int i;
 863
 864         if (target->state == TARGET_RUNNING)
 865         {
 866                 target->type->halt(target);
 867         }
 868
 869         while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 870         {
 871                 embeddedice_read_reg(dbg_stat);
 872                 jtag_execute_queue();
 873         }
 874         target->state = TARGET_HALTED;
 875
 876         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 877          * ensure that DBGRQ is cleared
 878          */
 879         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 880         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 881         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 882         embeddedice_store_reg(dbg_ctrl);
 883
 884         arm7_9_clear_halt(target);
 885
 886         /* if the target is in Thumb state, change to ARM state */
 887         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
 888         {
 889                 u32 r0_thumb, pc_thumb;
 890                 DEBUG("target entered debug from Thumb state, changing to ARM");
 891                 /* Entered debug from Thumb mode */
 892                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
 893                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
 894         }
 895
 896         /* all register content is now invalid */
 897         armv4_5_invalidate_core_regs(target);
 898
 899         /* SVC, ARM state, IRQ and FIQ disabled */
 900         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 901         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 902         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 903
 904         /* start fetching from 0x0 */
 905         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 906         armv4_5->core_cache->reg_list[15].dirty = 1;
 907         armv4_5->core_cache->reg_list[15].valid = 1;
 908
 909         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 910         armv4_5->core_state = ARMV4_5_STATE_ARM;
 911
 912         /* reset registers */
 913         for (i = 0; i <= 14; i++)
 914         {
 915                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
 916                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
 917                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 918         }
 919
 920         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 921
 922         return ERROR_OK;
 923 }
 924
 925 int arm7_9_prepare_reset_halt(target_t *target)
 926 {
 927         armv4_5_common_t *armv4_5 = target->arch_info;
 928         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 929
 930         /* poll the target, and resume if it was currently halted */
 931         arm7_9_poll(target);
 932         if (target->state == TARGET_HALTED)
 933         {
 934                 arm7_9_resume(target, 1, 0x0, 0, 1);
 935         }
 936
 937         if (arm7_9->has_vector_catch)
 938         {
 939                 /* program vector catch register to catch reset vector */
 940                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
 941         }
 942         else
 943         {
 944                 /* program watchpoint unit to match on reset vector address */
 945                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
 946                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
 947                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
 948                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
 949         }
 950
 951         return ERROR_OK;
 952 }
 953
 954 int arm7_9_halt(target_t *target)
 955 {
 956         armv4_5_common_t *armv4_5 = target->arch_info;
 957         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 958         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 959
 960         DEBUG("target->state: %s", target_state_strings[target->state]);
 961
 962         if (target->state == TARGET_HALTED)
 963         {
 964                 WARNING("target was already halted");
 965                 return ERROR_TARGET_ALREADY_HALTED;
 966         }
 967
 968         if (target->state == TARGET_UNKNOWN)
 969         {
 970                 WARNING("target was in unknown state when halt was requested");
 971         }
 972
 973         if (target->state == TARGET_RESET)
 974         {
 975                 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
 976                 {
 977                         ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 978                         return ERROR_TARGET_FAILURE;
 979                 }
 980                 else
 981                 {
 982                         /* we came here in a reset_halt or reset_init sequence
 983                          * debug entry was already prepared in arm7_9_prepare_reset_halt()
 984                          */
 985                         target->debug_reason = DBG_REASON_DBGRQ;
 986
 987                         return ERROR_OK;
 988                 }
 989         }
 990
 991         if (arm7_9->use_dbgrq)
 992         {
 993                 /* program EmbeddedICE Debug Control Register to assert DBGRQ
 994                  */
 995                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
 996                 embeddedice_store_reg(dbg_ctrl);
 997         }
 998         else
 999         {
1000                 /* program watchpoint unit to match on any address
1001                  */
1002                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1003                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1004                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1005                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
1006         }
1007
1008         target->debug_reason = DBG_REASON_DBGRQ;
1009
1010         return ERROR_OK;
1011 }
1012
1013 int arm7_9_debug_entry(target_t *target)
1014 {
1015         int i;
1016         u32 context[16];
1017         u32* context_p[16];
1018         u32 r0_thumb, pc_thumb;
1019         u32 cpsr;
1020         int retval;
1021         /* get pointers to arch-specific information */
1022         armv4_5_common_t *armv4_5 = target->arch_info;
1023         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1024         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1025         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1026
1027 #ifdef _DEBUG_ARM7_9_
1028         DEBUG("-");
1029 #endif
1030
1031         if (arm7_9->pre_debug_entry)
1032                 arm7_9->pre_debug_entry(target);
1033
1034         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1035          * ensure that DBGRQ is cleared
1036          */
1037         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1038         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1039         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1040         embeddedice_store_reg(dbg_ctrl);
1041
1042         arm7_9_clear_halt(target);
1043
1044         if ((retval = jtag_execute_queue()) != ERROR_OK)
1045         {
1046                 switch (retval)
1047                 {
1048                         case ERROR_JTAG_QUEUE_FAILED:
1049                                 ERROR("JTAG queue failed while writing EmbeddedICE control register");
1050                                 exit(-1);
1051                                 break;
1052                         default:
1053                                 break;
1054                 }
1055         }
1056
1057         if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1058                 return retval;
1059
1060
1061         if (target->state != TARGET_HALTED)
1062         {
1063                 WARNING("target not halted");
1064                 return ERROR_TARGET_NOT_HALTED;
1065         }
1066
1067         /* if the target is in Thumb state, change to ARM state */
1068         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1069         {
1070                 DEBUG("target entered debug from Thumb state");
1071                 /* Entered debug from Thumb mode */
1072                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1073                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1074                 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1075         }
1076         else
1077         {
1078                 DEBUG("target entered debug from ARM state");
1079                 /* Entered debug from ARM mode */
1080                 armv4_5->core_state = ARMV4_5_STATE_ARM;
1081         }
1082
1083         for (i = 0; i < 16; i++)
1084                 context_p[i] = &context[i];
1085         /* save core registers (r0 - r15 of current core mode) */
1086         arm7_9->read_core_regs(target, 0xffff, context_p);
1087
1088         arm7_9->read_xpsr(target, &cpsr, 0);
1089
1090         if ((retval = jtag_execute_queue()) != ERROR_OK)
1091                 return retval;
1092
1093         /* if the core has been executing in Thumb state, set the T bit */
1094         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1095                 cpsr |= 0x20;
1096
1097         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1098         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1099         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1100
1101         armv4_5->core_mode = cpsr & 0x1f;
1102
1103         if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1104         {
1105                 target->state = TARGET_UNKNOWN;
1106                 ERROR("cpsr contains invalid mode value - communication failure");
1107                 return ERROR_TARGET_FAILURE;
1108         }
1109
1110         DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1111
1112         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1113         {
1114                 DEBUG("thumb state, applying fixups");
1115                 context[0] = r0_thumb;
1116                 context[15] = pc_thumb;
1117         } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1118         {
1119                 /* adjust value stored by STM */
1120                 context[15] -= 3 * 4;
1121         }
1122
1123         if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1124                         || (target->debug_reason == DBG_REASON_SINGLESTEP)
1125                         || (target->debug_reason == DBG_REASON_WATCHPOINT)
1126                         || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1127                         || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1128                 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1129         else if (target->debug_reason == DBG_REASON_DBGRQ)
1130                 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1131         else
1132         {
1133                 ERROR("unknown debug reason: %i", target->debug_reason);
1134         }
1135
1136
1137         for (i=0; i<=15; i++)
1138         {
1139                 DEBUG("r%i: 0x%8.8x", i, context[i]);
1140                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1141                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1142                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1143         }
1144
1145         DEBUG("entered debug state at PC 0x%x", context[15]);
1146
1147         /* exceptions other than USR & SYS have a saved program status register */
1148         if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1149         {
1150                 u32 spsr;
1151                 arm7_9->read_xpsr(target, &spsr, 1);
1152                 jtag_execute_queue();
1153                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1154                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1155                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1156         }
1157
1158         /* r0 and r15 (pc) have to be restored later */
1159         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1160         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1161
1162         if ((retval = jtag_execute_queue()) != ERROR_OK)
1163                 return retval;
1164
1165         if (arm7_9->post_debug_entry)
1166                 arm7_9->post_debug_entry(target);
1167
1168         return ERROR_OK;
1169 }
1170
1171 int arm7_9_full_context(target_t *target)
1172 {
1173         int i;
1174         int retval;
1175         armv4_5_common_t *armv4_5 = target->arch_info;
1176         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1177
1178         DEBUG("-");
1179
1180         if (target->state != TARGET_HALTED)
1181         {
1182                 WARNING("target not halted");
1183                 return ERROR_TARGET_NOT_HALTED;
1184         }
1185
1186         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1187          * SYS shares registers with User, so we don't touch SYS
1188          */
1189         for(i = 0; i < 6; i++)
1190         {
1191                 u32 mask = 0;
1192                 u32* reg_p[16];
1193                 int j;
1194                 int valid = 1;
1195
1196                 /* check if there are invalid registers in the current mode
1197                  */
1198                 for (j = 0; j <= 16; j++)
1199                 {
1200                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1201                                 valid = 0;
1202                 }
1203
1204                 if (!valid)
1205                 {
1206                         u32 tmp_cpsr;
1207
1208                         /* change processor mode (and mask T bit) */
1209                         tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1210                         tmp_cpsr |= armv4_5_number_to_mode(i);
1211                         tmp_cpsr &= ~0x20;
1212                         arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1213
1214                         for (j = 0; j < 15; j++)
1215                         {
1216                                 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1217                                 {
1218                                         reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1219                                         mask |= 1 << j;
1220                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1221                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1222                                 }
1223                         }
1224
1225                         /* if only the PSR is invalid, mask is all zeroes */
1226                         if (mask)
1227                                 arm7_9->read_core_regs(target, mask, reg_p);
1228
1229                         /* check if the PSR has to be read */
1230                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1231                         {
1232                                 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1233                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1234                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1235                         }
1236                 }
1237         }
1238
1239         /* restore processor mode (mask T bit) */
1240         arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1241
1242         if ((retval = jtag_execute_queue()) != ERROR_OK)
1243         {
1244                 ERROR("JTAG failure");
1245                 exit(-1);
1246         }
1247         return ERROR_OK;
1248 }
1249
1250 int arm7_9_restore_context(target_t *target)
1251 {
1252         armv4_5_common_t *armv4_5 = target->arch_info;
1253         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1254         reg_t *reg;
1255         armv4_5_core_reg_t *reg_arch_info;
1256         enum armv4_5_mode current_mode = armv4_5->core_mode;
1257         int i, j;
1258         int dirty;
1259         int mode_change;
1260
1261         DEBUG("-");
1262
1263         if (target->state != TARGET_HALTED)
1264         {
1265                 WARNING("target not halted");
1266                 return ERROR_TARGET_NOT_HALTED;
1267         }
1268
1269         if (arm7_9->pre_restore_context)
1270                 arm7_9->pre_restore_context(target);
1271
1272         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1273          * SYS shares registers with User, so we don't touch SYS
1274          */
1275         for (i = 0; i < 6; i++)
1276         {
1277                 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1278                 dirty = 0;
1279                 mode_change = 0;
1280                 /* check if there are dirty registers in the current mode
1281                 */
1282                 for (j = 0; j <= 16; j++)
1283                 {
1284                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1285                         reg_arch_info = reg->arch_info;
1286                         if (reg->dirty == 1)
1287                         {
1288                                 if (reg->valid == 1)
1289                                 {
1290                                         dirty = 1;
1291                                         DEBUG("examining dirty reg: %s", reg->name);
1292                                         if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1293                                                 && (reg_arch_info->mode != current_mode)
1294                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1295                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1296                                         {
1297                                                 mode_change = 1;
1298                                                 DEBUG("require mode change");
1299                                         }
1300                                 }
1301                                 else
1302                                 {
1303                                         ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1304                                 }
1305                         }
1306                 }
1307
1308                 if (dirty)
1309                 {
1310                         u32 mask = 0x0;
1311                         int num_regs = 0;
1312                         u32 regs[16];
1313
1314                         if (mode_change)
1315                         {
1316                                 u32 tmp_cpsr;
1317
1318                                 /* change processor mode (mask T bit) */
1319                                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1320                                 tmp_cpsr |= armv4_5_number_to_mode(i);
1321                                 tmp_cpsr &= ~0x20;
1322                                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1323                                 current_mode = armv4_5_number_to_mode(i);
1324                         }
1325
1326                         for (j = 0; j <= 14; j++)
1327                         {
1328                                 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1329                                 reg_arch_info = reg->arch_info;
1330
1331
1332                                 if (reg->dirty == 1)
1333                                 {
1334                                         regs[j] = buf_get_u32(reg->value, 0, 32);
1335                                         mask |= 1 << j;
1336                                         num_regs++;
1337                                         reg->dirty = 0;
1338                                         reg->valid = 1;
1339                                         DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1340                                 }
1341                         }
1342
1343                         if (mask)
1344                         {
1345                                 arm7_9->write_core_regs(target, mask, regs);
1346                         }
1347
1348                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1349                         reg_arch_info = reg->arch_info;
1350                         if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1351                         {
1352                                 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1353                                 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1354                         }
1355                 }
1356         }
1357
1358         if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1359         {
1360                 /* restore processor mode (mask T bit) */
1361                 u32 tmp_cpsr;
1362
1363                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1364                 tmp_cpsr |= armv4_5_number_to_mode(i);
1365                 tmp_cpsr &= ~0x20;
1366                 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1367                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1368         }
1369         else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1370         {
1371                 /* CPSR has been changed, full restore necessary (mask T bit) */
1372                 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1373                 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1374                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1375                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1376         }
1377
1378         /* restore PC */
1379         DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1380         arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1381         armv4_5->core_cache->reg_list[15].dirty = 0;
1382
1383         if (arm7_9->post_restore_context)
1384                 arm7_9->post_restore_context(target);
1385
1386         return ERROR_OK;
1387 }
1388
1389 int arm7_9_restart_core(struct target_s *target)
1390 {
1391         armv4_5_common_t *armv4_5 = target->arch_info;
1392         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1393         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1394
1395         /* set RESTART instruction */
1396         jtag_add_end_state(TAP_RTI);
1397         arm_jtag_set_instr(jtag_info, 0x4, NULL);
1398
1399         jtag_add_runtest(1, TAP_RTI);
1400         if ((jtag_execute_queue()) != ERROR_OK)
1401         {
1402                 exit(-1);
1403         }
1404
1405         return ERROR_OK;
1406 }
1407
1408 void arm7_9_enable_watchpoints(struct target_s *target)
1409 {
1410         watchpoint_t *watchpoint = target->watchpoints;
1411
1412         while (watchpoint)
1413         {
1414                 if (watchpoint->set == 0)
1415                         arm7_9_set_watchpoint(target, watchpoint);
1416                 watchpoint = watchpoint->next;
1417         }
1418 }
1419
1420 void arm7_9_enable_breakpoints(struct target_s *target)
1421 {
1422         breakpoint_t *breakpoint = target->breakpoints;
1423
1424         /* set any pending breakpoints */
1425         while (breakpoint)
1426         {
1427                 if (breakpoint->set == 0)
1428                         arm7_9_set_breakpoint(target, breakpoint);
1429                 breakpoint = breakpoint->next;
1430         }
1431 }
1432
1433 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1434 {
1435         breakpoint_t *breakpoint = target->breakpoints;
1436         watchpoint_t *watchpoint = target->watchpoints;
1437
1438         /* set any pending breakpoints */
1439         while (breakpoint)
1440         {
1441                 if (breakpoint->set != 0)
1442                         arm7_9_unset_breakpoint(target, breakpoint);
1443                 breakpoint = breakpoint->next;
1444         }
1445
1446         while (watchpoint)
1447         {
1448                 if (watchpoint->set != 0)
1449                         arm7_9_unset_watchpoint(target, watchpoint);
1450                 watchpoint = watchpoint->next;
1451         }
1452 }
1453
1454 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1455 {
1456         armv4_5_common_t *armv4_5 = target->arch_info;
1457         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1458         breakpoint_t *breakpoint = target->breakpoints;
1459         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1460         int err;
1461
1462         DEBUG("-");
1463
1464         if (target->state != TARGET_HALTED)
1465         {
1466                 WARNING("target not halted");
1467                 return ERROR_TARGET_NOT_HALTED;
1468         }
1469
1470         if (!debug_execution)
1471         {
1472                 target_free_all_working_areas(target);
1473         }
1474
1475         /* current = 1: continue on current pc, otherwise continue at <address> */
1476         if (!current)
1477                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1478
1479         /* the front-end may request us not to handle breakpoints */
1480         if (handle_breakpoints)
1481         {
1482                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1483                 {
1484                         DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1485                         arm7_9_unset_breakpoint(target, breakpoint);
1486
1487                         DEBUG("enable single-step");
1488                         arm7_9->enable_single_step(target);
1489
1490                         target->debug_reason = DBG_REASON_SINGLESTEP;
1491
1492                         arm7_9_restore_context(target);
1493
1494                         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1495                                 arm7_9->branch_resume(target);
1496                         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1497                         {
1498                                 arm7_9->branch_resume_thumb(target);
1499                         }
1500                         else
1501                         {
1502                                 ERROR("unhandled core state");
1503                                 exit(-1);
1504                         }
1505
1506                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1507                         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1508                         err = arm7_9_execute_sys_speed(target);
1509
1510                         DEBUG("disable single-step");
1511                         arm7_9->disable_single_step(target);
1512
1513                         if (err != ERROR_OK)
1514                         {
1515                                 arm7_9_set_breakpoint(target, breakpoint);
1516                                 target->state = TARGET_UNKNOWN;
1517                                 return err;
1518                         }
1519
1520                         arm7_9_debug_entry(target);
1521                         DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1522
1523                         DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1524                         arm7_9_set_breakpoint(target, breakpoint);
1525                 }
1526         }
1527
1528         /* enable any pending breakpoints and watchpoints */
1529         arm7_9_enable_breakpoints(target);
1530         arm7_9_enable_watchpoints(target);
1531
1532         arm7_9_restore_context(target);
1533
1534         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1535         {
1536                 arm7_9->branch_resume(target);
1537         }
1538         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1539         {
1540                 arm7_9->branch_resume_thumb(target);
1541         }
1542         else
1543         {
1544                 ERROR("unhandled core state");
1545                 exit(-1);
1546         }
1547
1548         /* deassert DBGACK and INTDIS */
1549         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1550         /* INTDIS only when we really resume, not during debug execution */
1551         if (!debug_execution)
1552                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1553         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1554
1555         arm7_9_restart_core(target);
1556
1557         target->debug_reason = DBG_REASON_NOTHALTED;
1558
1559         if (!debug_execution)
1560         {
1561                 /* registers are now invalid */
1562                 armv4_5_invalidate_core_regs(target);
1563                 target->state = TARGET_RUNNING;
1564                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1565         }
1566         else
1567         {
1568                 target->state = TARGET_DEBUG_RUNNING;
1569                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1570         }
1571
1572         DEBUG("target resumed");
1573
1574         return ERROR_OK;
1575 }
1576
1577 void arm7_9_enable_eice_step(target_t *target)
1578 {
1579         armv4_5_common_t *armv4_5 = target->arch_info;
1580         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1581
1582         /* setup an inverse breakpoint on the current PC
1583         * - comparator 1 matches the current address
1584         * - rangeout from comparator 1 is connected to comparator 0 rangein
1585         * - comparator 0 matches any address, as long as rangein is low */
1586         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1587         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1588         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1589         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1590         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1591         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1592         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1593         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1594         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1595 }
1596
1597 void arm7_9_disable_eice_step(target_t *target)
1598 {
1599         armv4_5_common_t *armv4_5 = target->arch_info;
1600         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1601
1602         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1603         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1604         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1605         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1606         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1607         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1608         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1609         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1610         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1611 }
1612
1613 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1614 {
1615         armv4_5_common_t *armv4_5 = target->arch_info;
1616         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1617         breakpoint_t *breakpoint = NULL;
1618         int err;
1619
1620         if (target->state != TARGET_HALTED)
1621         {
1622                 WARNING("target not halted");
1623                 return ERROR_TARGET_NOT_HALTED;
1624         }
1625
1626         /* current = 1: continue on current pc, otherwise continue at <address> */
1627         if (!current)
1628                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1629
1630         /* the front-end may request us not to handle breakpoints */
1631         if (handle_breakpoints)
1632                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1633                         arm7_9_unset_breakpoint(target, breakpoint);
1634
1635         target->debug_reason = DBG_REASON_SINGLESTEP;
1636
1637         arm7_9_restore_context(target);
1638
1639         arm7_9->enable_single_step(target);
1640
1641         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1642         {
1643                 arm7_9->branch_resume(target);
1644         }
1645         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1646         {
1647                 arm7_9->branch_resume_thumb(target);
1648         }
1649         else
1650         {
1651                 ERROR("unhandled core state");
1652                 exit(-1);
1653         }
1654
1655         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1656
1657         err = arm7_9_execute_sys_speed(target);
1658         arm7_9->disable_single_step(target);
1659
1660         /* registers are now invalid */
1661         armv4_5_invalidate_core_regs(target);
1662
1663         if (err != ERROR_OK)
1664         {
1665                 target->state = TARGET_UNKNOWN;
1666         } else {
1667                 arm7_9_debug_entry(target);
1668                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1669                 DEBUG("target stepped");
1670         }
1671
1672         if (breakpoint)
1673                 arm7_9_set_breakpoint(target, breakpoint);
1674
1675         return err;
1676
1677 }
1678
1679 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1680 {
1681         u32* reg_p[16];
1682         u32 value;
1683         int retval;
1684         armv4_5_common_t *armv4_5 = target->arch_info;
1685         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1686         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1687
1688         if ((num < 0) || (num > 16))
1689                 return ERROR_INVALID_ARGUMENTS;
1690
1691         if ((mode != ARMV4_5_MODE_ANY)
1692                         && (mode != armv4_5->core_mode)
1693                         && (reg_mode != ARMV4_5_MODE_ANY))
1694         {
1695                 u32 tmp_cpsr;
1696
1697                 /* change processor mode (mask T bit) */
1698                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1699                 tmp_cpsr |= mode;
1700                 tmp_cpsr &= ~0x20;
1701                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1702         }
1703
1704         if ((num >= 0) && (num <= 15))
1705         {
1706                 /* read a normal core register */
1707                 reg_p[num] = &value;
1708
1709                 arm7_9->read_core_regs(target, 1 << num, reg_p);
1710         }
1711         else
1712         {
1713                 /* read a program status register
1714                  * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1715                  */
1716                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1717                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1718
1719                 arm7_9->read_xpsr(target, &value, spsr);
1720         }
1721
1722         if ((retval = jtag_execute_queue()) != ERROR_OK)
1723         {
1724                 ERROR("JTAG failure");
1725                 exit(-1);
1726         }
1727
1728         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1729         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1730         buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1731
1732         if ((mode != ARMV4_5_MODE_ANY)
1733                         && (mode != armv4_5->core_mode)
1734                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1735                 /* restore processor mode (mask T bit) */
1736                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1737         }
1738
1739         return ERROR_OK;
1740
1741 }
1742
1743 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1744 {
1745         u32 reg[16];
1746         int retval;
1747         armv4_5_common_t *armv4_5 = target->arch_info;
1748         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1749         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1750
1751         if ((num < 0) || (num > 16))
1752                 return ERROR_INVALID_ARGUMENTS;
1753
1754         if ((mode != ARMV4_5_MODE_ANY)
1755                         && (mode != armv4_5->core_mode)
1756                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1757                 u32 tmp_cpsr;
1758
1759                 /* change processor mode (mask T bit) */
1760                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1761                 tmp_cpsr |= mode;
1762                 tmp_cpsr &= ~0x20;
1763                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1764         }
1765
1766         if ((num >= 0) && (num <= 15))
1767         {
1768                 /* write a normal core register */
1769                 reg[num] = value;
1770
1771                 arm7_9->write_core_regs(target, 1 << num, reg);
1772         }
1773         else
1774         {
1775                 /* write a program status register
1776                 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1777                 */
1778                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1779                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1780
1781                 /* if we're writing the CPSR, mask the T bit */
1782                 if (!spsr)
1783                         value &= ~0x20;
1784
1785                 arm7_9->write_xpsr(target, value, spsr);
1786         }
1787
1788         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1789         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1790
1791         if ((mode != ARMV4_5_MODE_ANY)
1792                         && (mode != armv4_5->core_mode)
1793                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1794                 /* restore processor mode (mask T bit) */
1795                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1796         }
1797
1798         if ((retval = jtag_execute_queue()) != ERROR_OK)
1799         {
1800                 ERROR("JTAG failure");
1801                 exit(-1);
1802         }
1803
1804         return ERROR_OK;
1805
1806 }
1807
1808 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1809 {
1810         armv4_5_common_t *armv4_5 = target->arch_info;
1811         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1812
1813         u32 reg[16];
1814         int num_accesses = 0;
1815         int thisrun_accesses;
1816         int i;
1817         u32 cpsr;
1818         int retval;
1819         int last_reg = 0;
1820
1821         DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1822
1823         if (target->state != TARGET_HALTED)
1824         {
1825                 WARNING("target not halted");
1826                 return ERROR_TARGET_NOT_HALTED;
1827         }
1828
1829         /* sanitize arguments */
1830         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1831                 return ERROR_INVALID_ARGUMENTS;
1832
1833         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1834                 return ERROR_TARGET_UNALIGNED_ACCESS;
1835
1836         /* load the base register with the address of the first word */
1837         reg[0] = address;
1838         arm7_9->write_core_regs(target, 0x1, reg);
1839
1840         switch (size)
1841         {
1842                 case 4:
1843                         while (num_accesses < count)
1844                         {
1845                                 u32 reg_list;
1846                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1847                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1848
1849                                 if (last_reg <= thisrun_accesses)
1850                                         last_reg = thisrun_accesses;
1851
1852                                 arm7_9->load_word_regs(target, reg_list);
1853
1854                                 /* fast memory reads are only safe when the target is running
1855                                  * from a sufficiently high clock (32 kHz is usually too slow)
1856                                  */
1857                                 if (arm7_9->fast_memory_access)
1858                                         arm7_9_execute_fast_sys_speed(target);
1859                                 else
1860                                         arm7_9_execute_sys_speed(target);
1861
1862                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1863
1864                                 /* advance buffer, count number of accesses */
1865                                 buffer += thisrun_accesses * 4;
1866                                 num_accesses += thisrun_accesses;
1867                         }
1868                         break;
1869                 case 2:
1870                         while (num_accesses < count)
1871                         {
1872                                 u32 reg_list;
1873                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1874                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1875
1876                                 for (i = 1; i <= thisrun_accesses; i++)
1877                                 {
1878                                         if (i > last_reg)
1879                                                 last_reg = i;
1880                                         arm7_9->load_hword_reg(target, i);
1881                                         /* fast memory reads are only safe when the target is running
1882                                          * from a sufficiently high clock (32 kHz is usually too slow)
1883                                          */
1884                                         if (arm7_9->fast_memory_access)
1885                                                 arm7_9_execute_fast_sys_speed(target);
1886                                         else
1887                                                 arm7_9_execute_sys_speed(target);
1888                                 }
1889
1890                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1891
1892                                 /* advance buffer, count number of accesses */
1893                                 buffer += thisrun_accesses * 2;
1894                                 num_accesses += thisrun_accesses;
1895                         }
1896                         break;
1897                 case 1:
1898                         while (num_accesses < count)
1899                         {
1900                                 u32 reg_list;
1901                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1902                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1903
1904                                 for (i = 1; i <= thisrun_accesses; i++)
1905                                 {
1906                                         if (i > last_reg)
1907                                                 last_reg = i;
1908                                         arm7_9->load_byte_reg(target, i);
1909                                         /* fast memory reads are only safe when the target is running
1910                                          * from a sufficiently high clock (32 kHz is usually too slow)
1911                                          */
1912                                         if (arm7_9->fast_memory_access)
1913                                                 arm7_9_execute_fast_sys_speed(target);
1914                                         else
1915                                                 arm7_9_execute_sys_speed(target);
1916                                 }
1917
1918                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1919
1920                                 /* advance buffer, count number of accesses */
1921                                 buffer += thisrun_accesses * 1;
1922                                 num_accesses += thisrun_accesses;
1923                         }
1924                         break;
1925                 default:
1926                         ERROR("BUG: we shouldn't get here");
1927                         exit(-1);
1928                         break;
1929         }
1930
1931         for (i=0; i<=last_reg; i++)
1932                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1933
1934         arm7_9->read_xpsr(target, &cpsr, 0);
1935         if ((retval = jtag_execute_queue()) != ERROR_OK)
1936         {
1937                 ERROR("JTAG error while reading cpsr");
1938                 return ERROR_TARGET_DATA_ABORT;
1939         }
1940
1941         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1942         {
1943                 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1944
1945                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1946
1947                 return ERROR_TARGET_DATA_ABORT;
1948         }
1949
1950         return ERROR_OK;
1951 }
1952
1953 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1954 {
1955         armv4_5_common_t *armv4_5 = target->arch_info;
1956         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1957         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1958
1959         u32 reg[16];
1960         int num_accesses = 0;
1961         int thisrun_accesses;
1962         int i;
1963         u32 cpsr;
1964         int retval;
1965         int last_reg = 0;
1966
1967 #ifdef _DEBUG_ARM7_9_
1968         DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1969 #endif
1970
1971         if (target->state != TARGET_HALTED)
1972         {
1973                 WARNING("target not halted");
1974                 return ERROR_TARGET_NOT_HALTED;
1975         }
1976
1977         /* sanitize arguments */
1978         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1979                 return ERROR_INVALID_ARGUMENTS;
1980
1981         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1982                 return ERROR_TARGET_UNALIGNED_ACCESS;
1983
1984         /* load the base register with the address of the first word */
1985         reg[0] = address;
1986         arm7_9->write_core_regs(target, 0x1, reg);
1987
1988         /* Clear DBGACK, to make sure memory fetches work as expected */
1989         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1990         embeddedice_store_reg(dbg_ctrl);
1991
1992         switch (size)
1993         {
1994                 case 4:
1995                         while (num_accesses < count)
1996                         {
1997                                 u32 reg_list;
1998                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1999                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2000
2001                                 for (i = 1; i <= thisrun_accesses; i++)
2002                                 {
2003                                         if (i > last_reg)
2004                                                 last_reg = i;
2005                                         reg[i] = target_buffer_get_u32(target, buffer);
2006                                         buffer += 4;
2007                                 }
2008
2009                                 arm7_9->write_core_regs(target, reg_list, reg);
2010
2011                                 arm7_9->store_word_regs(target, reg_list);
2012
2013                                 /* fast memory writes are only safe when the target is running
2014                                  * from a sufficiently high clock (32 kHz is usually too slow)
2015                                  */
2016                                 if (arm7_9->fast_memory_access)
2017                                         arm7_9_execute_fast_sys_speed(target);
2018                                 else
2019                                         arm7_9_execute_sys_speed(target);
2020
2021                                 num_accesses += thisrun_accesses;
2022                         }
2023                         break;
2024                 case 2:
2025                         while (num_accesses < count)
2026                         {
2027                                 u32 reg_list;
2028                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2029                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2030
2031                                 for (i = 1; i <= thisrun_accesses; i++)
2032                                 {
2033                                         if (i > last_reg)
2034                                                 last_reg = i;
2035                                         reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2036                                         buffer += 2;
2037                                 }
2038
2039                                 arm7_9->write_core_regs(target, reg_list, reg);
2040
2041                                 for (i = 1; i <= thisrun_accesses; i++)
2042                                 {
2043                                         arm7_9->store_hword_reg(target, i);
2044
2045                                         /* fast memory writes are only safe when the target is running
2046                                          * from a sufficiently high clock (32 kHz is usually too slow)
2047                                          */
2048                                         if (arm7_9->fast_memory_access)
2049                                                 arm7_9_execute_fast_sys_speed(target);
2050                                         else
2051                                                 arm7_9_execute_sys_speed(target);
2052                                 }
2053
2054                                 num_accesses += thisrun_accesses;
2055                         }
2056                         break;
2057                 case 1:
2058                         while (num_accesses < count)
2059                         {
2060                                 u32 reg_list;
2061                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2062                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2063
2064                                 for (i = 1; i <= thisrun_accesses; i++)
2065                                 {
2066                                         if (i > last_reg)
2067                                                 last_reg = i;
2068                                         reg[i] = *buffer++ & 0xff;
2069                                 }
2070
2071                                 arm7_9->write_core_regs(target, reg_list, reg);
2072
2073                                 for (i = 1; i <= thisrun_accesses; i++)
2074                                 {
2075                                         arm7_9->store_byte_reg(target, i);
2076                                         /* fast memory writes are only safe when the target is running
2077                                          * from a sufficiently high clock (32 kHz is usually too slow)
2078                                          */
2079                                         if (arm7_9->fast_memory_access)
2080                                                 arm7_9_execute_fast_sys_speed(target);
2081                                         else
2082                                                 arm7_9_execute_sys_speed(target);
2083                                 }
2084
2085                                 num_accesses += thisrun_accesses;
2086                         }
2087                         break;
2088                 default:
2089                         ERROR("BUG: we shouldn't get here");
2090                         exit(-1);
2091                         break;
2092         }
2093
2094         /* Re-Set DBGACK */
2095         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2096         embeddedice_store_reg(dbg_ctrl);
2097
2098         for (i=0; i<=last_reg; i++)
2099                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2100
2101         arm7_9->read_xpsr(target, &cpsr, 0);
2102         if ((retval = jtag_execute_queue()) != ERROR_OK)
2103         {
2104                 ERROR("JTAG error while reading cpsr");
2105                 return ERROR_TARGET_DATA_ABORT;
2106         }
2107
2108         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2109         {
2110                 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2111
2112                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2113
2114                 return ERROR_TARGET_DATA_ABORT;
2115         }
2116
2117         return ERROR_OK;
2118 }
2119
2120 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2121 {
2122         armv4_5_common_t *armv4_5 = target->arch_info;
2123         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2124         enum armv4_5_state core_state = armv4_5->core_state;
2125         u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2126         u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2127         u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2128         int i;
2129
2130         u32 dcc_code[] =
2131         {
2132                 /* MRC      TST         BNE         MRC         STR         B */
2133                 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2134         };
2135
2136         if (!arm7_9->dcc_downloads)
2137                 return target->type->write_memory(target, address, 4, count, buffer);
2138
2139         /* regrab previously allocated working_area, or allocate a new one */
2140         if (!arm7_9->dcc_working_area)
2141         {
2142                 u8 dcc_code_buf[6 * 4];
2143
2144                 /* make sure we have a working area */
2145                 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2146                 {
2147                         INFO("no working area available, falling back to memory writes");
2148                         return target->type->write_memory(target, address, 4, count, buffer);
2149                 }
2150
2151                 /* copy target instructions to target endianness */
2152                 for (i = 0; i < 6; i++)
2153                 {
2154                         target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2155                 }
2156
2157                 /* write DCC code to working area */
2158                 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2159         }
2160
2161         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2162         armv4_5->core_cache->reg_list[0].valid = 1;
2163         armv4_5->core_cache->reg_list[0].dirty = 1;
2164         armv4_5->core_state = ARMV4_5_STATE_ARM;
2165
2166         arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2167
2168         int little=target->endianness==TARGET_LITTLE_ENDIAN;
2169         if (count>2)
2170         {
2171                 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2172                    core function repeated.
2173                  */
2174                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2175                 buffer+=4;
2176
2177                 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2178                 u8 reg_addr = ice_reg->addr & 0x1f;
2179                 int chain_pos = ice_reg->jtag_info->chain_pos;
2180                 /* we want the compiler to duplicate the code, which it does not
2181                  * do automatically.
2182                  */
2183                 if (little)
2184                 {
2185                         for (i = 1; i < count - 1; i++)
2186                         {
2187                                 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2188                                 buffer += 4;
2189                         }
2190                 } else
2191                 {
2192                         for (i = 1; i < count - 1; i++)
2193                         {
2194                                 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2195                                 buffer += 4;
2196                         }
2197                 }
2198                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2199         } else
2200         {
2201                 for (i = 0; i < count; i++)
2202                 {
2203                         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2204                         buffer += 4;
2205                 }
2206         }
2207
2208         target->type->halt(target);
2209
2210         while (target->state != TARGET_HALTED)
2211                 target->type->poll(target);
2212
2213         /* restore target state */
2214         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2215         armv4_5->core_cache->reg_list[0].valid = 1;
2216         armv4_5->core_cache->reg_list[0].dirty = 1;
2217         buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2218         armv4_5->core_cache->reg_list[1].valid = 1;
2219         armv4_5->core_cache->reg_list[1].dirty = 1;
2220         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2221         armv4_5->core_cache->reg_list[15].valid = 1;
2222         armv4_5->core_cache->reg_list[15].dirty = 1;
2223         armv4_5->core_state = core_state;
2224
2225         return ERROR_OK;
2226 }
2227
2228 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2229 {
2230         working_area_t *crc_algorithm;
2231         armv4_5_algorithm_t armv4_5_info;
2232         reg_param_t reg_params[2];
2233         int retval;
2234
2235         u32 arm7_9_crc_code[] = {
2236                 0xE1A02000,                             /* mov          r2, r0 */
2237                 0xE3E00000,                             /* mov          r0, #0xffffffff */
2238                 0xE1A03001,                             /* mov          r3, r1 */
2239                 0xE3A04000,                             /* mov          r4, #0 */
2240                 0xEA00000B,                             /* b            ncomp */
2241                                                                 /* nbyte: */
2242                 0xE7D21004,                             /* ldrb r1, [r2, r4] */
2243                 0xE59F7030,                             /* ldr          r7, CRC32XOR */
2244                 0xE0200C01,                             /* eor          r0, r0, r1, asl 24 */
2245                 0xE3A05000,                             /* mov          r5, #0 */
2246                                                                 /* loop: */
2247                 0xE3500000,                             /* cmp          r0, #0 */
2248                 0xE1A06080,                             /* mov          r6, r0, asl #1 */
2249                 0xE2855001,                             /* add          r5, r5, #1 */
2250                 0xE1A00006,                             /* mov          r0, r6 */
2251                 0xB0260007,                             /* eorlt        r0, r6, r7 */
2252                 0xE3550008,                             /* cmp          r5, #8 */
2253                 0x1AFFFFF8,                             /* bne          loop */
2254                 0xE2844001,                             /* add          r4, r4, #1 */
2255                                                                 /* ncomp: */
2256                 0xE1540003,                             /* cmp          r4, r3 */
2257                 0x1AFFFFF1,                             /* bne          nbyte */
2258                                                                 /* end: */
2259                 0xEAFFFFFE,                             /* b            end */
2260                 0x04C11DB7                              /* CRC32XOR:    .word 0x04C11DB7 */
2261         };
2262
2263         int i;
2264
2265         if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2266         {
2267                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2268         }
2269
2270         /* convert flash writing code into a buffer in target endianness */
2271         for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2272                 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2273
2274         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2275         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2276         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2277
2278         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2279         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2280
2281         buf_set_u32(reg_params[0].value, 0, 32, address);
2282         buf_set_u32(reg_params[1].value, 0, 32, count);
2283
2284         if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2285                 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2286         {
2287                 ERROR("error executing arm7_9 crc algorithm");
2288                 destroy_reg_param(&reg_params[0]);
2289                 destroy_reg_param(&reg_params[1]);
2290                 target_free_working_area(target, crc_algorithm);
2291                 return retval;
2292         }
2293
2294         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2295
2296         destroy_reg_param(&reg_params[0]);
2297         destroy_reg_param(&reg_params[1]);
2298
2299         target_free_working_area(target, crc_algorithm);
2300
2301         return ERROR_OK;
2302 }
2303
2304 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2305 {
2306         command_t *arm7_9_cmd;
2307
2308         arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2309
2310         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2311         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2312
2313         register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2314
2315         register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2316         register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2317         register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2318                 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2319         register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2320                  COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2321         register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2322                  COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2323         register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2324                 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2325
2326         armv4_5_register_commands(cmd_ctx);
2327
2328         etm_register_commands(cmd_ctx);
2329
2330         return ERROR_OK;
2331 }
2332
2333 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2334 {
2335         u32 value;
2336         int spsr;
2337         int retval;
2338         target_t *target = get_current_target(cmd_ctx);
2339         armv4_5_common_t *armv4_5;
2340         arm7_9_common_t *arm7_9;
2341
2342         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2343         {
2344                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2345                 return ERROR_OK;
2346         }
2347
2348         if (target->state != TARGET_HALTED)
2349         {
2350                 command_print(cmd_ctx, "can't write registers while running");
2351                 return ERROR_OK;
2352         }
2353
2354         if (argc < 2)
2355         {
2356                 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2357                 return ERROR_OK;
2358         }
2359
2360         value = strtoul(args[0], NULL, 0);
2361         spsr = strtol(args[1], NULL, 0);
2362
2363         /* if we're writing the CPSR, mask the T bit */
2364         if (!spsr)
2365                 value &= ~0x20;
2366
2367         arm7_9->write_xpsr(target, value, spsr);
2368         if ((retval = jtag_execute_queue()) != ERROR_OK)
2369         {
2370                 ERROR("JTAG error while writing to xpsr");
2371                 exit(-1);
2372         }
2373
2374         return ERROR_OK;
2375 }
2376
2377 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2378 {
2379         u32 value;
2380         int rotate;
2381         int spsr;
2382         int retval;
2383         target_t *target = get_current_target(cmd_ctx);
2384         armv4_5_common_t *armv4_5;
2385         arm7_9_common_t *arm7_9;
2386
2387         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2388         {
2389                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2390                 return ERROR_OK;
2391         }
2392
2393         if (target->state != TARGET_HALTED)
2394         {
2395                 command_print(cmd_ctx, "can't write registers while running");
2396                 return ERROR_OK;
2397         }
2398
2399         if (argc < 3)
2400         {
2401                 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2402                 return ERROR_OK;
2403         }
2404
2405         value = strtoul(args[0], NULL, 0);
2406         rotate = strtol(args[1], NULL, 0);
2407         spsr = strtol(args[2], NULL, 0);
2408
2409         arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2410         if ((retval = jtag_execute_queue()) != ERROR_OK)
2411         {
2412                 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2413                 exit(-1);
2414         }
2415
2416         return ERROR_OK;
2417 }
2418
2419 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2420 {
2421         u32 value;
2422         u32 mode;
2423         int num;
2424         target_t *target = get_current_target(cmd_ctx);
2425         armv4_5_common_t *armv4_5;
2426         arm7_9_common_t *arm7_9;
2427
2428         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2429         {
2430                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2431                 return ERROR_OK;
2432         }
2433
2434         if (target->state != TARGET_HALTED)
2435         {
2436                 command_print(cmd_ctx, "can't write registers while running");
2437                 return ERROR_OK;
2438         }
2439
2440         if (argc < 3)
2441         {
2442                 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2443                 return ERROR_OK;
2444         }
2445
2446         num = strtol(args[0], NULL, 0);
2447         mode = strtoul(args[1], NULL, 0);
2448         value = strtoul(args[2], NULL, 0);
2449
2450         arm7_9_write_core_reg(target, num, mode, value);
2451
2452         return ERROR_OK;
2453 }
2454
2455 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2456 {
2457         target_t *target = get_current_target(cmd_ctx);
2458         armv4_5_common_t *armv4_5;
2459         arm7_9_common_t *arm7_9;
2460
2461         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2462         {
2463                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2464                 return ERROR_OK;
2465         }
2466
2467         if (argc == 0)
2468         {
2469                 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2470                 return ERROR_OK;
2471         }
2472
2473         if (strcmp("enable", args[0]) == 0)
2474         {
2475                 if (arm7_9->sw_bkpts_use_wp)
2476                 {
2477                         arm7_9_enable_sw_bkpts(target);
2478                 }
2479                 else
2480                 {
2481                         arm7_9->sw_bkpts_enabled = 1;
2482                 }
2483         }
2484         else if (strcmp("disable", args[0]) == 0)
2485         {
2486                 if (arm7_9->sw_bkpts_use_wp)
2487                 {
2488                         arm7_9_disable_sw_bkpts(target);
2489                 }
2490                 else
2491                 {
2492                         arm7_9->sw_bkpts_enabled = 0;
2493                 }
2494         }
2495         else
2496         {
2497                 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2498         }
2499
2500         command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2501
2502         return ERROR_OK;
2503 }
2504
2505 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2506 {
2507         target_t *target = get_current_target(cmd_ctx);
2508         armv4_5_common_t *armv4_5;
2509         arm7_9_common_t *arm7_9;
2510
2511         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2512         {
2513                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2514                 return ERROR_OK;
2515         }
2516
2517         if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2518         {
2519                 arm7_9->force_hw_bkpts = 1;
2520                 if (arm7_9->sw_bkpts_use_wp)
2521                 {
2522                         arm7_9_disable_sw_bkpts(target);
2523                 }
2524         }
2525         else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2526         {
2527                 arm7_9->force_hw_bkpts = 0;
2528         }
2529         else
2530         {
2531                 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2532         }
2533
2534         command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2535
2536         return ERROR_OK;
2537 }
2538
2539 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2540 {
2541         target_t *target = get_current_target(cmd_ctx);
2542         armv4_5_common_t *armv4_5;
2543         arm7_9_common_t *arm7_9;
2544
2545         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2546         {
2547                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2548                 return ERROR_OK;
2549         }
2550
2551         if (argc > 0)
2552         {
2553                 if (strcmp("enable", args[0]) == 0)
2554                 {
2555                         arm7_9->use_dbgrq = 1;
2556                 }
2557                 else if (strcmp("disable", args[0]) == 0)
2558                 {
2559                         arm7_9->use_dbgrq = 0;
2560                 }
2561                 else
2562                 {
2563                         command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2564                 }
2565         }
2566
2567         command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2568
2569         return ERROR_OK;
2570 }
2571
2572 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2573 {
2574         target_t *target = get_current_target(cmd_ctx);
2575         armv4_5_common_t *armv4_5;
2576         arm7_9_common_t *arm7_9;
2577
2578         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2579         {
2580                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2581                 return ERROR_OK;
2582         }
2583
2584         if (argc > 0)
2585         {
2586                 if (strcmp("enable", args[0]) == 0)
2587                 {
2588                         arm7_9->fast_memory_access = 1;
2589                 }
2590                 else if (strcmp("disable", args[0]) == 0)
2591                 {
2592                         arm7_9->fast_memory_access = 0;
2593                 }
2594                 else
2595                 {
2596                         command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2597                 }
2598         }
2599
2600         command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2601
2602         return ERROR_OK;
2603 }
2604
2605 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2606 {
2607         target_t *target = get_current_target(cmd_ctx);
2608         armv4_5_common_t *armv4_5;
2609         arm7_9_common_t *arm7_9;
2610
2611         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2612         {
2613                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2614                 return ERROR_OK;
2615         }
2616
2617         if (argc > 0)
2618         {
2619                 if (strcmp("enable", args[0]) == 0)
2620                 {
2621                         arm7_9->dcc_downloads = 1;
2622                 }
2623                 else if (strcmp("disable", args[0]) == 0)
2624                 {
2625                         arm7_9->dcc_downloads = 0;
2626                 }
2627                 else
2628                 {
2629                         command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2630                 }
2631         }
2632
2633         command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2634
2635         return ERROR_OK;
2636 }
2637
2638 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2639 {
2640         armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2641
2642         arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2643
2644         arm_jtag_setup_connection(&arm7_9->jtag_info);
2645         arm7_9->wp_available = 2;
2646         arm7_9->wp0_used = 0;
2647         arm7_9->wp1_used = 0;
2648         arm7_9->force_hw_bkpts = 0;
2649         arm7_9->use_dbgrq = 0;
2650
2651         arm7_9->etm_ctx = NULL;
2652         arm7_9->has_single_step = 0;
2653         arm7_9->has_monitor_mode = 0;
2654         arm7_9->has_vector_catch = 0;
2655
2656         arm7_9->reinit_embeddedice = 0;
2657
2658         arm7_9->debug_entry_from_reset = 0;
2659
2660         arm7_9->dcc_working_area = NULL;
2661
2662         arm7_9->fast_memory_access = 0;
2663         arm7_9->dcc_downloads = 0;
2664
2665         jtag_register_event_callback(arm7_9_jtag_callback, target);
2666
2667         armv4_5->arch_info = arm7_9;
2668         armv4_5->read_core_reg = arm7_9_read_core_reg;
2669         armv4_5->write_core_reg = arm7_9_write_core_reg;
2670         armv4_5->full_context = arm7_9_full_context;
2671
2672         armv4_5_init_arch_info(target, armv4_5);
2673
2674         target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
2675
2676         return ERROR_OK;
2677 }