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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "embeddedice.h"
  27 #include "target.h"
  28 #include "armv4_5.h"
  29 #include "arm_jtag.h"
  30 #include "jtag.h"
  31 #include "log.h"
  32 #include "arm7_9_common.h"
  33 #include "breakpoints.h"
  34
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <unistd.h>
  38
  39 #include <sys/types.h>
  40 #include <sys/stat.h>
  41 #include <sys/time.h>
  42 #include <errno.h>
  43
  44 int arm7_9_debug_entry(target_t *target);
  45 int arm7_9_enable_sw_bkpts(struct target_s *target);
  46
  47 /* command handler forward declarations */
  48 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  55 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  56 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  57
  58 int arm7_9_reinit_embeddedice(target_t *target)
  59 {
  60         armv4_5_common_t *armv4_5 = target->arch_info;
  61         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  62
  63         breakpoint_t *breakpoint = target->breakpoints;
  64
  65         arm7_9->wp_available = 2;
  66         arm7_9->wp0_used = 0;
  67         arm7_9->wp1_used = 0;
  68
  69         /* mark all hardware breakpoints as unset */
  70         while (breakpoint)
  71         {
  72                 if (breakpoint->type == BKPT_HARD)
  73                 {
  74                         breakpoint->set = 0;
  75                 }
  76                 breakpoint = breakpoint->next;
  77         }
  78
  79         if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
  80         {
  81                 arm7_9->sw_bkpts_enabled = 0;
  82                 arm7_9_enable_sw_bkpts(target);
  83         }
  84
  85         arm7_9->reinit_embeddedice = 0;
  86
  87         return ERROR_OK;
  88 }
  89
  90 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
  91 {
  92         target_t *target = priv;
  93         armv4_5_common_t *armv4_5 = target->arch_info;
  94         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  95
  96         /* a test-logic reset occured
  97          * the EmbeddedICE registers have been reset
  98          * hardware breakpoints have been cleared
  99          */
 100         if (event == JTAG_TRST_ASSERTED)
 101         {
 102                 arm7_9->reinit_embeddedice = 1;
 103         }
 104
 105         return ERROR_OK;
 106 }
 107
 108 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
 109 {
 110         armv4_5_common_t *armv4_5 = target->arch_info;
 111         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 112
 113         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 114         {
 115                 return -1;
 116         }
 117
 118         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 119         {
 120                 return -1;
 121         }
 122
 123         *armv4_5_p = armv4_5;
 124         *arm7_9_p = arm7_9;
 125
 126         return ERROR_OK;
 127 }
 128
 129 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 130 {
 131         armv4_5_common_t *armv4_5 = target->arch_info;
 132         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 133
 134         if (target->state != TARGET_HALTED)
 135         {
 136                 WARNING("target not halted");
 137                 return ERROR_TARGET_NOT_HALTED;
 138         }
 139
 140         if (arm7_9->force_hw_bkpts)
 141                 breakpoint->type = BKPT_HARD;
 142
 143         if (breakpoint->set)
 144         {
 145                 WARNING("breakpoint already set");
 146                 return ERROR_OK;
 147         }
 148
 149         if (breakpoint->type == BKPT_HARD)
 150         {
 151                 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
 152                 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 153                 if (!arm7_9->wp0_used)
 154                 {
 155                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
 156                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 157                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
 158                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 159                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 160
 161                         jtag_execute_queue();
 162                         arm7_9->wp0_used = 1;
 163                         breakpoint->set = 1;
 164                 }
 165                 else if (!arm7_9->wp1_used)
 166                 {
 167                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
 168                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 169                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
 170                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 171                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 172
 173                         jtag_execute_queue();
 174                         arm7_9->wp1_used = 1;
 175                         breakpoint->set = 2;
 176                 }
 177                 else
 178                 {
 179                         ERROR("BUG: no hardware comparator available");
 180                         return ERROR_OK;
 181                 }
 182         }
 183         else if (breakpoint->type == BKPT_SOFT)
 184         {
 185                 if (breakpoint->length == 4)
 186                 {
 187                         /* keep the original instruction in target endianness */
 188                         target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 189                         /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 190                         target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
 191                 }
 192                 else
 193                 {
 194                         /* keep the original instruction in target endianness */
 195                         target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 196                         /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 197                         target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt);
 198                 }
 199                 breakpoint->set = 1;
 200         }
 201
 202         return ERROR_OK;
 203
 204 }
 205
 206 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 207 {
 208         armv4_5_common_t *armv4_5 = target->arch_info;
 209         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 210
 211         if (target->state != TARGET_HALTED)
 212         {
 213                 WARNING("target not halted");
 214                 return ERROR_TARGET_NOT_HALTED;
 215         }
 216
 217         if (!breakpoint->set)
 218         {
 219                 WARNING("breakpoint not set");
 220                 return ERROR_OK;
 221         }
 222
 223         if (breakpoint->type == BKPT_HARD)
 224         {
 225                 if (breakpoint->set == 1)
 226                 {
 227                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 228                         jtag_execute_queue();
 229                         arm7_9->wp0_used = 0;
 230                 }
 231                 else if (breakpoint->set == 2)
 232                 {
 233                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 234                         jtag_execute_queue();
 235                         arm7_9->wp1_used = 0;
 236                 }
 237                 breakpoint->set = 0;
 238         }
 239         else
 240         {
 241                 /* restore original instruction (kept in target endianness) */
 242                 if (breakpoint->length == 4)
 243                 {
 244                         target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 245                 }
 246                 else
 247                 {
 248                         target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 249                 }
 250                 breakpoint->set = 0;
 251         }
 252
 253         return ERROR_OK;
 254 }
 255
 256 int arm7_9_add_breakpoint(struct target_s *target, u32 address, u32 length, enum breakpoint_type type)
 257 {
 258         armv4_5_common_t *armv4_5 = target->arch_info;
 259         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 260
 261         if (target->state != TARGET_HALTED)
 262         {
 263                 WARNING("target not halted");
 264                 return ERROR_TARGET_NOT_HALTED;
 265         }
 266
 267         if (arm7_9->force_hw_bkpts)
 268         {
 269                 type = BKPT_HARD;
 270         }
 271
 272         if ((type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
 273         {
 274                 INFO("sw breakpoint requested, but software breakpoints not enabled");
 275                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 276         }
 277
 278         if ((type == BKPT_HARD) && (arm7_9->wp_available < 1))
 279         {
 280                 INFO("no watchpoint unit available for hardware breakpoint");
 281                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 282         }
 283
 284         if (type == BKPT_HARD)
 285                 arm7_9->wp_available--;
 286
 287         if ((length != 2) && (length != 4))
 288         {
 289                 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 290                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 291         }
 292
 293         return ERROR_OK;
 294 }
 295
 296 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 297 {
 298         armv4_5_common_t *armv4_5 = target->arch_info;
 299         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 300
 301         if (target->state != TARGET_HALTED)
 302         {
 303                 WARNING("target not halted");
 304                 return ERROR_TARGET_NOT_HALTED;
 305         }
 306
 307         if (breakpoint->set)
 308         {
 309                 arm7_9_unset_breakpoint(target, breakpoint);
 310         }
 311
 312         if (breakpoint->type == BKPT_HARD)
 313                 arm7_9->wp_available++;
 314
 315         return ERROR_OK;
 316 }
 317
 318 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 319 {
 320         armv4_5_common_t *armv4_5 = target->arch_info;
 321         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 322         int rw_mask = 1;
 323         u32 mask;
 324
 325         mask = watchpoint->length - 1;
 326
 327         if (target->state != TARGET_HALTED)
 328         {
 329                 WARNING("target not halted");
 330                 return ERROR_TARGET_NOT_HALTED;
 331         }
 332
 333         if (watchpoint->rw == WPT_ACCESS)
 334                 rw_mask = 0;
 335         else
 336                 rw_mask = 1;
 337
 338         if (!arm7_9->wp0_used)
 339         {
 340                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
 341                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 342                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
 343                 if( watchpoint->mask != 0xffffffffu )
 344                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
 345                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 346                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 347
 348                 jtag_execute_queue();
 349                 watchpoint->set = 1;
 350                 arm7_9->wp0_used = 2;
 351         }
 352         else if (!arm7_9->wp1_used)
 353         {
 354                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
 355                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 356                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
 357                 if( watchpoint->mask != 0xffffffffu )
 358                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
 359                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 360                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 361
 362                 jtag_execute_queue();
 363                 watchpoint->set = 2;
 364                 arm7_9->wp1_used = 2;
 365         }
 366         else
 367         {
 368                 ERROR("BUG: no hardware comparator available");
 369                 return ERROR_OK;
 370         }
 371
 372         return ERROR_OK;
 373 }
 374
 375 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 376 {
 377         armv4_5_common_t *armv4_5 = target->arch_info;
 378         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 379
 380         if (target->state != TARGET_HALTED)
 381         {
 382                 WARNING("target not halted");
 383                 return ERROR_TARGET_NOT_HALTED;
 384         }
 385
 386         if (!watchpoint->set)
 387         {
 388                 WARNING("breakpoint not set");
 389                 return ERROR_OK;
 390         }
 391
 392         if (watchpoint->set == 1)
 393         {
 394                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 395                 jtag_execute_queue();
 396                 arm7_9->wp0_used = 0;
 397         }
 398         else if (watchpoint->set == 2)
 399         {
 400                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 401                 jtag_execute_queue();
 402                 arm7_9->wp1_used = 0;
 403         }
 404         watchpoint->set = 0;
 405
 406         return ERROR_OK;
 407 }
 408
 409 int arm7_9_add_watchpoint(struct target_s *target, u32 address, u32 length, enum watchpoint_rw rw)
 410 {
 411         armv4_5_common_t *armv4_5 = target->arch_info;
 412         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 413
 414         if (target->state != TARGET_HALTED)
 415         {
 416                 WARNING("target not halted");
 417                 return ERROR_TARGET_NOT_HALTED;
 418         }
 419
 420         if (arm7_9->wp_available < 1)
 421         {
 422                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 423         }
 424
 425         if ((length != 1) && (length != 2) && (length != 4))
 426         {
 427                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 428         }
 429
 430         arm7_9->wp_available--;
 431
 432         return ERROR_OK;
 433 }
 434
 435 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 436 {
 437         armv4_5_common_t *armv4_5 = target->arch_info;
 438         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 439
 440         if (target->state != TARGET_HALTED)
 441         {
 442                 WARNING("target not halted");
 443                 return ERROR_TARGET_NOT_HALTED;
 444         }
 445
 446         if (watchpoint->set)
 447         {
 448                 arm7_9_unset_watchpoint(target, watchpoint);
 449         }
 450
 451         arm7_9->wp_available++;
 452
 453         return ERROR_OK;
 454 }
 455
 456 int arm7_9_enable_sw_bkpts(struct target_s *target)
 457 {
 458         armv4_5_common_t *armv4_5 = target->arch_info;
 459         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 460         int retval;
 461
 462         if (arm7_9->sw_bkpts_enabled)
 463                 return ERROR_OK;
 464
 465         if (arm7_9->wp_available < 1)
 466         {
 467                 WARNING("can't enable sw breakpoints with no watchpoint unit available");
 468                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 469         }
 470         arm7_9->wp_available--;
 471
 472         if (!arm7_9->wp0_used)
 473         {
 474                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
 475                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
 476                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
 477                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 478                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 479                 arm7_9->sw_bkpts_enabled = 1;
 480                 arm7_9->wp0_used = 3;
 481         }
 482         else if (!arm7_9->wp1_used)
 483         {
 484                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
 485                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
 486                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
 487                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 488                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 489                 arm7_9->sw_bkpts_enabled = 2;
 490                 arm7_9->wp1_used = 3;
 491         }
 492         else
 493         {
 494                 ERROR("BUG: both watchpoints used, but wp_available >= 1");
 495                 exit(-1);
 496         }
 497
 498         if ((retval = jtag_execute_queue()) != ERROR_OK)
 499         {
 500                 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
 501                 exit(-1);
 502         };
 503
 504         return ERROR_OK;
 505 }
 506
 507 int arm7_9_disable_sw_bkpts(struct target_s *target)
 508 {
 509         armv4_5_common_t *armv4_5 = target->arch_info;
 510         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 511
 512         if (!arm7_9->sw_bkpts_enabled)
 513                 return ERROR_OK;
 514
 515         if (arm7_9->sw_bkpts_enabled == 1)
 516         {
 517                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 518                 arm7_9->sw_bkpts_enabled = 0;
 519                 arm7_9->wp0_used = 0;
 520                 arm7_9->wp_available++;
 521         }
 522         else if (arm7_9->sw_bkpts_enabled == 2)
 523         {
 524                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 525                 arm7_9->sw_bkpts_enabled = 0;
 526                 arm7_9->wp1_used = 0;
 527                 arm7_9->wp_available++;
 528         }
 529
 530         return ERROR_OK;
 531 }
 532
 533 int arm7_9_execute_sys_speed(struct target_s *target)
 534 {
 535         int timeout;
 536         int retval;
 537
 538         armv4_5_common_t *armv4_5 = target->arch_info;
 539         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 540         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 541         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 542
 543         /* set RESTART instruction */
 544         jtag_add_end_state(TAP_RTI);
 545         arm_jtag_set_instr(jtag_info, 0x4);
 546
 547         for (timeout=0; timeout<50; timeout++)
 548         {
 549                 /* read debug status register */
 550                 embeddedice_read_reg(dbg_stat);
 551                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 552                         return retval;
 553                 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 554                                    && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 555                         break;
 556                 usleep(100000);
 557         }
 558         if (timeout == 50)
 559         {
 560                 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 561                 return ERROR_TARGET_TIMEOUT;
 562         }
 563
 564         return ERROR_OK;
 565 }
 566
 567 int arm7_9_execute_fast_sys_speed(struct target_s *target)
 568 {
 569         u8 check_value[4], check_mask[4];
 570
 571         armv4_5_common_t *armv4_5 = target->arch_info;
 572         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 573         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 574         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 575
 576         /* set RESTART instruction */
 577         jtag_add_end_state(TAP_RTI);
 578         arm_jtag_set_instr(jtag_info, 0x4);
 579
 580         /* check for DBGACK and SYSCOMP set (others don't care) */
 581         buf_set_u32(check_value, 0, 32, 0x9);
 582         buf_set_u32(check_mask, 0, 32, 0x9);
 583
 584         /* read debug status register */
 585         embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
 586
 587         return ERROR_OK;
 588 }
 589
 590 enum target_state arm7_9_poll(target_t *target)
 591 {
 592         int retval;
 593         armv4_5_common_t *armv4_5 = target->arch_info;
 594         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 595         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 596
 597         if (arm7_9->reinit_embeddedice)
 598         {
 599                 arm7_9_reinit_embeddedice(target);
 600         }
 601
 602         /* read debug status register */
 603         embeddedice_read_reg(dbg_stat);
 604         if ((retval = jtag_execute_queue()) != ERROR_OK)
 605         {
 606                 switch (retval)
 607                 {
 608                         case ERROR_JTAG_QUEUE_FAILED:
 609                                 ERROR("JTAG queue failed while reading EmbeddedICE status register");
 610                                 exit(-1);
 611                                 break;
 612                         default:
 613                                 break;
 614                 }
 615         }
 616
 617         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 618         {
 619                 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
 620                 if ((target->state == TARGET_UNKNOWN))
 621                 {
 622                         WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
 623                         target->state = TARGET_RUNNING;
 624                 }
 625                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 626                 {
 627                         target->state = TARGET_HALTED;
 628                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 629                                 return retval;
 630
 631                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 632                 }
 633                 if (target->state == TARGET_DEBUG_RUNNING)
 634                 {
 635                         target->state = TARGET_HALTED;
 636                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 637                                 return retval;
 638
 639                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 640                 }
 641         }
 642         else
 643         {
 644                 if (target->state != TARGET_DEBUG_RUNNING)
 645                         target->state = TARGET_RUNNING;
 646         }
 647
 648         return target->state;
 649 }
 650
 651 int arm7_9_assert_reset(target_t *target)
 652 {
 653         int retval;
 654
 655         DEBUG("target->state: %s", target_state_strings[target->state]);
 656
 657         if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
 658         {
 659                 /* assert SRST and TRST */
 660                 /* system would get ouf sync if we didn't reset test-logic, too */
 661                 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
 662                 {
 663                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 664                         {
 665                                 WARNING("can't assert srst");
 666                                 return retval;
 667                         }
 668                         else
 669                         {
 670                                 ERROR("unknown error");
 671                                 exit(-1);
 672                         }
 673                 }
 674                 jtag_add_sleep(5000);
 675                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 676                 {
 677                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 678                         {
 679                                 WARNING("srst resets test logic, too");
 680                                 retval = jtag_add_reset(1, 1);
 681                         }
 682                 }
 683         }
 684         else
 685         {
 686                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 687                 {
 688                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 689                         {
 690                                 WARNING("srst resets test logic, too");
 691                                 retval = jtag_add_reset(1, 1);
 692                         }
 693
 694                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 695                         {
 696                                 WARNING("can't assert srst");
 697                                 return retval;
 698                         }
 699                         else if (retval != ERROR_OK)
 700                         {
 701                                 ERROR("unknown error");
 702                                 exit(-1);
 703                         }
 704                 }
 705         }
 706
 707         target->state = TARGET_RESET;
 708         jtag_add_sleep(50000);
 709
 710         armv4_5_invalidate_core_regs(target);
 711
 712         return ERROR_OK;
 713
 714 }
 715
 716 int arm7_9_deassert_reset(target_t *target)
 717 {
 718         DEBUG("target->state: %s", target_state_strings[target->state]);
 719
 720         /* deassert reset lines */
 721         jtag_add_reset(0, 0);
 722
 723         return ERROR_OK;
 724
 725 }
 726
 727 int arm7_9_soft_reset_halt(struct target_s *target)
 728 {
 729         armv4_5_common_t *armv4_5 = target->arch_info;
 730         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 731         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 732         int i;
 733
 734         if (target->state == TARGET_RUNNING)
 735         {
 736                 target->type->halt(target);
 737         }
 738
 739         while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
 740         {
 741                 embeddedice_read_reg(dbg_stat);
 742                 jtag_execute_queue();
 743         }
 744         target->state = TARGET_HALTED;
 745
 746         /* all register content is now invalid */
 747         armv4_5_invalidate_core_regs(target);
 748
 749         /* SVC, ARM state, IRQ and FIQ disabled */
 750         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 751         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 752         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 753
 754         /* start fetching from 0x0 */
 755         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 756         armv4_5->core_cache->reg_list[15].dirty = 1;
 757         armv4_5->core_cache->reg_list[15].valid = 1;
 758
 759         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 760         armv4_5->core_state = ARMV4_5_STATE_ARM;
 761
 762         /* reset registers */
 763         for (i = 0; i <= 14; i++)
 764         {
 765                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
 766                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
 767                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 768         }
 769
 770         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 771
 772         return ERROR_OK;
 773 }
 774
 775 int arm7_9_halt(target_t *target)
 776 {
 777         armv4_5_common_t *armv4_5 = target->arch_info;
 778         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 779         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 780
 781         DEBUG("target->state: %s", target_state_strings[target->state]);
 782
 783         if (target->state == TARGET_HALTED)
 784         {
 785                 WARNING("target was already halted");
 786                 return ERROR_TARGET_ALREADY_HALTED;
 787         }
 788
 789         if (target->state == TARGET_UNKNOWN)
 790         {
 791                 WARNING("target was in unknown state when halt was requested");
 792         }
 793
 794         if ((target->state == TARGET_RESET) && (jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_srst))
 795         {
 796                 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 797                 return ERROR_TARGET_FAILURE;
 798         }
 799
 800         if (arm7_9->use_dbgrq)
 801         {
 802                 /* program EmbeddedICE Debug Control Register to assert DBGRQ
 803                  */
 804                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
 805                 embeddedice_store_reg(dbg_ctrl);
 806         }
 807         else
 808         {
 809                 /* program watchpoint unit to match on any address
 810                  */
 811                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
 812                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
 813                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
 814                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
 815         }
 816
 817         target->debug_reason = DBG_REASON_DBGRQ;
 818
 819         return ERROR_OK;
 820 }
 821
 822 int arm7_9_clear_halt(target_t *target)
 823 {
 824         armv4_5_common_t *armv4_5 = target->arch_info;
 825         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 826         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 827
 828         if (arm7_9->use_dbgrq)
 829         {
 830                 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
 831                  */
 832                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 833                 embeddedice_store_reg(dbg_ctrl);
 834         }
 835         else
 836         {
 837                 /* restore registers if watchpoint unit 0 was in use
 838                  */
 839                 if (arm7_9->wp0_used)
 840                 {
 841                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
 842                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
 843                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
 844                 }
 845                 /* control value always has to be restored, as it was either disabled,
 846                  * or enabled with possibly different bits
 847                  */
 848                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 849         }
 850
 851         return ERROR_OK;
 852 }
 853
 854 int arm7_9_debug_entry(target_t *target)
 855 {
 856         int i;
 857         u32 context[16];
 858         u32* context_p[16];
 859         u32 r0_thumb, pc_thumb;
 860         u32 cpsr;
 861         int retval;
 862         /* get pointers to arch-specific information */
 863         armv4_5_common_t *armv4_5 = target->arch_info;
 864         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 865         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 866         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 867
 868 #ifdef _DEBUG_ARM7_9_
 869         DEBUG("");
 870 #endif
 871
 872         if (arm7_9->pre_debug_entry)
 873                 arm7_9->pre_debug_entry(target);
 874
 875         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 876          * ensure that DBGRQ is cleared
 877          */
 878         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 879         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 880         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 881         embeddedice_store_reg(dbg_ctrl);
 882
 883         arm7_9_clear_halt(target);
 884
 885         if ((retval = jtag_execute_queue()) != ERROR_OK)
 886         {
 887                 switch (retval)
 888                 {
 889                         case ERROR_JTAG_QUEUE_FAILED:
 890                                 ERROR("JTAG queue failed while writing EmbeddedICE control register");
 891                                 exit(-1);
 892                                 break;
 893                         default:
 894                                 break;
 895                 }
 896         }
 897
 898         if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
 899                 return retval;
 900
 901
 902         if (target->state != TARGET_HALTED)
 903         {
 904                 WARNING("target not halted");
 905                 return ERROR_TARGET_NOT_HALTED;
 906         }
 907
 908         /* if the target is in Thumb state, change to ARM state */
 909         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
 910         {
 911                 DEBUG("target entered debug from Thumb state");
 912                 /* Entered debug from Thumb mode */
 913                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
 914                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
 915                 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
 916         }
 917         else
 918         {
 919                 DEBUG("target entered debug from ARM state");
 920                 /* Entered debug from ARM mode */
 921                 armv4_5->core_state = ARMV4_5_STATE_ARM;
 922         }
 923
 924         for (i = 0; i < 16; i++)
 925                 context_p[i] = &context[i];
 926         /* save core registers (r0 - r15 of current core mode) */
 927         arm7_9->read_core_regs(target, 0xffff, context_p);
 928
 929         arm7_9->read_xpsr(target, &cpsr, 0);
 930
 931         if ((retval = jtag_execute_queue()) != ERROR_OK)
 932                 return retval;
 933
 934         /* if the core has been executing in Thumb state, set the T bit */
 935         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 936                 cpsr |= 0x20;
 937
 938         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
 939         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
 940         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 941
 942         armv4_5->core_mode = cpsr & 0x1f;
 943
 944         if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
 945         {
 946                 target->state = TARGET_UNKNOWN;
 947                 ERROR("cpsr contains invalid mode value - communication failure");
 948                 return ERROR_TARGET_FAILURE;
 949         }
 950
 951         DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
 952
 953         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 954         {
 955                 DEBUG("thumb state, applying fixups");
 956                 context[0] = r0_thumb;
 957                 context[15] = pc_thumb;
 958         } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 959         {
 960                 /* adjust value stored by STM */
 961                 context[15] -= 3 * 4;
 962         }
 963
 964         if ((target->debug_reason == DBG_REASON_BREAKPOINT)
 965                         || (target->debug_reason == DBG_REASON_SINGLESTEP)
 966                         || (target->debug_reason == DBG_REASON_WATCHPOINT)
 967                         || (target->debug_reason == DBG_REASON_WPTANDBKPT)
 968                         || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
 969                 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 970         else if (target->debug_reason == DBG_REASON_DBGRQ)
 971                 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 972         else
 973         {
 974                 ERROR("unknown debug reason: %i", target->debug_reason);
 975         }
 976
 977
 978         for (i=0; i<=15; i++)
 979         {
 980                 DEBUG("r%i: 0x%8.8x", i, context[i]);
 981                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
 982                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
 983                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 984         }
 985
 986         DEBUG("entered debug state at PC 0x%x", context[15]);
 987
 988         /* exceptions other than USR & SYS have a saved program status register */
 989         if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
 990         {
 991                 u32 spsr;
 992                 arm7_9->read_xpsr(target, &spsr, 1);
 993                 jtag_execute_queue();
 994                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
 995                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
 996                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
 997         }
 998
 999         /* r0 and r15 (pc) have to be restored later */
1000         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1001         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
1002
1003         if ((retval = jtag->execute_queue()) != ERROR_OK)
1004                 return retval;
1005
1006         if (arm7_9->post_debug_entry)
1007                 arm7_9->post_debug_entry(target);
1008
1009         return ERROR_OK;
1010 }
1011
1012 int arm7_9_full_context(target_t *target)
1013 {
1014         int i;
1015         int retval;
1016         armv4_5_common_t *armv4_5 = target->arch_info;
1017         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1018
1019         DEBUG("");
1020
1021         if (target->state != TARGET_HALTED)
1022         {
1023                 WARNING("target not halted");
1024                 return ERROR_TARGET_NOT_HALTED;
1025         }
1026
1027         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1028          * SYS shares registers with User, so we don't touch SYS
1029          */
1030         for(i = 0; i < 6; i++)
1031         {
1032                 u32 mask = 0;
1033                 u32* reg_p[16];
1034                 int j;
1035                 int valid = 1;
1036
1037                 /* check if there are invalid registers in the current mode
1038                  */
1039                 for (j = 0; j <= 16; j++)
1040                 {
1041                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1042                                 valid = 0;
1043                 }
1044
1045                 if (!valid)
1046                 {
1047                         u32 tmp_cpsr;
1048
1049                         /* change processor mode (and mask T bit) */
1050                         tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1051                         tmp_cpsr |= armv4_5_number_to_mode(i);
1052                         tmp_cpsr &= ~0x20;
1053                         arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1054
1055                         for (j = 0; j < 15; j++)
1056                         {
1057                                 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1058                                 {
1059                                         reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1060                                         mask |= 1 << j;
1061                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1062                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1063                                 }
1064                         }
1065
1066                         /* if only the PSR is invalid, mask is all zeroes */
1067                         if (mask)
1068                                 arm7_9->read_core_regs(target, mask, reg_p);
1069
1070                         /* check if the PSR has to be read */
1071                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1072                         {
1073                                 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1074                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1075                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1076                         }
1077                 }
1078         }
1079
1080         /* restore processor mode (mask T bit) */
1081         arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1082
1083         if ((retval = jtag_execute_queue()) != ERROR_OK)
1084         {
1085                 ERROR("JTAG failure");
1086                 exit(-1);
1087         }
1088         return ERROR_OK;
1089 }
1090
1091 int arm7_9_restore_context(target_t *target)
1092 {
1093         armv4_5_common_t *armv4_5 = target->arch_info;
1094         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1095         reg_t *reg;
1096         armv4_5_core_reg_t *reg_arch_info;
1097         enum armv4_5_mode current_mode = armv4_5->core_mode;
1098         int i, j;
1099         int dirty;
1100         int mode_change;
1101
1102         DEBUG("");
1103
1104         if (target->state != TARGET_HALTED)
1105         {
1106                 WARNING("target not halted");
1107                 return ERROR_TARGET_NOT_HALTED;
1108         }
1109
1110         if (arm7_9->pre_restore_context)
1111                 arm7_9->pre_restore_context(target);
1112
1113         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1114          * SYS shares registers with User, so we don't touch SYS
1115          */
1116         for (i = 0; i < 6; i++)
1117         {
1118                 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1119                 dirty = 0;
1120                 mode_change = 0;
1121                 /* check if there are dirty registers in the current mode
1122                 */
1123                 for (j = 0; j <= 16; j++)
1124                 {
1125                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1126                         reg_arch_info = reg->arch_info;
1127                         if (reg->dirty == 1)
1128                         {
1129                                 if (reg->valid == 1)
1130                                 {
1131                                         dirty = 1;
1132                                         DEBUG("examining dirty reg: %s", reg->name);
1133                                         if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1134                                                 && (reg_arch_info->mode != current_mode)
1135                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1136                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1137                                         {
1138                                                 mode_change = 1;
1139                                                 DEBUG("require mode change");
1140                                         }
1141                                 }
1142                                 else
1143                                 {
1144                                         ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1145                                         exit(-1);
1146                                 }
1147                         }
1148                 }
1149
1150                 if (dirty)
1151                 {
1152                         u32 mask = 0x0;
1153                         int num_regs = 0;
1154                         u32 regs[16];
1155
1156                         if (mode_change)
1157                         {
1158                                 u32 tmp_cpsr;
1159
1160                                 /* change processor mode (mask T bit) */
1161                                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1162                                 tmp_cpsr |= armv4_5_number_to_mode(i);
1163                                 tmp_cpsr &= ~0x20;
1164                                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1165                                 current_mode = armv4_5_number_to_mode(i);
1166                         }
1167
1168                         for (j = 0; j <= 14; j++)
1169                         {
1170                                 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1171                                 reg_arch_info = reg->arch_info;
1172
1173
1174                                 if (reg->dirty == 1)
1175                                 {
1176                                         regs[j] = buf_get_u32(reg->value, 0, 32);
1177                                         mask |= 1 << j;
1178                                         num_regs++;
1179                                         reg->dirty = 0;
1180                                         reg->valid = 1;
1181                                         DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1182                                 }
1183                         }
1184
1185                         if (mask)
1186                         {
1187                                 arm7_9->write_core_regs(target, mask, regs);
1188                         }
1189
1190                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1191                         reg_arch_info = reg->arch_info;
1192                         if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1193                         {
1194                                 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1195                                 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1196                         }
1197                 }
1198         }
1199
1200         if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1201         {
1202                 /* restore processor mode (mask T bit) */
1203                 u32 tmp_cpsr;
1204
1205                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1206                 tmp_cpsr |= armv4_5_number_to_mode(i);
1207                 tmp_cpsr &= ~0x20;
1208                 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1209                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1210         }
1211         else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1212         {
1213                 /* CPSR has been changed, full restore necessary (mask T bit) */
1214                 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1215                 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1216                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1217                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1218         }
1219
1220         /* restore PC */
1221         DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1222         arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1223         armv4_5->core_cache->reg_list[15].dirty = 0;
1224
1225         if (arm7_9->post_restore_context)
1226                 arm7_9->post_restore_context(target);
1227
1228         return ERROR_OK;
1229 }
1230
1231 int arm7_9_restart_core(struct target_s *target)
1232 {
1233         armv4_5_common_t *armv4_5 = target->arch_info;
1234         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1235         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1236
1237         /* set RESTART instruction */
1238         jtag_add_end_state(TAP_RTI);
1239         arm_jtag_set_instr(jtag_info, 0x4);
1240
1241         jtag_add_runtest(1, TAP_RTI);
1242         if ((jtag_execute_queue()) != ERROR_OK)
1243         {
1244                 exit(-1);
1245         }
1246
1247         return ERROR_OK;
1248 }
1249
1250 void arm7_9_enable_watchpoints(struct target_s *target)
1251 {
1252         watchpoint_t *watchpoint = target->watchpoints;
1253
1254         while (watchpoint)
1255         {
1256                 if (watchpoint->set == 0)
1257                         arm7_9_set_watchpoint(target, watchpoint);
1258                 watchpoint = watchpoint->next;
1259         }
1260 }
1261
1262 void arm7_9_enable_breakpoints(struct target_s *target)
1263 {
1264         breakpoint_t *breakpoint = target->breakpoints;
1265
1266         /* set any pending breakpoints */
1267         while (breakpoint)
1268         {
1269                 if (breakpoint->set == 0)
1270                         arm7_9_set_breakpoint(target, breakpoint);
1271                 breakpoint = breakpoint->next;
1272         }
1273 }
1274
1275 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1276 {
1277         breakpoint_t *breakpoint = target->breakpoints;
1278         watchpoint_t *watchpoint = target->watchpoints;
1279
1280         /* set any pending breakpoints */
1281         while (breakpoint)
1282         {
1283                 if (breakpoint->set != 0)
1284                         arm7_9_unset_breakpoint(target, breakpoint);
1285                 breakpoint = breakpoint->next;
1286         }
1287
1288         while (watchpoint)
1289         {
1290                 if (watchpoint->set != 0)
1291                         arm7_9_unset_watchpoint(target, watchpoint);
1292                 watchpoint = watchpoint->next;
1293         }
1294 }
1295
1296 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1297 {
1298         armv4_5_common_t *armv4_5 = target->arch_info;
1299         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1300         breakpoint_t *breakpoint = target->breakpoints;
1301         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1302
1303         DEBUG("");
1304
1305         if (target->state != TARGET_HALTED)
1306         {
1307                 WARNING("target not halted");
1308                 return ERROR_TARGET_NOT_HALTED;
1309         }
1310
1311         if (!debug_execution)
1312         {
1313                 target_free_all_working_areas(target);
1314         }
1315
1316         /* current = 1: continue on current pc, otherwise continue at <address> */
1317         if (!current)
1318                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1319
1320         /* the front-end may request us not to handle breakpoints */
1321         if (handle_breakpoints)
1322         {
1323                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1324                 {
1325                         DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1326                         arm7_9_unset_breakpoint(target, breakpoint);
1327
1328                         DEBUG("enable single-step");
1329                         arm7_9->enable_single_step(target);
1330
1331                         target->debug_reason = DBG_REASON_SINGLESTEP;
1332
1333                         arm7_9_restore_context(target);
1334
1335                         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1336                                 arm7_9->branch_resume(target);
1337                         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1338                         {
1339                                 arm7_9->branch_resume_thumb(target);
1340                         }
1341                         else
1342                         {
1343                                 ERROR("unhandled core state");
1344                                 exit(-1);
1345                         }
1346
1347                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1348                         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1349                         arm7_9_execute_sys_speed(target);
1350
1351                         DEBUG("disable single-step");
1352                         arm7_9->disable_single_step(target);
1353
1354                         arm7_9_debug_entry(target);
1355                         DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1356
1357                         DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1358                         arm7_9_set_breakpoint(target, breakpoint);
1359                 }
1360         }
1361
1362         /* enable any pending breakpoints and watchpoints */
1363         arm7_9_enable_breakpoints(target);
1364         arm7_9_enable_watchpoints(target);
1365
1366         arm7_9_restore_context(target);
1367
1368         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1369         {
1370                 arm7_9->branch_resume(target);
1371         }
1372         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1373         {
1374                 arm7_9->branch_resume_thumb(target);
1375         }
1376         else
1377         {
1378                 ERROR("unhandled core state");
1379                 exit(-1);
1380         }
1381
1382         /* deassert DBGACK and INTDIS */
1383         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1384         /* INTDIS only when we really resume, not during debug execution */
1385         if (!debug_execution)
1386                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1387         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1388
1389         arm7_9_restart_core(target);
1390
1391         target->debug_reason = DBG_REASON_NOTHALTED;
1392
1393         if (!debug_execution)
1394         {
1395                 /* registers are now invalid */
1396                 armv4_5_invalidate_core_regs(target);
1397                 target->state = TARGET_RUNNING;
1398                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1399         }
1400         else
1401         {
1402                 target->state = TARGET_DEBUG_RUNNING;
1403                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1404         }
1405
1406         DEBUG("target resumed");
1407
1408         return ERROR_OK;
1409 }
1410
1411 void arm7_9_enable_eice_step(target_t *target)
1412 {
1413         armv4_5_common_t *armv4_5 = target->arch_info;
1414         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1415
1416         /* setup an inverse breakpoint on the current PC
1417         * - comparator 1 matches the current address
1418         * - rangeout from comparator 1 is connected to comparator 0 rangein
1419         * - comparator 0 matches any address, as long as rangein is low */
1420         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1421         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1422         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1423         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1424         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1425         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1426         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1427         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1428         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1429 }
1430
1431 void arm7_9_disable_eice_step(target_t *target)
1432 {
1433         armv4_5_common_t *armv4_5 = target->arch_info;
1434         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1435
1436         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1437         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1438         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1439         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1440         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1441         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1442         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1443         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1444         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1445 }
1446
1447 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1448 {
1449         armv4_5_common_t *armv4_5 = target->arch_info;
1450         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1451         breakpoint_t *breakpoint = target->breakpoints;
1452
1453         if (target->state != TARGET_HALTED)
1454         {
1455                 WARNING("target not halted");
1456                 return ERROR_TARGET_NOT_HALTED;
1457         }
1458
1459         /* current = 1: continue on current pc, otherwise continue at <address> */
1460         if (!current)
1461                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1462
1463         /* the front-end may request us not to handle breakpoints */
1464         if (handle_breakpoints)
1465                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1466                         arm7_9_unset_breakpoint(target, breakpoint);
1467
1468         target->debug_reason = DBG_REASON_SINGLESTEP;
1469
1470         arm7_9_restore_context(target);
1471
1472         arm7_9->enable_single_step(target);
1473
1474         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1475         {
1476                 arm7_9->branch_resume(target);
1477         }
1478         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1479         {
1480                 arm7_9->branch_resume_thumb(target);
1481         }
1482         else
1483         {
1484                 ERROR("unhandled core state");
1485                 exit(-1);
1486         }
1487
1488         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1489
1490         arm7_9_execute_sys_speed(target);
1491         arm7_9->disable_single_step(target);
1492
1493         /* registers are now invalid */
1494         armv4_5_invalidate_core_regs(target);
1495
1496         arm7_9_debug_entry(target);
1497
1498         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1499
1500         if (breakpoint)
1501                 arm7_9_set_breakpoint(target, breakpoint);
1502
1503         DEBUG("target stepped");
1504
1505         return ERROR_OK;
1506
1507 }
1508
1509 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1510 {
1511         u32* reg_p[16];
1512         int retval;
1513         armv4_5_common_t *armv4_5 = target->arch_info;
1514         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1515         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1516
1517         if ((num < 0) || (num > 16))
1518                 return ERROR_INVALID_ARGUMENTS;
1519
1520         if ((mode != ARMV4_5_MODE_ANY)
1521                         && (mode != armv4_5->core_mode)
1522                         && (reg_mode != ARMV4_5_MODE_ANY))
1523         {
1524                 u32 tmp_cpsr;
1525
1526                 /* change processor mode (mask T bit) */
1527                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1528                 tmp_cpsr |= mode;
1529                 tmp_cpsr &= ~0x20;
1530                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1531         }
1532
1533         if ((num >= 0) && (num <= 15))
1534         {
1535                 /* read a normal core register */
1536                 reg_p[num] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value;
1537
1538                 arm7_9->read_core_regs(target, 1 << num, reg_p);
1539         }
1540         else
1541         {
1542                 /* read a program status register
1543                  * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1544                  */
1545                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1546                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1547
1548                 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, spsr);
1549         }
1550
1551         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1552         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1553
1554         if ((mode != ARMV4_5_MODE_ANY)
1555                         && (mode != armv4_5->core_mode)
1556                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1557                 /* restore processor mode (mask T bit) */
1558                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1559         }
1560
1561         if ((retval = jtag_execute_queue()) != ERROR_OK)
1562         {
1563                 ERROR("JTAG failure");
1564                 exit(-1);
1565         }
1566
1567         return ERROR_OK;
1568
1569 }
1570
1571 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1572 {
1573         u32 reg[16];
1574         int retval;
1575         armv4_5_common_t *armv4_5 = target->arch_info;
1576         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1577         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1578
1579         if ((num < 0) || (num > 16))
1580                 return ERROR_INVALID_ARGUMENTS;
1581
1582         if ((mode != ARMV4_5_MODE_ANY)
1583                         && (mode != armv4_5->core_mode)
1584                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1585                 u32 tmp_cpsr;
1586
1587                 /* change processor mode (mask T bit) */
1588                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1589                 tmp_cpsr |= mode;
1590                 tmp_cpsr &= ~0x20;
1591                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1592         }
1593
1594         if ((num >= 0) && (num <= 15))
1595         {
1596                 /* write a normal core register */
1597                 reg[num] = value;
1598
1599                 arm7_9->write_core_regs(target, 1 << num, reg);
1600         }
1601         else
1602         {
1603                 /* write a program status register
1604                 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1605                 */
1606                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1607                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1608
1609                 /* if we're writing the CPSR, mask the T bit */
1610                 if (!spsr)
1611                         value &= ~0x20;
1612
1613                 arm7_9->write_xpsr(target, value, spsr);
1614         }
1615
1616         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1617         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1618
1619         if ((mode != ARMV4_5_MODE_ANY)
1620                         && (mode != armv4_5->core_mode)
1621                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1622                 /* restore processor mode (mask T bit) */
1623                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1624         }
1625
1626         if ((retval = jtag_execute_queue()) != ERROR_OK)
1627         {
1628                 ERROR("JTAG failure");
1629                 exit(-1);
1630         }
1631
1632         return ERROR_OK;
1633
1634 }
1635
1636 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1637 {
1638         armv4_5_common_t *armv4_5 = target->arch_info;
1639         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1640
1641         u32 reg[16];
1642         int num_accesses = 0;
1643         int thisrun_accesses;
1644         int i;
1645         u32 cpsr;
1646         int retval;
1647         int last_reg = 0;
1648
1649         DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1650
1651         if (target->state != TARGET_HALTED)
1652         {
1653                 WARNING("target not halted");
1654                 return ERROR_TARGET_NOT_HALTED;
1655         }
1656
1657         /* sanitize arguments */
1658         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1659                 return ERROR_INVALID_ARGUMENTS;
1660
1661         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1662                 return ERROR_TARGET_UNALIGNED_ACCESS;
1663
1664         /* load the base register with the address of the first word */
1665         reg[0] = address;
1666         arm7_9->write_core_regs(target, 0x1, reg);
1667
1668         switch (size)
1669         {
1670                 case 4:
1671                         while (num_accesses < count)
1672                         {
1673                                 u32 reg_list;
1674                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1675                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1676
1677                                 if (last_reg <= thisrun_accesses)
1678                                         last_reg = thisrun_accesses;
1679
1680                                 arm7_9->load_word_regs(target, reg_list);
1681
1682                                 /* fast memory reads are only safe when the target is running
1683                                  * from a sufficiently high clock (32 kHz is usually too slow)
1684                                  */
1685                                 if (arm7_9->fast_memory_access)
1686                                         arm7_9_execute_fast_sys_speed(target);
1687                                 else
1688                                         arm7_9_execute_sys_speed(target);
1689
1690                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1691
1692                                 /* advance buffer, count number of accesses */
1693                                 buffer += thisrun_accesses * 4;
1694                                 num_accesses += thisrun_accesses;
1695                         }
1696                         break;
1697                 case 2:
1698                         while (num_accesses < count)
1699                         {
1700                                 u32 reg_list;
1701                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1702                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1703
1704                                 for (i = 1; i <= thisrun_accesses; i++)
1705                                 {
1706                                         if (i > last_reg)
1707                                                 last_reg = i;
1708                                         arm7_9->load_hword_reg(target, i);
1709                                         /* fast memory reads are only safe when the target is running
1710                                          * from a sufficiently high clock (32 kHz is usually too slow)
1711                                          */
1712                                         if (arm7_9->fast_memory_access)
1713                                                 arm7_9_execute_fast_sys_speed(target);
1714                                         else
1715                                                 arm7_9_execute_sys_speed(target);
1716                                 }
1717
1718                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1719
1720                                 /* advance buffer, count number of accesses */
1721                                 buffer += thisrun_accesses * 2;
1722                                 num_accesses += thisrun_accesses;
1723                         }
1724                         break;
1725                 case 1:
1726                         while (num_accesses < count)
1727                         {
1728                                 u32 reg_list;
1729                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1730                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1731
1732                                 for (i = 1; i <= thisrun_accesses; i++)
1733                                 {
1734                                         if (i > last_reg)
1735                                                 last_reg = i;
1736                                         arm7_9->load_byte_reg(target, i);
1737                                         /* fast memory reads are only safe when the target is running
1738                                          * from a sufficiently high clock (32 kHz is usually too slow)
1739                                          */
1740                                         if (arm7_9->fast_memory_access)
1741                                                 arm7_9_execute_fast_sys_speed(target);
1742                                         else
1743                                                 arm7_9_execute_sys_speed(target);
1744                                 }
1745
1746                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1747
1748                                 /* advance buffer, count number of accesses */
1749                                 buffer += thisrun_accesses * 1;
1750                                 num_accesses += thisrun_accesses;
1751                         }
1752                         break;
1753                 default:
1754                         ERROR("BUG: we shouldn't get here");
1755                         exit(-1);
1756                         break;
1757         }
1758
1759         for (i=0; i<=last_reg; i++)
1760                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1761
1762         arm7_9->read_xpsr(target, &cpsr, 0);
1763         if ((retval = jtag_execute_queue()) != ERROR_OK)
1764         {
1765                 ERROR("JTAG error while reading cpsr");
1766                 exit(-1);
1767         }
1768
1769         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1770         {
1771                 ERROR("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1772
1773                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1774
1775                 return ERROR_TARGET_DATA_ABORT;
1776         }
1777
1778         return ERROR_OK;
1779 }
1780
1781 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1782 {
1783         armv4_5_common_t *armv4_5 = target->arch_info;
1784         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1785         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1786
1787         u32 reg[16];
1788         int num_accesses = 0;
1789         int thisrun_accesses;
1790         int i;
1791         u32 cpsr;
1792         int retval;
1793         int last_reg = 0;
1794
1795         DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1796
1797         if (target->state != TARGET_HALTED)
1798         {
1799                 WARNING("target not halted");
1800                 return ERROR_TARGET_NOT_HALTED;
1801         }
1802
1803         /* sanitize arguments */
1804         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1805                 return ERROR_INVALID_ARGUMENTS;
1806
1807         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1808                 return ERROR_TARGET_UNALIGNED_ACCESS;
1809
1810         /* load the base register with the address of the first word */
1811         reg[0] = address;
1812         arm7_9->write_core_regs(target, 0x1, reg);
1813
1814         /* Clear DBGACK, to make sure memory fetches work as expected */
1815         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1816         embeddedice_store_reg(dbg_ctrl);
1817
1818         switch (size)
1819         {
1820                 case 4:
1821                         while (num_accesses < count)
1822                         {
1823                                 u32 reg_list;
1824                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1825                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1826
1827                                 for (i = 1; i <= thisrun_accesses; i++)
1828                                 {
1829                                         if (i > last_reg)
1830                                                 last_reg = i;
1831                                         reg[i] = target_buffer_get_u32(target, buffer);
1832                                         buffer += 4;
1833                                 }
1834
1835                                 arm7_9->write_core_regs(target, reg_list, reg);
1836
1837                                 arm7_9->store_word_regs(target, reg_list);
1838
1839                                 /* fast memory writes are only safe when the target is running
1840                                  * from a sufficiently high clock (32 kHz is usually too slow)
1841                                  */
1842                                 if (arm7_9->fast_memory_access)
1843                                         arm7_9_execute_fast_sys_speed(target);
1844                                 else
1845                                         arm7_9_execute_sys_speed(target);
1846
1847                                 num_accesses += thisrun_accesses;
1848                         }
1849                         break;
1850                 case 2:
1851                         while (num_accesses < count)
1852                         {
1853                                 u32 reg_list;
1854                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1855                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1856
1857                                 for (i = 1; i <= thisrun_accesses; i++)
1858                                 {
1859                                         if (i > last_reg)
1860                                                 last_reg = i;
1861                                         reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1862                                         buffer += 2;
1863                                 }
1864
1865                                 arm7_9->write_core_regs(target, reg_list, reg);
1866
1867                                 for (i = 1; i <= thisrun_accesses; i++)
1868                                 {
1869                                         arm7_9->store_hword_reg(target, i);
1870
1871                                         /* fast memory writes are only safe when the target is running
1872                                          * from a sufficiently high clock (32 kHz is usually too slow)
1873                                          */
1874                                         if (arm7_9->fast_memory_access)
1875                                                 arm7_9_execute_fast_sys_speed(target);
1876                                         else
1877                                                 arm7_9_execute_sys_speed(target);
1878                                 }
1879
1880                                 num_accesses += thisrun_accesses;
1881                         }
1882                         break;
1883                 case 1:
1884                         while (num_accesses < count)
1885                         {
1886                                 u32 reg_list;
1887                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1888                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1889
1890                                 for (i = 1; i <= thisrun_accesses; i++)
1891                                 {
1892                                         if (i > last_reg)
1893                                                 last_reg = i;
1894                                         reg[i] = *buffer++ & 0xff;
1895                                 }
1896
1897                                 arm7_9->write_core_regs(target, reg_list, reg);
1898
1899                                 for (i = 1; i <= thisrun_accesses; i++)
1900                                 {
1901                                         arm7_9->store_byte_reg(target, i);
1902                                         /* fast memory writes are only safe when the target is running
1903                                          * from a sufficiently high clock (32 kHz is usually too slow)
1904                                          */
1905                                         if (arm7_9->fast_memory_access)
1906                                                 arm7_9_execute_fast_sys_speed(target);
1907                                         else
1908                                                 arm7_9_execute_sys_speed(target);
1909                                 }
1910
1911                                 num_accesses += thisrun_accesses;
1912                         }
1913                         break;
1914                 default:
1915                         ERROR("BUG: we shouldn't get here");
1916                         exit(-1);
1917                         break;
1918         }
1919
1920         /* Re-Set DBGACK */
1921         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1922         embeddedice_store_reg(dbg_ctrl);
1923
1924         for (i=0; i<=last_reg; i++)
1925                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1926
1927         arm7_9->read_xpsr(target, &cpsr, 0);
1928         if ((retval = jtag_execute_queue()) != ERROR_OK)
1929         {
1930                 ERROR("JTAG error while reading cpsr");
1931                 exit(-1);
1932         }
1933
1934         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1935         {
1936                 ERROR("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1937
1938                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1939
1940                 return ERROR_TARGET_DATA_ABORT;
1941         }
1942
1943         return ERROR_OK;
1944 }
1945
1946 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
1947 {
1948         armv4_5_common_t *armv4_5 = target->arch_info;
1949         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1950         enum armv4_5_state core_state = armv4_5->core_state;
1951         u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
1952         u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
1953         u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1954         int i;
1955
1956         u32 dcc_code[] =
1957         {
1958                 /* MRC      TST         BNE         MRC         STR         B */
1959                 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1960         };
1961
1962         if (!arm7_9->dcc_downloads)
1963                 return target->type->write_memory(target, address, 4, count, buffer);
1964
1965         /* regrab previously allocated working_area, or allocate a new one */
1966         if (!arm7_9->dcc_working_area)
1967         {
1968                 u8 dcc_code_buf[6 * 4];
1969
1970                 /* make sure we have a working area */
1971                 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
1972                 {
1973                         INFO("no working area available, falling back to memory writes");
1974                         return target->type->write_memory(target, address, 4, count, buffer);
1975                 }
1976
1977                 /* copy target instructions to target endianness */
1978                 for (i = 0; i < 6; i++)
1979                 {
1980                         target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
1981                 }
1982
1983                 /* write DCC code to working area */
1984                 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
1985         }
1986
1987         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
1988         armv4_5->core_cache->reg_list[0].valid = 1;
1989         armv4_5->core_cache->reg_list[0].dirty = 1;
1990         armv4_5->core_state = ARMV4_5_STATE_ARM;
1991
1992         arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
1993
1994         for (i = 0; i < count; i++)
1995         {
1996                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
1997                 buffer += 4;
1998         }
1999
2000         target->type->halt(target);
2001
2002         while (target->state != TARGET_HALTED)
2003                 target->type->poll(target);
2004
2005         /* restore target state */
2006         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2007         armv4_5->core_cache->reg_list[0].valid = 1;
2008         armv4_5->core_cache->reg_list[0].dirty = 1;
2009         buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2010         armv4_5->core_cache->reg_list[1].valid = 1;
2011         armv4_5->core_cache->reg_list[1].dirty = 1;
2012         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2013         armv4_5->core_cache->reg_list[15].valid = 1;
2014         armv4_5->core_cache->reg_list[15].dirty = 1;
2015         armv4_5->core_state = core_state;
2016
2017         return ERROR_OK;
2018 }
2019
2020 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2021 {
2022         command_t *arm7_9_cmd;
2023
2024         arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2025
2026         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2027         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2028
2029         register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2030
2031         register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2032         register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2033         register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2034                 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2035         register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2036                  COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2037         register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2038                  COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2039         register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2040                 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2041
2042         armv4_5_register_commands(cmd_ctx);
2043
2044         return ERROR_OK;
2045 }
2046
2047 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2048 {
2049         u32 value;
2050         int spsr;
2051         int retval;
2052         target_t *target = get_current_target(cmd_ctx);
2053         armv4_5_common_t *armv4_5;
2054         arm7_9_common_t *arm7_9;
2055
2056         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2057         {
2058                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2059                 return ERROR_OK;
2060         }
2061
2062         if (target->state != TARGET_HALTED)
2063         {
2064                 command_print(cmd_ctx, "can't write registers while running");
2065                 return ERROR_OK;
2066         }
2067
2068         if (argc < 2)
2069         {
2070                 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2071                 return ERROR_OK;
2072         }
2073
2074         value = strtoul(args[0], NULL, 0);
2075         spsr = strtol(args[1], NULL, 0);
2076
2077         /* if we're writing the CPSR, mask the T bit */
2078         if (!spsr)
2079                 value &= ~0x20;
2080
2081         arm7_9->write_xpsr(target, value, spsr);
2082         if ((retval = jtag_execute_queue()) != ERROR_OK)
2083         {
2084                 ERROR("JTAG error while writing to xpsr");
2085                 exit(-1);
2086         }
2087
2088         return ERROR_OK;
2089 }
2090
2091 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2092 {
2093         u32 value;
2094         int rotate;
2095         int spsr;
2096         int retval;
2097         target_t *target = get_current_target(cmd_ctx);
2098         armv4_5_common_t *armv4_5;
2099         arm7_9_common_t *arm7_9;
2100
2101         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2102         {
2103                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2104                 return ERROR_OK;
2105         }
2106
2107         if (target->state != TARGET_HALTED)
2108         {
2109                 command_print(cmd_ctx, "can't write registers while running");
2110                 return ERROR_OK;
2111         }
2112
2113         if (argc < 3)
2114         {
2115                 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2116                 return ERROR_OK;
2117         }
2118
2119         value = strtoul(args[0], NULL, 0);
2120         rotate = strtol(args[1], NULL, 0);
2121         spsr = strtol(args[2], NULL, 0);
2122
2123         arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2124         if ((retval = jtag_execute_queue()) != ERROR_OK)
2125         {
2126                 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2127                 exit(-1);
2128         }
2129
2130         return ERROR_OK;
2131 }
2132
2133 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2134 {
2135         u32 value;
2136         u32 mode;
2137         int num;
2138         target_t *target = get_current_target(cmd_ctx);
2139         armv4_5_common_t *armv4_5;
2140         arm7_9_common_t *arm7_9;
2141
2142         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2143         {
2144                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2145                 return ERROR_OK;
2146         }
2147
2148         if (target->state != TARGET_HALTED)
2149         {
2150                 command_print(cmd_ctx, "can't write registers while running");
2151                 return ERROR_OK;
2152         }
2153
2154         if (argc < 3)
2155         {
2156                 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2157                 return ERROR_OK;
2158         }
2159
2160         num = strtol(args[0], NULL, 0);
2161         mode = strtoul(args[1], NULL, 0);
2162         value = strtoul(args[2], NULL, 0);
2163
2164         arm7_9_write_core_reg(target, num, mode, value);
2165
2166         return ERROR_OK;
2167 }
2168
2169 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2170 {
2171         target_t *target = get_current_target(cmd_ctx);
2172         armv4_5_common_t *armv4_5;
2173         arm7_9_common_t *arm7_9;
2174
2175         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2176         {
2177                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2178                 return ERROR_OK;
2179         }
2180
2181         if (argc == 0)
2182         {
2183                 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2184                 return ERROR_OK;
2185         }
2186
2187         if (strcmp("enable", args[0]) == 0)
2188         {
2189                 if (arm7_9->sw_bkpts_use_wp)
2190                 {
2191                         arm7_9_enable_sw_bkpts(target);
2192                 }
2193                 else
2194                 {
2195                         arm7_9->sw_bkpts_enabled = 1;
2196                 }
2197         }
2198         else if (strcmp("disable", args[0]) == 0)
2199         {
2200                 if (arm7_9->sw_bkpts_use_wp)
2201                 {
2202                         arm7_9_disable_sw_bkpts(target);
2203                 }
2204                 else
2205                 {
2206                         arm7_9->sw_bkpts_enabled = 0;
2207                 }
2208         }
2209         else
2210         {
2211                 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2212         }
2213
2214         command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2215
2216         return ERROR_OK;
2217 }
2218
2219 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2220 {
2221         target_t *target = get_current_target(cmd_ctx);
2222         armv4_5_common_t *armv4_5;
2223         arm7_9_common_t *arm7_9;
2224
2225         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2226         {
2227                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2228                 return ERROR_OK;
2229         }
2230
2231         if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2232         {
2233                 arm7_9->force_hw_bkpts = 1;
2234                 if (arm7_9->sw_bkpts_use_wp)
2235                 {
2236                         arm7_9_disable_sw_bkpts(target);
2237                 }
2238         }
2239         else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2240         {
2241                 arm7_9->force_hw_bkpts = 0;
2242         }
2243         else
2244         {
2245                 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2246         }
2247
2248         command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2249
2250         return ERROR_OK;
2251 }
2252
2253 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2254 {
2255         target_t *target = get_current_target(cmd_ctx);
2256         armv4_5_common_t *armv4_5;
2257         arm7_9_common_t *arm7_9;
2258
2259         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2260         {
2261                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2262                 return ERROR_OK;
2263         }
2264
2265         if (argc > 0)
2266         {
2267                 if (strcmp("enable", args[0]) == 0)
2268                 {
2269                         arm7_9->use_dbgrq = 1;
2270                 }
2271                 else if (strcmp("disable", args[0]) == 0)
2272                 {
2273                         arm7_9->use_dbgrq = 0;
2274                 }
2275                 else
2276                 {
2277                         command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2278                 }
2279         }
2280
2281         command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2282
2283         return ERROR_OK;
2284 }
2285
2286 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2287 {
2288         target_t *target = get_current_target(cmd_ctx);
2289         armv4_5_common_t *armv4_5;
2290         arm7_9_common_t *arm7_9;
2291
2292         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2293         {
2294                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2295                 return ERROR_OK;
2296         }
2297
2298         if (argc > 0)
2299         {
2300                 if (strcmp("enable", args[0]) == 0)
2301                 {
2302                         arm7_9->fast_memory_access = 1;
2303                 }
2304                 else if (strcmp("disable", args[0]) == 0)
2305                 {
2306                         arm7_9->fast_memory_access = 0;
2307                 }
2308                 else
2309                 {
2310                         command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2311                 }
2312         }
2313
2314         command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2315
2316         return ERROR_OK;
2317 }
2318
2319 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2320 {
2321         target_t *target = get_current_target(cmd_ctx);
2322         armv4_5_common_t *armv4_5;
2323         arm7_9_common_t *arm7_9;
2324
2325         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2326         {
2327                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2328                 return ERROR_OK;
2329         }
2330
2331         if (argc > 0)
2332         {
2333                 if (strcmp("enable", args[0]) == 0)
2334                 {
2335                         arm7_9->dcc_downloads = 1;
2336                 }
2337                 else if (strcmp("disable", args[0]) == 0)
2338                 {
2339                         arm7_9->dcc_downloads = 0;
2340                 }
2341                 else
2342                 {
2343                         command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2344                 }
2345         }
2346
2347         command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2348
2349         return ERROR_OK;
2350 }
2351
2352 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2353 {
2354         armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2355
2356         arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2357
2358         arm_jtag_setup_connection(&arm7_9->jtag_info);
2359         arm7_9->wp_available = 2;
2360         arm7_9->wp0_used = 0;
2361         arm7_9->wp1_used = 0;
2362         arm7_9->force_hw_bkpts = 0;
2363         arm7_9->use_dbgrq = 0;
2364         arm7_9->has_etm = 0;
2365
2366         arm7_9->reinit_embeddedice = 0;
2367
2368         arm7_9->dcc_working_area = NULL;
2369
2370         arm7_9->fast_memory_access = 0;
2371         arm7_9->dcc_downloads = 0;
2372
2373         jtag_register_event_callback(arm7_9_jtag_callback, target);
2374
2375         armv4_5->arch_info = arm7_9;
2376         armv4_5->read_core_reg = arm7_9_read_core_reg;
2377         armv4_5->write_core_reg = arm7_9_write_core_reg;
2378         armv4_5->full_context = arm7_9_full_context;
2379
2380         armv4_5_init_arch_info(target, armv4_5);
2381
2382         return ERROR_OK;
2383 }