1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
28 #include "target_request.h"
33 #include "arm7_9_common.h"
34 #include "breakpoints.h"
40 #include <sys/types.h>
45 int arm7_9_debug_entry(target_t *target);
46 int arm7_9_enable_sw_bkpts(struct target_s *target);
48 /* command handler forward declarations */
49 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
60 int arm7_9_reinit_embeddedice(target_t *target)
62 armv4_5_common_t *armv4_5 = target->arch_info;
63 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
65 breakpoint_t *breakpoint = target->breakpoints;
67 arm7_9->wp_available = 2;
71 /* mark all hardware breakpoints as unset */
74 if (breakpoint->type == BKPT_HARD)
78 breakpoint = breakpoint->next;
81 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
83 arm7_9->sw_bkpts_enabled = 0;
84 arm7_9_enable_sw_bkpts(target);
90 /* set things up after a reset / on startup */
91 int arm7_9_setup(target_t *target)
93 /* a test-logic reset have occured
94 * the EmbeddedICE registers have been reset
95 * hardware breakpoints have been cleared
97 return arm7_9_reinit_embeddedice(target);
100 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
102 armv4_5_common_t *armv4_5 = target->arch_info;
103 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
105 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
110 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
115 *armv4_5_p = armv4_5;
121 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
123 armv4_5_common_t *armv4_5 = target->arch_info;
124 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
126 if (target->state != TARGET_HALTED)
128 LOG_WARNING("target not halted");
129 return ERROR_TARGET_NOT_HALTED;
132 if (arm7_9->force_hw_bkpts)
133 breakpoint->type = BKPT_HARD;
137 LOG_WARNING("breakpoint already set");
141 if (breakpoint->type == BKPT_HARD)
143 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
144 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
145 if (!arm7_9->wp0_used)
147 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
148 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
149 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
150 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
151 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
153 jtag_execute_queue();
154 arm7_9->wp0_used = 1;
157 else if (!arm7_9->wp1_used)
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
162 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
163 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
165 jtag_execute_queue();
166 arm7_9->wp1_used = 1;
171 LOG_ERROR("BUG: no hardware comparator available");
175 else if (breakpoint->type == BKPT_SOFT)
177 if (breakpoint->length == 4)
179 u32 verify = 0xffffffff;
180 /* keep the original instruction in target endianness */
181 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
182 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
183 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
185 target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
186 if (verify != arm7_9->arm_bkpt)
188 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
195 /* keep the original instruction in target endianness */
196 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
197 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
198 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
200 target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
201 if (verify != arm7_9->thumb_bkpt)
203 LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
214 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
216 armv4_5_common_t *armv4_5 = target->arch_info;
217 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
219 if (target->state != TARGET_HALTED)
221 LOG_WARNING("target not halted");
222 return ERROR_TARGET_NOT_HALTED;
225 if (!breakpoint->set)
227 LOG_WARNING("breakpoint not set");
231 if (breakpoint->type == BKPT_HARD)
233 if (breakpoint->set == 1)
235 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
236 jtag_execute_queue();
237 arm7_9->wp0_used = 0;
239 else if (breakpoint->set == 2)
241 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
242 jtag_execute_queue();
243 arm7_9->wp1_used = 0;
249 /* restore original instruction (kept in target endianness) */
250 if (breakpoint->length == 4)
253 /* check that user program as not modified breakpoint instruction */
254 target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr);
255 if (current_instr==arm7_9->arm_bkpt)
256 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
261 /* check that user program as not modified breakpoint instruction */
262 target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr);
263 if (current_instr==arm7_9->thumb_bkpt)
264 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
272 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
274 armv4_5_common_t *armv4_5 = target->arch_info;
275 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
277 if (target->state != TARGET_HALTED)
279 LOG_WARNING("target not halted");
280 return ERROR_TARGET_NOT_HALTED;
283 if (arm7_9->force_hw_bkpts)
285 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
286 breakpoint->type = BKPT_HARD;
289 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
291 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
292 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
295 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
297 LOG_INFO("no watchpoint unit available for hardware breakpoint");
298 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
301 if ((breakpoint->length != 2) && (breakpoint->length != 4))
303 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
304 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
307 if (breakpoint->type == BKPT_HARD)
308 arm7_9->wp_available--;
313 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
315 armv4_5_common_t *armv4_5 = target->arch_info;
316 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
318 if (target->state != TARGET_HALTED)
320 LOG_WARNING("target not halted");
321 return ERROR_TARGET_NOT_HALTED;
326 arm7_9_unset_breakpoint(target, breakpoint);
329 if (breakpoint->type == BKPT_HARD)
330 arm7_9->wp_available++;
335 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
337 armv4_5_common_t *armv4_5 = target->arch_info;
338 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
342 mask = watchpoint->length - 1;
344 if (target->state != TARGET_HALTED)
346 LOG_WARNING("target not halted");
347 return ERROR_TARGET_NOT_HALTED;
350 if (watchpoint->rw == WPT_ACCESS)
355 if (!arm7_9->wp0_used)
357 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
359 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
360 if( watchpoint->mask != 0xffffffffu )
361 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
363 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
365 jtag_execute_queue();
367 arm7_9->wp0_used = 2;
369 else if (!arm7_9->wp1_used)
371 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
372 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
373 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
374 if( watchpoint->mask != 0xffffffffu )
375 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
376 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
377 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
379 jtag_execute_queue();
381 arm7_9->wp1_used = 2;
385 LOG_ERROR("BUG: no hardware comparator available");
392 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
394 armv4_5_common_t *armv4_5 = target->arch_info;
395 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
397 if (target->state != TARGET_HALTED)
399 LOG_WARNING("target not halted");
400 return ERROR_TARGET_NOT_HALTED;
403 if (!watchpoint->set)
405 LOG_WARNING("breakpoint not set");
409 if (watchpoint->set == 1)
411 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
412 jtag_execute_queue();
413 arm7_9->wp0_used = 0;
415 else if (watchpoint->set == 2)
417 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
418 jtag_execute_queue();
419 arm7_9->wp1_used = 0;
426 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
428 armv4_5_common_t *armv4_5 = target->arch_info;
429 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
431 if (target->state != TARGET_HALTED)
433 LOG_WARNING("target not halted");
434 return ERROR_TARGET_NOT_HALTED;
437 if (arm7_9->wp_available < 1)
439 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
442 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
447 arm7_9->wp_available--;
452 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
454 armv4_5_common_t *armv4_5 = target->arch_info;
455 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
457 if (target->state != TARGET_HALTED)
459 LOG_WARNING("target not halted");
460 return ERROR_TARGET_NOT_HALTED;
465 arm7_9_unset_watchpoint(target, watchpoint);
468 arm7_9->wp_available++;
473 int arm7_9_enable_sw_bkpts(struct target_s *target)
475 armv4_5_common_t *armv4_5 = target->arch_info;
476 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
479 if (arm7_9->sw_bkpts_enabled)
482 if (arm7_9->wp_available < 1)
484 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
487 arm7_9->wp_available--;
489 if (!arm7_9->wp0_used)
491 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
492 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
493 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
494 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
495 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
496 arm7_9->sw_bkpts_enabled = 1;
497 arm7_9->wp0_used = 3;
499 else if (!arm7_9->wp1_used)
501 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
502 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
503 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
504 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
505 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
506 arm7_9->sw_bkpts_enabled = 2;
507 arm7_9->wp1_used = 3;
511 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
515 if ((retval = jtag_execute_queue()) != ERROR_OK)
517 LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
524 int arm7_9_disable_sw_bkpts(struct target_s *target)
526 armv4_5_common_t *armv4_5 = target->arch_info;
527 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
529 if (!arm7_9->sw_bkpts_enabled)
532 if (arm7_9->sw_bkpts_enabled == 1)
534 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
535 arm7_9->sw_bkpts_enabled = 0;
536 arm7_9->wp0_used = 0;
537 arm7_9->wp_available++;
539 else if (arm7_9->sw_bkpts_enabled == 2)
541 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
542 arm7_9->sw_bkpts_enabled = 0;
543 arm7_9->wp1_used = 0;
544 arm7_9->wp_available++;
550 int arm7_9_execute_sys_speed(struct target_s *target)
555 armv4_5_common_t *armv4_5 = target->arch_info;
556 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
557 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
558 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
560 /* set RESTART instruction */
561 jtag_add_end_state(TAP_RTI);
562 if (arm7_9->need_bypass_before_restart) {
563 arm7_9->need_bypass_before_restart = 0;
564 arm_jtag_set_instr(jtag_info, 0xf, NULL);
566 arm_jtag_set_instr(jtag_info, 0x4, NULL);
568 for (timeout=0; timeout<50; timeout++)
570 /* read debug status register */
571 embeddedice_read_reg(dbg_stat);
572 if ((retval = jtag_execute_queue()) != ERROR_OK)
574 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
575 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
581 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
582 return ERROR_TARGET_TIMEOUT;
588 int arm7_9_execute_fast_sys_speed(struct target_s *target)
591 static u8 check_value[4], check_mask[4];
593 armv4_5_common_t *armv4_5 = target->arch_info;
594 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
595 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
596 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
598 /* set RESTART instruction */
599 jtag_add_end_state(TAP_RTI);
600 if (arm7_9->need_bypass_before_restart) {
601 arm7_9->need_bypass_before_restart = 0;
602 arm_jtag_set_instr(jtag_info, 0xf, NULL);
604 arm_jtag_set_instr(jtag_info, 0x4, NULL);
608 /* check for DBGACK and SYSCOMP set (others don't care) */
610 /* NB! These are constants that must be available until after next jtag_execute() and
611 we evaluate the values upon first execution in lieu of setting up these constants
614 buf_set_u32(check_value, 0, 32, 0x9);
615 buf_set_u32(check_mask, 0, 32, 0x9);
619 /* read debug status register */
620 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
625 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
627 armv4_5_common_t *armv4_5 = target->arch_info;
628 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
629 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
633 data = malloc(size * (sizeof(u32)));
635 embeddedice_receive(jtag_info, data, size);
637 for (i = 0; i < size; i++)
639 h_u32_to_le(buffer + (i * 4), data[i]);
647 int arm7_9_handle_target_request(void *priv)
649 target_t *target = priv;
650 if (!target->type->examined)
652 armv4_5_common_t *armv4_5 = target->arch_info;
653 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
654 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
655 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
658 if (!target->dbg_msg_enabled)
661 if (target->state == TARGET_RUNNING)
663 /* read DCC control register */
664 embeddedice_read_reg(dcc_control);
665 jtag_execute_queue();
668 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
672 embeddedice_receive(jtag_info, &request, 1);
673 target_request(target, request);
680 int arm7_9_poll(target_t *target)
683 armv4_5_common_t *armv4_5 = target->arch_info;
684 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
685 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
687 /* read debug status register */
688 embeddedice_read_reg(dbg_stat);
689 if ((retval = jtag_execute_queue()) != ERROR_OK)
694 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
696 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
697 if (target->state == TARGET_UNKNOWN)
699 target->state = TARGET_RUNNING;
700 LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
702 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
705 if (target->state == TARGET_RESET)
707 if (target->reset_halt)
709 if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
716 target->state = TARGET_HALTED;
718 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
723 reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
724 u32 t=*((u32 *)reg->value);
727 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
731 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
733 if (target->state == TARGET_DEBUG_RUNNING)
735 target->state = TARGET_HALTED;
736 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
739 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
741 if (target->state != TARGET_HALTED)
743 LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
748 if (target->state != TARGET_DEBUG_RUNNING)
749 target->state = TARGET_RUNNING;
756 Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
757 in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
758 while the core is held in reset(SRST). It isn't possible to program the halt
759 condition once reset was asserted, hence a hook that allows the target to set
760 up its reset-halt condition prior to asserting reset.
763 int arm7_9_assert_reset(target_t *target)
765 armv4_5_common_t *armv4_5 = target->arch_info;
766 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
767 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
769 if (!(jtag_reset_config & RESET_HAS_SRST))
771 LOG_ERROR("Can't assert SRST");
775 if (target->reset_halt)
778 * Some targets do not support communication while SRST is asserted. We need to
779 * set up the reset vector catch here.
781 * If TRST is asserted, then these settings will be reset anyway, so setting them
784 if (arm7_9->has_vector_catch)
786 /* program vector catch register to catch reset vector */
787 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
791 /* program watchpoint unit to match on reset vector address */
792 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
793 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
794 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
795 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
796 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
800 /* here we should issue a srst only, but we may have to assert trst as well */
801 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
803 jtag_add_reset(1, 1);
806 jtag_add_reset(0, 1);
810 target->state = TARGET_RESET;
811 jtag_add_sleep(50000);
813 armv4_5_invalidate_core_regs(target);
819 int arm7_9_deassert_reset(target_t *target)
821 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
823 /* deassert reset lines */
824 jtag_add_reset(0, 0);
829 int arm7_9_clear_halt(target_t *target)
831 armv4_5_common_t *armv4_5 = target->arch_info;
832 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
833 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
835 /* we used DBGRQ only if we didn't come out of reset */
836 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
838 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
840 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
841 embeddedice_store_reg(dbg_ctrl);
845 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
847 /* if we came out of reset, and vector catch is supported, we used
848 * vector catch to enter debug state
849 * restore the register in that case
851 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
855 /* restore registers if watchpoint unit 0 was in use
857 if (arm7_9->wp0_used)
859 if (arm7_9->debug_entry_from_reset)
861 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
863 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
864 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
865 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
867 /* control value always has to be restored, as it was either disabled,
868 * or enabled with possibly different bits
870 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
877 int arm7_9_soft_reset_halt(struct target_s *target)
879 armv4_5_common_t *armv4_5 = target->arch_info;
880 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
881 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
882 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
886 if ((retval=target_halt(target))!=ERROR_OK)
891 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
893 embeddedice_read_reg(dbg_stat);
894 if ((retval=jtag_execute_queue())!=ERROR_OK)
896 /* do not eat all CPU, time out after 1 se*/
902 LOG_ERROR("Failed to halt CPU after 1 sec");
903 return ERROR_TARGET_TIMEOUT;
905 target->state = TARGET_HALTED;
907 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
908 * ensure that DBGRQ is cleared
910 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
911 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
912 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
913 embeddedice_store_reg(dbg_ctrl);
915 arm7_9_clear_halt(target);
917 /* if the target is in Thumb state, change to ARM state */
918 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
920 u32 r0_thumb, pc_thumb;
921 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
922 /* Entered debug from Thumb mode */
923 armv4_5->core_state = ARMV4_5_STATE_THUMB;
924 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
927 /* all register content is now invalid */
928 armv4_5_invalidate_core_regs(target);
930 /* SVC, ARM state, IRQ and FIQ disabled */
931 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
932 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
933 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
935 /* start fetching from 0x0 */
936 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
937 armv4_5->core_cache->reg_list[15].dirty = 1;
938 armv4_5->core_cache->reg_list[15].valid = 1;
940 armv4_5->core_mode = ARMV4_5_MODE_SVC;
941 armv4_5->core_state = ARMV4_5_STATE_ARM;
943 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
946 /* reset registers */
947 for (i = 0; i <= 14; i++)
949 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
950 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
951 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
954 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
959 int arm7_9_halt(target_t *target)
961 armv4_5_common_t *armv4_5 = target->arch_info;
962 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
963 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
965 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
967 if (target->state == TARGET_HALTED)
969 LOG_DEBUG("target was already halted");
973 if (target->state == TARGET_UNKNOWN)
975 LOG_WARNING("target was in unknown state when halt was requested");
978 if (target->state == TARGET_RESET)
980 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
982 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
983 return ERROR_TARGET_FAILURE;
987 /* we came here in a reset_halt or reset_init sequence
988 * debug entry was already prepared in arm7_9_assert_reset()
990 target->debug_reason = DBG_REASON_DBGRQ;
996 if (arm7_9->use_dbgrq)
998 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1000 if (arm7_9->set_special_dbgrq) {
1001 arm7_9->set_special_dbgrq(target);
1003 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1004 embeddedice_store_reg(dbg_ctrl);
1009 /* program watchpoint unit to match on any address
1011 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1012 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1013 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1014 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1017 target->debug_reason = DBG_REASON_DBGRQ;
1022 int arm7_9_debug_entry(target_t *target)
1027 u32 r0_thumb, pc_thumb;
1030 /* get pointers to arch-specific information */
1031 armv4_5_common_t *armv4_5 = target->arch_info;
1032 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1033 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1034 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1036 #ifdef _DEBUG_ARM7_9_
1040 if (arm7_9->pre_debug_entry)
1041 arm7_9->pre_debug_entry(target);
1043 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1044 * ensure that DBGRQ is cleared
1046 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1047 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1048 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1049 embeddedice_store_reg(dbg_ctrl);
1051 arm7_9_clear_halt(target);
1053 if ((retval = jtag_execute_queue()) != ERROR_OK)
1058 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1062 if (target->state != TARGET_HALTED)
1064 LOG_WARNING("target not halted");
1065 return ERROR_TARGET_NOT_HALTED;
1068 /* if the target is in Thumb state, change to ARM state */
1069 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1071 LOG_DEBUG("target entered debug from Thumb state");
1072 /* Entered debug from Thumb mode */
1073 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1074 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1075 LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1079 LOG_DEBUG("target entered debug from ARM state");
1080 /* Entered debug from ARM mode */
1081 armv4_5->core_state = ARMV4_5_STATE_ARM;
1084 for (i = 0; i < 16; i++)
1085 context_p[i] = &context[i];
1086 /* save core registers (r0 - r15 of current core mode) */
1087 arm7_9->read_core_regs(target, 0xffff, context_p);
1089 arm7_9->read_xpsr(target, &cpsr, 0);
1091 if ((retval = jtag_execute_queue()) != ERROR_OK)
1094 /* if the core has been executing in Thumb state, set the T bit */
1095 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1098 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1099 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1100 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1102 armv4_5->core_mode = cpsr & 0x1f;
1104 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1106 target->state = TARGET_UNKNOWN;
1107 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1108 return ERROR_TARGET_FAILURE;
1111 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1113 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1115 LOG_DEBUG("thumb state, applying fixups");
1116 context[0] = r0_thumb;
1117 context[15] = pc_thumb;
1118 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1120 /* adjust value stored by STM */
1121 context[15] -= 3 * 4;
1124 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1125 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1126 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1127 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1128 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1129 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1130 else if (target->debug_reason == DBG_REASON_DBGRQ)
1131 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1134 LOG_ERROR("unknown debug reason: %i", target->debug_reason);
1137 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1140 for (i=0; i<=15; i++)
1142 LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
1143 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1144 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1145 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1148 LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
1150 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1153 /* exceptions other than USR & SYS have a saved program status register */
1154 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1157 arm7_9->read_xpsr(target, &spsr, 1);
1158 jtag_execute_queue();
1159 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1160 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1161 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1164 /* r0 and r15 (pc) have to be restored later */
1165 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1166 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1168 if ((retval = jtag_execute_queue()) != ERROR_OK)
1171 if (arm7_9->post_debug_entry)
1172 arm7_9->post_debug_entry(target);
1177 int arm7_9_full_context(target_t *target)
1181 armv4_5_common_t *armv4_5 = target->arch_info;
1182 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1186 if (target->state != TARGET_HALTED)
1188 LOG_WARNING("target not halted");
1189 return ERROR_TARGET_NOT_HALTED;
1192 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1195 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1196 * SYS shares registers with User, so we don't touch SYS
1198 for(i = 0; i < 6; i++)
1205 /* check if there are invalid registers in the current mode
1207 for (j = 0; j <= 16; j++)
1209 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1217 /* change processor mode (and mask T bit) */
1218 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1219 tmp_cpsr |= armv4_5_number_to_mode(i);
1221 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1223 for (j = 0; j < 15; j++)
1225 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1227 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1229 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1230 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1234 /* if only the PSR is invalid, mask is all zeroes */
1236 arm7_9->read_core_regs(target, mask, reg_p);
1238 /* check if the PSR has to be read */
1239 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1241 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1242 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1243 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1248 /* restore processor mode (mask T bit) */
1249 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1251 if ((retval = jtag_execute_queue()) != ERROR_OK)
1258 int arm7_9_restore_context(target_t *target)
1260 armv4_5_common_t *armv4_5 = target->arch_info;
1261 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1263 armv4_5_core_reg_t *reg_arch_info;
1264 enum armv4_5_mode current_mode = armv4_5->core_mode;
1271 if (target->state != TARGET_HALTED)
1273 LOG_WARNING("target not halted");
1274 return ERROR_TARGET_NOT_HALTED;
1277 if (arm7_9->pre_restore_context)
1278 arm7_9->pre_restore_context(target);
1280 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1283 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1284 * SYS shares registers with User, so we don't touch SYS
1286 for (i = 0; i < 6; i++)
1288 LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1291 /* check if there are dirty registers in the current mode
1293 for (j = 0; j <= 16; j++)
1295 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1296 reg_arch_info = reg->arch_info;
1297 if (reg->dirty == 1)
1299 if (reg->valid == 1)
1302 LOG_DEBUG("examining dirty reg: %s", reg->name);
1303 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1304 && (reg_arch_info->mode != current_mode)
1305 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1306 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1309 LOG_DEBUG("require mode change");
1314 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1329 /* change processor mode (mask T bit) */
1330 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1331 tmp_cpsr |= armv4_5_number_to_mode(i);
1333 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1334 current_mode = armv4_5_number_to_mode(i);
1337 for (j = 0; j <= 14; j++)
1339 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1340 reg_arch_info = reg->arch_info;
1343 if (reg->dirty == 1)
1345 regs[j] = buf_get_u32(reg->value, 0, 32);
1350 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1356 arm7_9->write_core_regs(target, mask, regs);
1359 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1360 reg_arch_info = reg->arch_info;
1361 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1363 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1364 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1369 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1371 /* restore processor mode (mask T bit) */
1374 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1375 tmp_cpsr |= armv4_5_number_to_mode(i);
1377 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1378 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1380 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1382 /* CPSR has been changed, full restore necessary (mask T bit) */
1383 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1384 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1385 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1386 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1390 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1391 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1392 armv4_5->core_cache->reg_list[15].dirty = 0;
1394 if (arm7_9->post_restore_context)
1395 arm7_9->post_restore_context(target);
1400 int arm7_9_restart_core(struct target_s *target)
1402 armv4_5_common_t *armv4_5 = target->arch_info;
1403 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1404 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1406 /* set RESTART instruction */
1407 jtag_add_end_state(TAP_RTI);
1408 if (arm7_9->need_bypass_before_restart) {
1409 arm7_9->need_bypass_before_restart = 0;
1410 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1412 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1414 jtag_add_runtest(1, TAP_RTI);
1415 return jtag_execute_queue();
1418 void arm7_9_enable_watchpoints(struct target_s *target)
1420 watchpoint_t *watchpoint = target->watchpoints;
1424 if (watchpoint->set == 0)
1425 arm7_9_set_watchpoint(target, watchpoint);
1426 watchpoint = watchpoint->next;
1430 void arm7_9_enable_breakpoints(struct target_s *target)
1432 breakpoint_t *breakpoint = target->breakpoints;
1434 /* set any pending breakpoints */
1437 if (breakpoint->set == 0)
1438 arm7_9_set_breakpoint(target, breakpoint);
1439 breakpoint = breakpoint->next;
1443 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1445 breakpoint_t *breakpoint = target->breakpoints;
1446 watchpoint_t *watchpoint = target->watchpoints;
1448 /* set any pending breakpoints */
1451 if (breakpoint->set != 0)
1452 arm7_9_unset_breakpoint(target, breakpoint);
1453 breakpoint = breakpoint->next;
1458 if (watchpoint->set != 0)
1459 arm7_9_unset_watchpoint(target, watchpoint);
1460 watchpoint = watchpoint->next;
1464 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1466 armv4_5_common_t *armv4_5 = target->arch_info;
1467 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1468 breakpoint_t *breakpoint = target->breakpoints;
1469 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1474 if (target->state != TARGET_HALTED)
1476 LOG_WARNING("target not halted");
1477 return ERROR_TARGET_NOT_HALTED;
1480 if (!debug_execution)
1482 target_free_all_working_areas(target);
1485 /* current = 1: continue on current pc, otherwise continue at <address> */
1487 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1489 /* the front-end may request us not to handle breakpoints */
1490 if (handle_breakpoints)
1492 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1494 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1495 arm7_9_unset_breakpoint(target, breakpoint);
1497 LOG_DEBUG("enable single-step");
1498 arm7_9->enable_single_step(target);
1500 target->debug_reason = DBG_REASON_SINGLESTEP;
1502 arm7_9_restore_context(target);
1504 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1505 arm7_9->branch_resume(target);
1506 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1508 arm7_9->branch_resume_thumb(target);
1512 LOG_ERROR("unhandled core state");
1516 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1517 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1518 err = arm7_9_execute_sys_speed(target);
1520 LOG_DEBUG("disable single-step");
1521 arm7_9->disable_single_step(target);
1523 if (err != ERROR_OK)
1525 arm7_9_set_breakpoint(target, breakpoint);
1526 target->state = TARGET_UNKNOWN;
1530 arm7_9_debug_entry(target);
1531 LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1533 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1534 arm7_9_set_breakpoint(target, breakpoint);
1538 /* enable any pending breakpoints and watchpoints */
1539 arm7_9_enable_breakpoints(target);
1540 arm7_9_enable_watchpoints(target);
1542 arm7_9_restore_context(target);
1544 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1546 arm7_9->branch_resume(target);
1548 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1550 arm7_9->branch_resume_thumb(target);
1554 LOG_ERROR("unhandled core state");
1558 /* deassert DBGACK and INTDIS */
1559 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1560 /* INTDIS only when we really resume, not during debug execution */
1561 if (!debug_execution)
1562 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1563 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1565 arm7_9_restart_core(target);
1567 target->debug_reason = DBG_REASON_NOTHALTED;
1569 if (!debug_execution)
1571 /* registers are now invalid */
1572 armv4_5_invalidate_core_regs(target);
1573 target->state = TARGET_RUNNING;
1574 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1578 target->state = TARGET_DEBUG_RUNNING;
1579 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1582 LOG_DEBUG("target resumed");
1587 void arm7_9_enable_eice_step(target_t *target)
1589 armv4_5_common_t *armv4_5 = target->arch_info;
1590 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1592 /* setup an inverse breakpoint on the current PC
1593 * - comparator 1 matches the current address
1594 * - rangeout from comparator 1 is connected to comparator 0 rangein
1595 * - comparator 0 matches any address, as long as rangein is low */
1596 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1597 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1598 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1599 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
1600 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1601 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1602 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1603 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1604 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1607 void arm7_9_disable_eice_step(target_t *target)
1609 armv4_5_common_t *armv4_5 = target->arch_info;
1610 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1612 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1613 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1614 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1615 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1616 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1617 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1618 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1619 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1620 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1623 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1625 armv4_5_common_t *armv4_5 = target->arch_info;
1626 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1627 breakpoint_t *breakpoint = NULL;
1630 if (target->state != TARGET_HALTED)
1632 LOG_WARNING("target not halted");
1633 return ERROR_TARGET_NOT_HALTED;
1636 /* current = 1: continue on current pc, otherwise continue at <address> */
1638 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1640 /* the front-end may request us not to handle breakpoints */
1641 if (handle_breakpoints)
1642 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1643 arm7_9_unset_breakpoint(target, breakpoint);
1645 target->debug_reason = DBG_REASON_SINGLESTEP;
1647 arm7_9_restore_context(target);
1649 arm7_9->enable_single_step(target);
1651 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1653 arm7_9->branch_resume(target);
1655 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1657 arm7_9->branch_resume_thumb(target);
1661 LOG_ERROR("unhandled core state");
1665 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1667 err = arm7_9_execute_sys_speed(target);
1668 arm7_9->disable_single_step(target);
1670 /* registers are now invalid */
1671 armv4_5_invalidate_core_regs(target);
1673 if (err != ERROR_OK)
1675 target->state = TARGET_UNKNOWN;
1677 arm7_9_debug_entry(target);
1678 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1679 LOG_DEBUG("target stepped");
1683 arm7_9_set_breakpoint(target, breakpoint);
1689 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1694 armv4_5_common_t *armv4_5 = target->arch_info;
1695 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1697 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1700 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1702 if ((num < 0) || (num > 16))
1703 return ERROR_INVALID_ARGUMENTS;
1705 if ((mode != ARMV4_5_MODE_ANY)
1706 && (mode != armv4_5->core_mode)
1707 && (reg_mode != ARMV4_5_MODE_ANY))
1711 /* change processor mode (mask T bit) */
1712 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1715 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1718 if ((num >= 0) && (num <= 15))
1720 /* read a normal core register */
1721 reg_p[num] = &value;
1723 arm7_9->read_core_regs(target, 1 << num, reg_p);
1727 /* read a program status register
1728 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1730 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1731 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1733 arm7_9->read_xpsr(target, &value, spsr);
1736 if ((retval = jtag_execute_queue()) != ERROR_OK)
1741 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1742 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1743 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1745 if ((mode != ARMV4_5_MODE_ANY)
1746 && (mode != armv4_5->core_mode)
1747 && (reg_mode != ARMV4_5_MODE_ANY)) {
1748 /* restore processor mode (mask T bit) */
1749 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1756 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1759 armv4_5_common_t *armv4_5 = target->arch_info;
1760 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1762 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1765 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1767 if ((num < 0) || (num > 16))
1768 return ERROR_INVALID_ARGUMENTS;
1770 if ((mode != ARMV4_5_MODE_ANY)
1771 && (mode != armv4_5->core_mode)
1772 && (reg_mode != ARMV4_5_MODE_ANY)) {
1775 /* change processor mode (mask T bit) */
1776 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1779 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1782 if ((num >= 0) && (num <= 15))
1784 /* write a normal core register */
1787 arm7_9->write_core_regs(target, 1 << num, reg);
1791 /* write a program status register
1792 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1794 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1795 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1797 /* if we're writing the CPSR, mask the T bit */
1801 arm7_9->write_xpsr(target, value, spsr);
1804 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1805 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1807 if ((mode != ARMV4_5_MODE_ANY)
1808 && (mode != armv4_5->core_mode)
1809 && (reg_mode != ARMV4_5_MODE_ANY)) {
1810 /* restore processor mode (mask T bit) */
1811 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1814 return jtag_execute_queue();
1817 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1819 armv4_5_common_t *armv4_5 = target->arch_info;
1820 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1823 int num_accesses = 0;
1824 int thisrun_accesses;
1830 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1832 if (target->state != TARGET_HALTED)
1834 LOG_WARNING("target not halted");
1835 return ERROR_TARGET_NOT_HALTED;
1838 /* sanitize arguments */
1839 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1840 return ERROR_INVALID_ARGUMENTS;
1842 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1843 return ERROR_TARGET_UNALIGNED_ACCESS;
1845 /* load the base register with the address of the first word */
1847 arm7_9->write_core_regs(target, 0x1, reg);
1852 while (num_accesses < count)
1855 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1856 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1858 if (last_reg <= thisrun_accesses)
1859 last_reg = thisrun_accesses;
1861 arm7_9->load_word_regs(target, reg_list);
1863 /* fast memory reads are only safe when the target is running
1864 * from a sufficiently high clock (32 kHz is usually too slow)
1866 if (arm7_9->fast_memory_access)
1867 arm7_9_execute_fast_sys_speed(target);
1869 arm7_9_execute_sys_speed(target);
1871 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1873 /* advance buffer, count number of accesses */
1874 buffer += thisrun_accesses * 4;
1875 num_accesses += thisrun_accesses;
1879 while (num_accesses < count)
1882 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1883 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1885 for (i = 1; i <= thisrun_accesses; i++)
1889 arm7_9->load_hword_reg(target, i);
1890 /* fast memory reads are only safe when the target is running
1891 * from a sufficiently high clock (32 kHz is usually too slow)
1893 if (arm7_9->fast_memory_access)
1894 arm7_9_execute_fast_sys_speed(target);
1896 arm7_9_execute_sys_speed(target);
1899 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1901 /* advance buffer, count number of accesses */
1902 buffer += thisrun_accesses * 2;
1903 num_accesses += thisrun_accesses;
1907 while (num_accesses < count)
1910 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1911 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1913 for (i = 1; i <= thisrun_accesses; i++)
1917 arm7_9->load_byte_reg(target, i);
1918 /* fast memory reads are only safe when the target is running
1919 * from a sufficiently high clock (32 kHz is usually too slow)
1921 if (arm7_9->fast_memory_access)
1922 arm7_9_execute_fast_sys_speed(target);
1924 arm7_9_execute_sys_speed(target);
1927 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1929 /* advance buffer, count number of accesses */
1930 buffer += thisrun_accesses * 1;
1931 num_accesses += thisrun_accesses;
1935 LOG_ERROR("BUG: we shouldn't get here");
1940 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1943 for (i=0; i<=last_reg; i++)
1944 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1946 arm7_9->read_xpsr(target, &cpsr, 0);
1947 if ((retval = jtag_execute_queue()) != ERROR_OK)
1949 LOG_ERROR("JTAG error while reading cpsr");
1950 return ERROR_TARGET_DATA_ABORT;
1953 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1955 LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1957 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1959 return ERROR_TARGET_DATA_ABORT;
1965 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1967 armv4_5_common_t *armv4_5 = target->arch_info;
1968 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1969 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1972 int num_accesses = 0;
1973 int thisrun_accesses;
1979 #ifdef _DEBUG_ARM7_9_
1980 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1983 if (target->state != TARGET_HALTED)
1985 LOG_WARNING("target not halted");
1986 return ERROR_TARGET_NOT_HALTED;
1989 /* sanitize arguments */
1990 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1991 return ERROR_INVALID_ARGUMENTS;
1993 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1994 return ERROR_TARGET_UNALIGNED_ACCESS;
1996 /* load the base register with the address of the first word */
1998 arm7_9->write_core_regs(target, 0x1, reg);
2000 /* Clear DBGACK, to make sure memory fetches work as expected */
2001 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2002 embeddedice_store_reg(dbg_ctrl);
2007 while (num_accesses < count)
2010 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2011 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2013 for (i = 1; i <= thisrun_accesses; i++)
2017 reg[i] = target_buffer_get_u32(target, buffer);
2021 arm7_9->write_core_regs(target, reg_list, reg);
2023 arm7_9->store_word_regs(target, reg_list);
2025 /* fast memory writes are only safe when the target is running
2026 * from a sufficiently high clock (32 kHz is usually too slow)
2028 if (arm7_9->fast_memory_access)
2029 arm7_9_execute_fast_sys_speed(target);
2031 arm7_9_execute_sys_speed(target);
2033 num_accesses += thisrun_accesses;
2037 while (num_accesses < count)
2040 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2041 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2043 for (i = 1; i <= thisrun_accesses; i++)
2047 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2051 arm7_9->write_core_regs(target, reg_list, reg);
2053 for (i = 1; i <= thisrun_accesses; i++)
2055 arm7_9->store_hword_reg(target, i);
2057 /* fast memory writes are only safe when the target is running
2058 * from a sufficiently high clock (32 kHz is usually too slow)
2060 if (arm7_9->fast_memory_access)
2061 arm7_9_execute_fast_sys_speed(target);
2063 arm7_9_execute_sys_speed(target);
2066 num_accesses += thisrun_accesses;
2070 while (num_accesses < count)
2073 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2074 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2076 for (i = 1; i <= thisrun_accesses; i++)
2080 reg[i] = *buffer++ & 0xff;
2083 arm7_9->write_core_regs(target, reg_list, reg);
2085 for (i = 1; i <= thisrun_accesses; i++)
2087 arm7_9->store_byte_reg(target, i);
2088 /* fast memory writes are only safe when the target is running
2089 * from a sufficiently high clock (32 kHz is usually too slow)
2091 if (arm7_9->fast_memory_access)
2092 arm7_9_execute_fast_sys_speed(target);
2094 arm7_9_execute_sys_speed(target);
2097 num_accesses += thisrun_accesses;
2101 LOG_ERROR("BUG: we shouldn't get here");
2107 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2108 embeddedice_store_reg(dbg_ctrl);
2110 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2113 for (i=0; i<=last_reg; i++)
2114 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2116 arm7_9->read_xpsr(target, &cpsr, 0);
2117 if ((retval = jtag_execute_queue()) != ERROR_OK)
2119 LOG_ERROR("JTAG error while reading cpsr");
2120 return ERROR_TARGET_DATA_ABORT;
2123 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2125 LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2127 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2129 return ERROR_TARGET_DATA_ABORT;
2135 static const u32 dcc_code[] =
2137 /* MRC TST BNE MRC STR B */
2138 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2141 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2143 armv4_5_common_t *armv4_5 = target->arch_info;
2144 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2145 enum armv4_5_state core_state = armv4_5->core_state;
2146 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2147 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2148 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2151 if (!arm7_9->dcc_downloads)
2152 return target->type->write_memory(target, address, 4, count, buffer);
2154 /* regrab previously allocated working_area, or allocate a new one */
2155 if (!arm7_9->dcc_working_area)
2157 u8 dcc_code_buf[6 * 4];
2159 /* make sure we have a working area */
2160 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2162 LOG_INFO("no working area available, falling back to memory writes");
2163 return target->type->write_memory(target, address, 4, count, buffer);
2166 /* copy target instructions to target endianness */
2167 for (i = 0; i < 6; i++)
2169 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2172 /* write DCC code to working area */
2173 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2176 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2177 armv4_5->core_cache->reg_list[0].valid = 1;
2178 armv4_5->core_cache->reg_list[0].dirty = 1;
2179 armv4_5->core_state = ARMV4_5_STATE_ARM;
2181 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2183 int little=target->endianness==TARGET_LITTLE_ENDIAN;
2186 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2187 core function repeated.
2189 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2192 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2193 u8 reg_addr = ice_reg->addr & 0x1f;
2194 int chain_pos = ice_reg->jtag_info->chain_pos;
2195 /* we want the compiler to duplicate the code, which it does not
2200 for (i = 1; i < count - 1; i++)
2202 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2207 for (i = 1; i < count - 1; i++)
2209 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2213 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2216 for (i = 0; i < count; i++)
2218 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2223 target_halt(target);
2225 for (i=0; i<100; i++)
2227 target_poll(target);
2228 if (target->state == TARGET_HALTED)
2230 usleep(1000); /* sleep 1ms */
2234 LOG_ERROR("bulk write timed out, target not halted");
2235 return ERROR_TARGET_TIMEOUT;
2238 /* restore target state */
2239 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2240 armv4_5->core_cache->reg_list[0].valid = 1;
2241 armv4_5->core_cache->reg_list[0].dirty = 1;
2242 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2243 armv4_5->core_cache->reg_list[1].valid = 1;
2244 armv4_5->core_cache->reg_list[1].dirty = 1;
2245 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2246 armv4_5->core_cache->reg_list[15].valid = 1;
2247 armv4_5->core_cache->reg_list[15].dirty = 1;
2248 armv4_5->core_state = core_state;
2253 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2255 working_area_t *crc_algorithm;
2256 armv4_5_algorithm_t armv4_5_info;
2257 reg_param_t reg_params[2];
2260 u32 arm7_9_crc_code[] = {
2261 0xE1A02000, /* mov r2, r0 */
2262 0xE3E00000, /* mov r0, #0xffffffff */
2263 0xE1A03001, /* mov r3, r1 */
2264 0xE3A04000, /* mov r4, #0 */
2265 0xEA00000B, /* b ncomp */
2267 0xE7D21004, /* ldrb r1, [r2, r4] */
2268 0xE59F7030, /* ldr r7, CRC32XOR */
2269 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2270 0xE3A05000, /* mov r5, #0 */
2272 0xE3500000, /* cmp r0, #0 */
2273 0xE1A06080, /* mov r6, r0, asl #1 */
2274 0xE2855001, /* add r5, r5, #1 */
2275 0xE1A00006, /* mov r0, r6 */
2276 0xB0260007, /* eorlt r0, r6, r7 */
2277 0xE3550008, /* cmp r5, #8 */
2278 0x1AFFFFF8, /* bne loop */
2279 0xE2844001, /* add r4, r4, #1 */
2281 0xE1540003, /* cmp r4, r3 */
2282 0x1AFFFFF1, /* bne nbyte */
2284 0xEAFFFFFE, /* b end */
2285 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2290 if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2292 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2295 /* convert flash writing code into a buffer in target endianness */
2296 for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2297 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2299 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2300 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2301 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2303 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
2304 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
2306 buf_set_u32(reg_params[0].value, 0, 32, address);
2307 buf_set_u32(reg_params[1].value, 0, 32, count);
2309 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2310 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2312 LOG_ERROR("error executing arm7_9 crc algorithm");
2313 destroy_reg_param(®_params[0]);
2314 destroy_reg_param(®_params[1]);
2315 target_free_working_area(target, crc_algorithm);
2319 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2321 destroy_reg_param(®_params[0]);
2322 destroy_reg_param(®_params[1]);
2324 target_free_working_area(target, crc_algorithm);
2329 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
2331 working_area_t *erase_check_algorithm;
2332 reg_param_t reg_params[3];
2333 armv4_5_algorithm_t armv4_5_info;
2337 u32 erase_check_code[] =
2340 0xe4d03001, /* ldrb r3, [r0], #1 */
2341 0xe0022003, /* and r2, r2, r3 */
2342 0xe2511001, /* subs r1, r1, #1 */
2343 0x1afffffb, /* bne loop */
2345 0xeafffffe /* b end */
2348 /* make sure we have a working area */
2349 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
2351 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2354 /* convert flash writing code into a buffer in target endianness */
2355 for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
2356 target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]);
2358 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2359 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2360 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2362 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
2363 buf_set_u32(reg_params[0].value, 0, 32, address);
2365 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
2366 buf_set_u32(reg_params[1].value, 0, 32, count);
2368 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
2369 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2371 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
2372 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
2374 destroy_reg_param(®_params[0]);
2375 destroy_reg_param(®_params[1]);
2376 destroy_reg_param(®_params[2]);
2377 target_free_working_area(target, erase_check_algorithm);
2381 *blank = buf_get_u32(reg_params[2].value, 0, 32);
2383 destroy_reg_param(®_params[0]);
2384 destroy_reg_param(®_params[1]);
2385 destroy_reg_param(®_params[2]);
2387 target_free_working_area(target, erase_check_algorithm);
2392 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2394 command_t *arm7_9_cmd;
2396 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2398 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2399 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2401 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2403 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2404 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2405 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2406 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2407 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2408 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2409 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2410 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2411 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2412 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2414 armv4_5_register_commands(cmd_ctx);
2416 etm_register_commands(cmd_ctx);
2421 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2426 target_t *target = get_current_target(cmd_ctx);
2427 armv4_5_common_t *armv4_5;
2428 arm7_9_common_t *arm7_9;
2430 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2432 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2436 if (target->state != TARGET_HALTED)
2438 command_print(cmd_ctx, "can't write registers while running");
2444 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2448 value = strtoul(args[0], NULL, 0);
2449 spsr = strtol(args[1], NULL, 0);
2451 /* if we're writing the CPSR, mask the T bit */
2455 arm7_9->write_xpsr(target, value, spsr);
2456 if ((retval = jtag_execute_queue()) != ERROR_OK)
2458 LOG_ERROR("JTAG error while writing to xpsr");
2465 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2471 target_t *target = get_current_target(cmd_ctx);
2472 armv4_5_common_t *armv4_5;
2473 arm7_9_common_t *arm7_9;
2475 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2477 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2481 if (target->state != TARGET_HALTED)
2483 command_print(cmd_ctx, "can't write registers while running");
2489 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2493 value = strtoul(args[0], NULL, 0);
2494 rotate = strtol(args[1], NULL, 0);
2495 spsr = strtol(args[2], NULL, 0);
2497 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2498 if ((retval = jtag_execute_queue()) != ERROR_OK)
2500 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2507 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2512 target_t *target = get_current_target(cmd_ctx);
2513 armv4_5_common_t *armv4_5;
2514 arm7_9_common_t *arm7_9;
2516 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2518 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2522 if (target->state != TARGET_HALTED)
2524 command_print(cmd_ctx, "can't write registers while running");
2530 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2534 num = strtol(args[0], NULL, 0);
2535 mode = strtoul(args[1], NULL, 0);
2536 value = strtoul(args[2], NULL, 0);
2538 arm7_9_write_core_reg(target, num, mode, value);
2543 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2545 target_t *target = get_current_target(cmd_ctx);
2546 armv4_5_common_t *armv4_5;
2547 arm7_9_common_t *arm7_9;
2549 if (target->state != TARGET_HALTED)
2551 LOG_ERROR("target not halted");
2552 return ERROR_TARGET_NOT_HALTED;
2555 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2557 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2563 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2567 if (strcmp("enable", args[0]) == 0)
2569 if (arm7_9->sw_bkpts_use_wp)
2571 arm7_9_enable_sw_bkpts(target);
2575 arm7_9->sw_bkpts_enabled = 1;
2578 else if (strcmp("disable", args[0]) == 0)
2580 if (arm7_9->sw_bkpts_use_wp)
2582 arm7_9_disable_sw_bkpts(target);
2586 arm7_9->sw_bkpts_enabled = 0;
2591 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2594 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2599 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2601 target_t *target = get_current_target(cmd_ctx);
2602 armv4_5_common_t *armv4_5;
2603 arm7_9_common_t *arm7_9;
2605 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2607 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2611 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2613 arm7_9->force_hw_bkpts = 1;
2614 if (arm7_9->sw_bkpts_use_wp)
2616 arm7_9_disable_sw_bkpts(target);
2619 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2621 arm7_9->force_hw_bkpts = 0;
2625 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2628 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2633 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2635 target_t *target = get_current_target(cmd_ctx);
2636 armv4_5_common_t *armv4_5;
2637 arm7_9_common_t *arm7_9;
2639 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2641 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2647 if (strcmp("enable", args[0]) == 0)
2649 arm7_9->use_dbgrq = 1;
2651 else if (strcmp("disable", args[0]) == 0)
2653 arm7_9->use_dbgrq = 0;
2657 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2661 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2666 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2668 target_t *target = get_current_target(cmd_ctx);
2669 armv4_5_common_t *armv4_5;
2670 arm7_9_common_t *arm7_9;
2672 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2674 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2680 if (strcmp("enable", args[0]) == 0)
2682 arm7_9->fast_memory_access = 1;
2684 else if (strcmp("disable", args[0]) == 0)
2686 arm7_9->fast_memory_access = 0;
2690 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2694 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2699 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2701 target_t *target = get_current_target(cmd_ctx);
2702 armv4_5_common_t *armv4_5;
2703 arm7_9_common_t *arm7_9;
2705 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2707 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2713 if (strcmp("enable", args[0]) == 0)
2715 arm7_9->dcc_downloads = 1;
2717 else if (strcmp("disable", args[0]) == 0)
2719 arm7_9->dcc_downloads = 0;
2723 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2727 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2732 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2734 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2736 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2738 arm_jtag_setup_connection(&arm7_9->jtag_info);
2739 arm7_9->wp_available = 2;
2740 arm7_9->wp0_used = 0;
2741 arm7_9->wp1_used = 0;
2742 arm7_9->force_hw_bkpts = 0;
2743 arm7_9->use_dbgrq = 0;
2745 arm7_9->etm_ctx = NULL;
2746 arm7_9->has_single_step = 0;
2747 arm7_9->has_monitor_mode = 0;
2748 arm7_9->has_vector_catch = 0;
2750 arm7_9->debug_entry_from_reset = 0;
2752 arm7_9->dcc_working_area = NULL;
2754 arm7_9->fast_memory_access = fast_and_dangerous;
2755 arm7_9->dcc_downloads = fast_and_dangerous;
2757 arm7_9->need_bypass_before_restart = 0;
2759 armv4_5->arch_info = arm7_9;
2760 armv4_5->read_core_reg = arm7_9_read_core_reg;
2761 armv4_5->write_core_reg = arm7_9_write_core_reg;
2762 armv4_5->full_context = arm7_9_full_context;
2764 armv4_5_init_arch_info(target, armv4_5);
2766 target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);