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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "embeddedice.h"
  27 #include "target.h"
  28 #include "armv4_5.h"
  29 #include "arm_jtag.h"
  30 #include "jtag.h"
  31 #include "log.h"
  32 #include "arm7_9_common.h"
  33 #include "breakpoints.h"
  34
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <unistd.h>
  38
  39 #include <sys/types.h>
  40 #include <sys/stat.h>
  41 #include <sys/time.h>
  42 #include <errno.h>
  43
  44 int arm7_9_debug_entry(target_t *target);
  45 int arm7_9_enable_sw_bkpts(struct target_s *target);
  46
  47 /* command handler forward declarations */
  48 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  55 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  56 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  57
  58 int arm7_9_reinit_embeddedice(target_t *target)
  59 {
  60         armv4_5_common_t *armv4_5 = target->arch_info;
  61         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  62
  63         breakpoint_t *breakpoint = target->breakpoints;
  64
  65         arm7_9->wp_available = 2;
  66         arm7_9->wp0_used = 0;
  67         arm7_9->wp1_used = 0;
  68
  69         /* mark all hardware breakpoints as unset */
  70         while (breakpoint)
  71         {
  72                 if (breakpoint->type == BKPT_HARD)
  73                 {
  74                         breakpoint->set = 0;
  75                 }
  76                 breakpoint = breakpoint->next;
  77         }
  78
  79         if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
  80         {
  81                 arm7_9->sw_bkpts_enabled = 0;
  82                 arm7_9_enable_sw_bkpts(target);
  83         }
  84
  85         arm7_9->reinit_embeddedice = 0;
  86
  87         return ERROR_OK;
  88 }
  89
  90 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
  91 {
  92         target_t *target = priv;
  93         armv4_5_common_t *armv4_5 = target->arch_info;
  94         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  95
  96         /* a test-logic reset occured
  97          * the EmbeddedICE registers have been reset
  98          * hardware breakpoints have been cleared
  99          */
 100         if (event == JTAG_TRST_ASSERTED)
 101         {
 102                 arm7_9->reinit_embeddedice = 1;
 103         }
 104
 105         return ERROR_OK;
 106 }
 107
 108 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
 109 {
 110         armv4_5_common_t *armv4_5 = target->arch_info;
 111         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 112
 113         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 114         {
 115                 return -1;
 116         }
 117
 118         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 119         {
 120                 return -1;
 121         }
 122
 123         *armv4_5_p = armv4_5;
 124         *arm7_9_p = arm7_9;
 125
 126         return ERROR_OK;
 127 }
 128
 129 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 130 {
 131         armv4_5_common_t *armv4_5 = target->arch_info;
 132         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 133
 134         if (target->state != TARGET_HALTED)
 135         {
 136                 WARNING("target not halted");
 137                 return ERROR_TARGET_NOT_HALTED;
 138         }
 139
 140         if (arm7_9->force_hw_bkpts)
 141                 breakpoint->type = BKPT_HARD;
 142
 143         if (breakpoint->set)
 144         {
 145                 WARNING("breakpoint already set");
 146                 return ERROR_OK;
 147         }
 148
 149         if (breakpoint->type == BKPT_HARD)
 150         {
 151                 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
 152                 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 153                 if (!arm7_9->wp0_used)
 154                 {
 155                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
 156                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 157                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
 158                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 159                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 160
 161                         jtag_execute_queue();
 162                         arm7_9->wp0_used = 1;
 163                         breakpoint->set = 1;
 164                 }
 165                 else if (!arm7_9->wp1_used)
 166                 {
 167                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
 168                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 169                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
 170                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 171                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 172
 173                         jtag_execute_queue();
 174                         arm7_9->wp1_used = 1;
 175                         breakpoint->set = 2;
 176                 }
 177                 else
 178                 {
 179                         ERROR("BUG: no hardware comparator available");
 180                         return ERROR_OK;
 181                 }
 182         }
 183         else if (breakpoint->type == BKPT_SOFT)
 184         {
 185                 if (breakpoint->length == 4)
 186                 {
 187                         /* keep the original instruction in target endianness */
 188                         target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 189                         /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 190                         target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
 191                 }
 192                 else
 193                 {
 194                         /* keep the original instruction in target endianness */
 195                         target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 196                         /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 197                         target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt);
 198                 }
 199                 breakpoint->set = 1;
 200         }
 201
 202         return ERROR_OK;
 203
 204 }
 205
 206 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 207 {
 208         armv4_5_common_t *armv4_5 = target->arch_info;
 209         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 210
 211         if (target->state != TARGET_HALTED)
 212         {
 213                 WARNING("target not halted");
 214                 return ERROR_TARGET_NOT_HALTED;
 215         }
 216
 217         if (!breakpoint->set)
 218         {
 219                 WARNING("breakpoint not set");
 220                 return ERROR_OK;
 221         }
 222
 223         if (breakpoint->type == BKPT_HARD)
 224         {
 225                 if (breakpoint->set == 1)
 226                 {
 227                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 228                         jtag_execute_queue();
 229                         arm7_9->wp0_used = 0;
 230                 }
 231                 else if (breakpoint->set == 2)
 232                 {
 233                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 234                         jtag_execute_queue();
 235                         arm7_9->wp1_used = 0;
 236                 }
 237                 breakpoint->set = 0;
 238         }
 239         else
 240         {
 241                 /* restore original instruction (kept in target endianness) */
 242                 if (breakpoint->length == 4)
 243                 {
 244                         target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 245                 }
 246                 else
 247                 {
 248                         target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 249                 }
 250                 breakpoint->set = 0;
 251         }
 252
 253         return ERROR_OK;
 254 }
 255
 256 int arm7_9_add_breakpoint(struct target_s *target, u32 address, u32 length, enum breakpoint_type type)
 257 {
 258         armv4_5_common_t *armv4_5 = target->arch_info;
 259         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 260
 261         if (target->state != TARGET_HALTED)
 262         {
 263                 WARNING("target not halted");
 264                 return ERROR_TARGET_NOT_HALTED;
 265         }
 266
 267         if (arm7_9->force_hw_bkpts)
 268         {
 269                 type = BKPT_HARD;
 270         }
 271
 272         if ((type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
 273         {
 274                 INFO("sw breakpoint requested, but software breakpoints not enabled");
 275                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 276         }
 277
 278         if ((type == BKPT_HARD) && (arm7_9->wp_available < 1))
 279         {
 280                 INFO("no watchpoint unit available for hardware breakpoint");
 281                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 282         }
 283
 284         if (type == BKPT_HARD)
 285                 arm7_9->wp_available--;
 286
 287         if ((length != 2) && (length != 4))
 288         {
 289                 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 290                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 291         }
 292
 293         return ERROR_OK;
 294 }
 295
 296 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 297 {
 298         armv4_5_common_t *armv4_5 = target->arch_info;
 299         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 300
 301         if (target->state != TARGET_HALTED)
 302         {
 303                 WARNING("target not halted");
 304                 return ERROR_TARGET_NOT_HALTED;
 305         }
 306
 307         if (breakpoint->set)
 308         {
 309                 arm7_9_unset_breakpoint(target, breakpoint);
 310         }
 311
 312         if (breakpoint->type == BKPT_HARD)
 313                 arm7_9->wp_available++;
 314
 315         return ERROR_OK;
 316 }
 317
 318 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 319 {
 320         armv4_5_common_t *armv4_5 = target->arch_info;
 321         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 322         int rw_mask = 1;
 323         u32 mask;
 324
 325         mask = watchpoint->length - 1;
 326
 327         if (target->state != TARGET_HALTED)
 328         {
 329                 WARNING("target not halted");
 330                 return ERROR_TARGET_NOT_HALTED;
 331         }
 332
 333         if (watchpoint->rw == WPT_ACCESS)
 334                 rw_mask = 0;
 335         else
 336                 rw_mask = 1;
 337
 338         if (!arm7_9->wp0_used)
 339         {
 340                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
 341                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 342                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
 343                 if( watchpoint->mask != 0xffffffffu )
 344                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
 345                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 346                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 347
 348                 jtag_execute_queue();
 349                 watchpoint->set = 1;
 350                 arm7_9->wp0_used = 2;
 351         }
 352         else if (!arm7_9->wp1_used)
 353         {
 354                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
 355                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 356                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
 357                 if( watchpoint->mask != 0xffffffffu )
 358                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
 359                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 360                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 361
 362                 jtag_execute_queue();
 363                 watchpoint->set = 2;
 364                 arm7_9->wp1_used = 2;
 365         }
 366         else
 367         {
 368                 ERROR("BUG: no hardware comparator available");
 369                 return ERROR_OK;
 370         }
 371
 372         return ERROR_OK;
 373 }
 374
 375 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 376 {
 377         armv4_5_common_t *armv4_5 = target->arch_info;
 378         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 379
 380         if (target->state != TARGET_HALTED)
 381         {
 382                 WARNING("target not halted");
 383                 return ERROR_TARGET_NOT_HALTED;
 384         }
 385
 386         if (!watchpoint->set)
 387         {
 388                 WARNING("breakpoint not set");
 389                 return ERROR_OK;
 390         }
 391
 392         if (watchpoint->set == 1)
 393         {
 394                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 395                 jtag_execute_queue();
 396                 arm7_9->wp0_used = 0;
 397         }
 398         else if (watchpoint->set == 2)
 399         {
 400                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 401                 jtag_execute_queue();
 402                 arm7_9->wp1_used = 0;
 403         }
 404         watchpoint->set = 0;
 405
 406         return ERROR_OK;
 407 }
 408
 409 int arm7_9_add_watchpoint(struct target_s *target, u32 address, u32 length, enum watchpoint_rw rw)
 410 {
 411         armv4_5_common_t *armv4_5 = target->arch_info;
 412         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 413
 414         if (target->state != TARGET_HALTED)
 415         {
 416                 WARNING("target not halted");
 417                 return ERROR_TARGET_NOT_HALTED;
 418         }
 419
 420         if (arm7_9->wp_available < 1)
 421         {
 422                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 423         }
 424
 425         if ((length != 1) && (length != 2) && (length != 4))
 426         {
 427                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 428         }
 429
 430         arm7_9->wp_available--;
 431
 432         return ERROR_OK;
 433 }
 434
 435 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 436 {
 437         armv4_5_common_t *armv4_5 = target->arch_info;
 438         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 439
 440         if (target->state != TARGET_HALTED)
 441         {
 442                 WARNING("target not halted");
 443                 return ERROR_TARGET_NOT_HALTED;
 444         }
 445
 446         if (watchpoint->set)
 447         {
 448                 arm7_9_unset_watchpoint(target, watchpoint);
 449         }
 450
 451         arm7_9->wp_available++;
 452
 453         return ERROR_OK;
 454 }
 455
 456 int arm7_9_enable_sw_bkpts(struct target_s *target)
 457 {
 458         armv4_5_common_t *armv4_5 = target->arch_info;
 459         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 460         int retval;
 461
 462         if (arm7_9->sw_bkpts_enabled)
 463                 return ERROR_OK;
 464
 465         if (arm7_9->wp_available < 1)
 466         {
 467                 WARNING("can't enable sw breakpoints with no watchpoint unit available");
 468                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 469         }
 470         arm7_9->wp_available--;
 471
 472         if (!arm7_9->wp0_used)
 473         {
 474                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
 475                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
 476                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
 477                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 478                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 479                 arm7_9->sw_bkpts_enabled = 1;
 480                 arm7_9->wp0_used = 3;
 481         }
 482         else if (!arm7_9->wp1_used)
 483         {
 484                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
 485                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
 486                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
 487                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 488                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 489                 arm7_9->sw_bkpts_enabled = 2;
 490                 arm7_9->wp1_used = 3;
 491         }
 492         else
 493         {
 494                 ERROR("BUG: both watchpoints used, but wp_available >= 1");
 495                 exit(-1);
 496         }
 497
 498         if ((retval = jtag_execute_queue()) != ERROR_OK)
 499         {
 500                 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
 501                 exit(-1);
 502         };
 503
 504         return ERROR_OK;
 505 }
 506
 507 int arm7_9_disable_sw_bkpts(struct target_s *target)
 508 {
 509         armv4_5_common_t *armv4_5 = target->arch_info;
 510         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 511
 512         if (!arm7_9->sw_bkpts_enabled)
 513                 return ERROR_OK;
 514
 515         if (arm7_9->sw_bkpts_enabled == 1)
 516         {
 517                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 518                 arm7_9->sw_bkpts_enabled = 0;
 519                 arm7_9->wp0_used = 0;
 520                 arm7_9->wp_available++;
 521         }
 522         else if (arm7_9->sw_bkpts_enabled == 2)
 523         {
 524                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 525                 arm7_9->sw_bkpts_enabled = 0;
 526                 arm7_9->wp1_used = 0;
 527                 arm7_9->wp_available++;
 528         }
 529
 530         return ERROR_OK;
 531 }
 532
 533 int arm7_9_execute_sys_speed(struct target_s *target)
 534 {
 535         int timeout;
 536         int retval;
 537
 538         armv4_5_common_t *armv4_5 = target->arch_info;
 539         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 540         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 541         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 542
 543         /* set RESTART instruction */
 544         jtag_add_end_state(TAP_RTI);
 545         arm_jtag_set_instr(jtag_info, 0x4);
 546
 547         for (timeout=0; timeout<50; timeout++)
 548         {
 549                 /* read debug status register */
 550                 embeddedice_read_reg(dbg_stat);
 551                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 552                         return retval;
 553                 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 554                                    && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 555                         break;
 556                 usleep(100000);
 557         }
 558         if (timeout == 50)
 559         {
 560                 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 561                 return ERROR_TARGET_TIMEOUT;
 562         }
 563
 564         return ERROR_OK;
 565 }
 566
 567 int arm7_9_execute_fast_sys_speed(struct target_s *target)
 568 {
 569         u8 check_value[4], check_mask[4];
 570
 571         armv4_5_common_t *armv4_5 = target->arch_info;
 572         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 573         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 574         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 575
 576         /* set RESTART instruction */
 577         jtag_add_end_state(TAP_RTI);
 578         arm_jtag_set_instr(jtag_info, 0x4);
 579
 580         /* check for DBGACK and SYSCOMP set (others don't care) */
 581         buf_set_u32(check_value, 0, 32, 0x9);
 582         buf_set_u32(check_mask, 0, 32, 0x9);
 583
 584         /* read debug status register */
 585         embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
 586
 587         return ERROR_OK;
 588 }
 589
 590 enum target_state arm7_9_poll(target_t *target)
 591 {
 592         int retval;
 593         armv4_5_common_t *armv4_5 = target->arch_info;
 594         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 595         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 596
 597         if (arm7_9->reinit_embeddedice)
 598         {
 599                 arm7_9_reinit_embeddedice(target);
 600         }
 601
 602         /* read debug status register */
 603         embeddedice_read_reg(dbg_stat);
 604         if ((retval = jtag_execute_queue()) != ERROR_OK)
 605         {
 606                 switch (retval)
 607                 {
 608                         case ERROR_JTAG_QUEUE_FAILED:
 609                                 ERROR("JTAG queue failed while reading EmbeddedICE status register");
 610                                 exit(-1);
 611                                 break;
 612                         default:
 613                                 break;
 614                 }
 615         }
 616
 617         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 618         {
 619                 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
 620                 if ((target->state == TARGET_UNKNOWN))
 621                 {
 622                         WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
 623                         target->state = TARGET_RUNNING;
 624                 }
 625                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 626                 {
 627                         target->state = TARGET_HALTED;
 628                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 629                                 return retval;
 630
 631                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 632                 }
 633                 if (target->state == TARGET_DEBUG_RUNNING)
 634                 {
 635                         target->state = TARGET_HALTED;
 636                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 637                                 return retval;
 638
 639                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 640                 }
 641         }
 642         else
 643         {
 644                 if (target->state != TARGET_DEBUG_RUNNING)
 645                         target->state = TARGET_RUNNING;
 646         }
 647
 648         return target->state;
 649 }
 650
 651 int arm7_9_assert_reset(target_t *target)
 652 {
 653         int retval;
 654
 655         DEBUG("target->state: %s", target_state_strings[target->state]);
 656
 657         if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
 658         {
 659                 /* assert SRST and TRST */
 660                 /* system would get ouf sync if we didn't reset test-logic, too */
 661                 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
 662                 {
 663                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 664                         {
 665                                 WARNING("can't assert srst");
 666                                 return retval;
 667                         }
 668                         else
 669                         {
 670                                 ERROR("unknown error");
 671                                 exit(-1);
 672                         }
 673                 }
 674                 jtag_add_sleep(5000);
 675                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 676                 {
 677                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 678                         {
 679                                 WARNING("srst resets test logic, too");
 680                                 retval = jtag_add_reset(1, 1);
 681                         }
 682                 }
 683         }
 684         else
 685         {
 686                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 687                 {
 688                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 689                         {
 690                                 WARNING("srst resets test logic, too");
 691                                 retval = jtag_add_reset(1, 1);
 692                         }
 693
 694                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 695                         {
 696                                 WARNING("can't assert srst");
 697                                 return retval;
 698                         }
 699                         else if (retval != ERROR_OK)
 700                         {
 701                                 ERROR("unknown error");
 702                                 exit(-1);
 703                         }
 704                 }
 705         }
 706
 707         target->state = TARGET_RESET;
 708         jtag_add_sleep(50000);
 709
 710         armv4_5_invalidate_core_regs(target);
 711
 712         return ERROR_OK;
 713
 714 }
 715
 716 int arm7_9_deassert_reset(target_t *target)
 717 {
 718         DEBUG("target->state: %s", target_state_strings[target->state]);
 719
 720         /* deassert reset lines */
 721         jtag_add_reset(0, 0);
 722
 723         return ERROR_OK;
 724
 725 }
 726
 727 int arm7_9_soft_reset_halt(struct target_s *target)
 728 {
 729         armv4_5_common_t *armv4_5 = target->arch_info;
 730         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 731         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 732         int i;
 733
 734         if (target->state == TARGET_RUNNING)
 735         {
 736                 target->type->halt(target);
 737         }
 738
 739         while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
 740         {
 741                 embeddedice_read_reg(dbg_stat);
 742                 jtag_execute_queue();
 743         }
 744         target->state = TARGET_HALTED;
 745
 746         /* all register content is now invalid */
 747         armv4_5_invalidate_core_regs(target);
 748
 749         /* SVC, ARM state, IRQ and FIQ disabled */
 750         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 751         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 752         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 753
 754         /* start fetching from 0x0 */
 755         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 756         armv4_5->core_cache->reg_list[15].dirty = 1;
 757         armv4_5->core_cache->reg_list[15].valid = 1;
 758
 759         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 760         armv4_5->core_state = ARMV4_5_STATE_ARM;
 761
 762         /* reset registers */
 763         for (i = 0; i <= 14; i++)
 764         {
 765                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
 766                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
 767                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 768         }
 769
 770         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 771
 772         return ERROR_OK;
 773 }
 774
 775 int arm7_9_halt(target_t *target)
 776 {
 777         armv4_5_common_t *armv4_5 = target->arch_info;
 778         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 779         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 780
 781         DEBUG("target->state: %s", target_state_strings[target->state]);
 782
 783         if (target->state == TARGET_HALTED)
 784         {
 785                 WARNING("target was already halted");
 786                 return ERROR_TARGET_ALREADY_HALTED;
 787         }
 788
 789         if (target->state == TARGET_UNKNOWN)
 790         {
 791                 WARNING("target was in unknown state when halt was requested");
 792         }
 793
 794         if ((target->state == TARGET_RESET) && (jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_srst))
 795         {
 796                 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 797                 return ERROR_TARGET_FAILURE;
 798         }
 799
 800         if (arm7_9->use_dbgrq)
 801         {
 802                 /* program EmbeddedICE Debug Control Register to assert DBGRQ
 803                  */
 804                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
 805                 embeddedice_store_reg(dbg_ctrl);
 806         }
 807         else
 808         {
 809                 /* program watchpoint unit to match on any address
 810                  */
 811                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
 812                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
 813                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
 814                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
 815         }
 816
 817         target->debug_reason = DBG_REASON_DBGRQ;
 818
 819         return ERROR_OK;
 820 }
 821
 822 int arm7_9_clear_halt(target_t *target)
 823 {
 824         armv4_5_common_t *armv4_5 = target->arch_info;
 825         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 826         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 827
 828         if (arm7_9->use_dbgrq)
 829         {
 830                 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
 831                  */
 832                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 833                 embeddedice_store_reg(dbg_ctrl);
 834         }
 835         else
 836         {
 837                 /* restore registers if watchpoint unit 0 was in use
 838                  */
 839                 if (arm7_9->wp0_used)
 840                 {
 841                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
 842                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
 843                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
 844                 }
 845                 /* control value always has to be restored, as it was either disabled,
 846                  * or enabled with possibly different bits
 847                  */
 848                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 849         }
 850
 851         return ERROR_OK;
 852 }
 853
 854 int arm7_9_debug_entry(target_t *target)
 855 {
 856         int i;
 857         u32 context[16];
 858         u32* context_p[16];
 859         u32 r0_thumb, pc_thumb;
 860         u32 cpsr;
 861         int retval;
 862         /* get pointers to arch-specific information */
 863         armv4_5_common_t *armv4_5 = target->arch_info;
 864         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 865         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 866         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 867
 868 #ifdef _DEBUG_ARM7_9_
 869         DEBUG("");
 870 #endif
 871
 872         if (arm7_9->pre_debug_entry)
 873                 arm7_9->pre_debug_entry(target);
 874
 875         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 876          * ensure that DBGRQ is cleared
 877          */
 878         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 879         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 880         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 881         embeddedice_store_reg(dbg_ctrl);
 882
 883         arm7_9_clear_halt(target);
 884
 885         if ((retval = jtag_execute_queue()) != ERROR_OK)
 886         {
 887                 switch (retval)
 888                 {
 889                         case ERROR_JTAG_QUEUE_FAILED:
 890                                 ERROR("JTAG queue failed while writing EmbeddedICE control register");
 891                                 exit(-1);
 892                                 break;
 893                         default:
 894                                 break;
 895                 }
 896         }
 897
 898         if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
 899                 return retval;
 900
 901
 902         if (target->state != TARGET_HALTED)
 903         {
 904                 WARNING("target not halted");
 905                 return ERROR_TARGET_NOT_HALTED;
 906         }
 907
 908         /* if the target is in Thumb state, change to ARM state */
 909         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
 910         {
 911                 DEBUG("target entered debug from Thumb state");
 912                 /* Entered debug from Thumb mode */
 913                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
 914                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
 915                 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
 916         }
 917         else
 918         {
 919                 DEBUG("target entered debug from ARM state");
 920                 /* Entered debug from ARM mode */
 921                 armv4_5->core_state = ARMV4_5_STATE_ARM;
 922         }
 923
 924         for (i = 0; i < 16; i++)
 925                 context_p[i] = &context[i];
 926         /* save core registers (r0 - r15 of current core mode) */
 927         arm7_9->read_core_regs(target, 0xffff, context_p);
 928
 929         arm7_9->read_xpsr(target, &cpsr, 0);
 930
 931         if ((retval = jtag_execute_queue()) != ERROR_OK)
 932                 return retval;
 933         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
 934         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
 935         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 936
 937         armv4_5->core_mode = cpsr & 0x1f;
 938         DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
 939
 940         if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
 941         {
 942                 target->state = TARGET_UNKNOWN;
 943                 ERROR("cpsr contains invalid mode value - communication failure");
 944                 return ERROR_TARGET_FAILURE;
 945         }
 946
 947         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 948         {
 949                 DEBUG("thumb state, applying fixups");
 950                 context[0] = r0_thumb;
 951                 context[15] = pc_thumb;
 952         } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 953         {
 954                 /* adjust value stored by STM */
 955                 context[15] -= 3 * 4;
 956         }
 957
 958         if ((target->debug_reason == DBG_REASON_BREAKPOINT)
 959                         || (target->debug_reason == DBG_REASON_SINGLESTEP)
 960                         || (target->debug_reason == DBG_REASON_WATCHPOINT)
 961                         || (target->debug_reason == DBG_REASON_WPTANDBKPT)
 962                         || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
 963                 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 964         else if (target->debug_reason == DBG_REASON_DBGRQ)
 965                 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 966         else
 967         {
 968                 ERROR("unknown debug reason: %i", target->debug_reason);
 969         }
 970
 971
 972         for (i=0; i<=15; i++)
 973         {
 974                 DEBUG("r%i: 0x%8.8x", i, context[i]);
 975                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
 976                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
 977                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 978         }
 979
 980         DEBUG("entered debug state at PC 0x%x", context[15]);
 981
 982         /* exceptions other than USR & SYS have a saved program status register */
 983         if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
 984         {
 985                 u32 spsr;
 986                 arm7_9->read_xpsr(target, &spsr, 1);
 987                 jtag_execute_queue();
 988                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
 989                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
 990                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
 991         }
 992
 993         /* r0 and r15 (pc) have to be restored later */
 994         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 995         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
 996
 997         if ((retval = jtag->execute_queue()) != ERROR_OK)
 998                 return retval;
 999
1000         if (arm7_9->post_debug_entry)
1001                 arm7_9->post_debug_entry(target);
1002
1003         return ERROR_OK;
1004 }
1005
1006 int arm7_9_full_context(target_t *target)
1007 {
1008         int i;
1009         int retval;
1010         armv4_5_common_t *armv4_5 = target->arch_info;
1011         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1012
1013         DEBUG("");
1014
1015         if (target->state != TARGET_HALTED)
1016         {
1017                 WARNING("target not halted");
1018                 return ERROR_TARGET_NOT_HALTED;
1019         }
1020
1021         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1022          * SYS shares registers with User, so we don't touch SYS
1023          */
1024         for(i = 0; i < 6; i++)
1025         {
1026                 u32 mask = 0;
1027                 u32* reg_p[16];
1028                 int j;
1029                 int valid = 1;
1030
1031                 /* check if there are invalid registers in the current mode
1032                  */
1033                 for (j = 0; j <= 16; j++)
1034                 {
1035                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1036                                 valid = 0;
1037                 }
1038
1039                 if (!valid)
1040                 {
1041                         u32 tmp_cpsr;
1042
1043                         /* change processor mode */
1044                         tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1045                         tmp_cpsr |= armv4_5_number_to_mode(i);
1046                         arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1047
1048                         for (j = 0; j < 15; j++)
1049                         {
1050                                 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1051                                 {
1052                                         reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1053                                         mask |= 1 << j;
1054                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1055                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1056                                 }
1057                         }
1058
1059                         /* if only the PSR is invalid, mask is all zeroes */
1060                         if (mask)
1061                                 arm7_9->read_core_regs(target, mask, reg_p);
1062
1063                         /* check if the PSR has to be read */
1064                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1065                         {
1066                                 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1067                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1068                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1069                         }
1070                 }
1071         }
1072
1073         /* restore processor mode */
1074         arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
1075
1076         if ((retval = jtag_execute_queue()) != ERROR_OK)
1077         {
1078                 ERROR("JTAG failure");
1079                 exit(-1);
1080         }
1081         return ERROR_OK;
1082 }
1083
1084 int arm7_9_restore_context(target_t *target)
1085 {
1086         armv4_5_common_t *armv4_5 = target->arch_info;
1087         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1088         reg_t *reg;
1089         armv4_5_core_reg_t *reg_arch_info;
1090         enum armv4_5_mode current_mode = armv4_5->core_mode;
1091         int i, j;
1092         int dirty;
1093         int mode_change;
1094
1095         DEBUG("");
1096
1097         if (target->state != TARGET_HALTED)
1098         {
1099                 WARNING("target not halted");
1100                 return ERROR_TARGET_NOT_HALTED;
1101         }
1102
1103         if (arm7_9->pre_restore_context)
1104                 arm7_9->pre_restore_context(target);
1105
1106         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1107          * SYS shares registers with User, so we don't touch SYS
1108          */
1109         for (i = 0; i < 6; i++)
1110         {
1111                 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1112                 dirty = 0;
1113                 mode_change = 0;
1114                 /* check if there are dirty registers in the current mode
1115                 */
1116                 for (j = 0; j <= 16; j++)
1117                 {
1118                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1119                         reg_arch_info = reg->arch_info;
1120                         if (reg->dirty == 1)
1121                         {
1122                                 if (reg->valid == 1)
1123                                 {
1124                                         dirty = 1;
1125                                         DEBUG("examining dirty reg: %s", reg->name);
1126                                         if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1127                                                 && (reg_arch_info->mode != current_mode)
1128                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1129                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1130                                         {
1131                                                 mode_change = 1;
1132                                                 DEBUG("require mode change");
1133                                         }
1134                                 }
1135                                 else
1136                                 {
1137                                         ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1138                                         exit(-1);
1139                                 }
1140                         }
1141                 }
1142
1143                 if (dirty)
1144                 {
1145                         u32 mask = 0x0;
1146                         int num_regs = 0;
1147                         u32 regs[16];
1148
1149                         if (mode_change)
1150                         {
1151                                 u32 tmp_cpsr;
1152
1153                                 /* change processor mode */
1154                                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1155                                 tmp_cpsr |= armv4_5_number_to_mode(i);
1156                                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1157                                 current_mode = armv4_5_number_to_mode(i);
1158                         }
1159
1160                         for (j = 0; j <= 14; j++)
1161                         {
1162                                 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1163                                 reg_arch_info = reg->arch_info;
1164
1165
1166                                 if (reg->dirty == 1)
1167                                 {
1168                                         regs[j] = buf_get_u32(reg->value, 0, 32);
1169                                         mask |= 1 << j;
1170                                         num_regs++;
1171                                         reg->dirty = 0;
1172                                         reg->valid = 1;
1173                                         DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1174                                 }
1175                         }
1176
1177                         if (mask)
1178                         {
1179                                 arm7_9->write_core_regs(target, mask, regs);
1180                         }
1181
1182                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1183                         reg_arch_info = reg->arch_info;
1184                         if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1185                         {
1186                                 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1187                                 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1188                         }
1189                 }
1190         }
1191
1192         if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1193         {
1194                 /* restore processor mode */
1195                 u32 tmp_cpsr;
1196
1197                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1198                 tmp_cpsr |= armv4_5_number_to_mode(i);
1199                 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1200                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1201         }
1202         else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1203         {
1204                 /* CPSR has been changed, full restore necessary */
1205                 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1206                 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), 0);
1207                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1208                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1209         }
1210
1211         /* restore PC */
1212         DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1213         arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1214         armv4_5->core_cache->reg_list[15].dirty = 0;
1215
1216         if (arm7_9->post_restore_context)
1217                 arm7_9->post_restore_context(target);
1218
1219         return ERROR_OK;
1220 }
1221
1222 int arm7_9_restart_core(struct target_s *target)
1223 {
1224         armv4_5_common_t *armv4_5 = target->arch_info;
1225         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1226         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1227
1228         /* set RESTART instruction */
1229         jtag_add_end_state(TAP_RTI);
1230         arm_jtag_set_instr(jtag_info, 0x4);
1231
1232         jtag_add_runtest(1, TAP_RTI);
1233         if ((jtag_execute_queue()) != ERROR_OK)
1234         {
1235                 exit(-1);
1236         }
1237
1238         return ERROR_OK;
1239 }
1240
1241 void arm7_9_enable_watchpoints(struct target_s *target)
1242 {
1243         watchpoint_t *watchpoint = target->watchpoints;
1244
1245         while (watchpoint)
1246         {
1247                 if (watchpoint->set == 0)
1248                         arm7_9_set_watchpoint(target, watchpoint);
1249                 watchpoint = watchpoint->next;
1250         }
1251 }
1252
1253 void arm7_9_enable_breakpoints(struct target_s *target)
1254 {
1255         breakpoint_t *breakpoint = target->breakpoints;
1256
1257         /* set any pending breakpoints */
1258         while (breakpoint)
1259         {
1260                 if (breakpoint->set == 0)
1261                         arm7_9_set_breakpoint(target, breakpoint);
1262                 breakpoint = breakpoint->next;
1263         }
1264 }
1265
1266 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1267 {
1268         breakpoint_t *breakpoint = target->breakpoints;
1269         watchpoint_t *watchpoint = target->watchpoints;
1270
1271         /* set any pending breakpoints */
1272         while (breakpoint)
1273         {
1274                 if (breakpoint->set != 0)
1275                         arm7_9_unset_breakpoint(target, breakpoint);
1276                 breakpoint = breakpoint->next;
1277         }
1278
1279         while (watchpoint)
1280         {
1281                 if (watchpoint->set != 0)
1282                         arm7_9_unset_watchpoint(target, watchpoint);
1283                 watchpoint = watchpoint->next;
1284         }
1285 }
1286
1287 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1288 {
1289         armv4_5_common_t *armv4_5 = target->arch_info;
1290         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1291         breakpoint_t *breakpoint = target->breakpoints;
1292         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1293
1294         DEBUG("");
1295
1296         if (target->state != TARGET_HALTED)
1297         {
1298                 WARNING("target not halted");
1299                 return ERROR_TARGET_NOT_HALTED;
1300         }
1301
1302         if (!debug_execution)
1303         {
1304                 target_free_all_working_areas(target);
1305         }
1306
1307         /* current = 1: continue on current pc, otherwise continue at <address> */
1308         if (!current)
1309                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1310
1311         /* the front-end may request us not to handle breakpoints */
1312         if (handle_breakpoints)
1313         {
1314                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1315                 {
1316                         DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1317                         arm7_9_unset_breakpoint(target, breakpoint);
1318
1319                         DEBUG("enable single-step");
1320                         arm7_9->enable_single_step(target);
1321
1322                         target->debug_reason = DBG_REASON_SINGLESTEP;
1323
1324                         arm7_9_restore_context(target);
1325
1326                         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1327                                 arm7_9->branch_resume(target);
1328                         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1329                         {
1330                                 arm7_9->branch_resume_thumb(target);
1331                         }
1332                         else
1333                         {
1334                                 ERROR("unhandled core state");
1335                                 exit(-1);
1336                         }
1337
1338                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1339                         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1340                         arm7_9_execute_sys_speed(target);
1341
1342                         DEBUG("disable single-step");
1343                         arm7_9->disable_single_step(target);
1344
1345                         arm7_9_debug_entry(target);
1346                         DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1347
1348                         DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1349                         arm7_9_set_breakpoint(target, breakpoint);
1350                 }
1351         }
1352
1353         /* enable any pending breakpoints and watchpoints */
1354         arm7_9_enable_breakpoints(target);
1355         arm7_9_enable_watchpoints(target);
1356
1357         arm7_9_restore_context(target);
1358
1359         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1360         {
1361                 arm7_9->branch_resume(target);
1362         }
1363         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1364         {
1365                 arm7_9->branch_resume_thumb(target);
1366         }
1367         else
1368         {
1369                 ERROR("unhandled core state");
1370                 exit(-1);
1371         }
1372
1373         /* deassert DBGACK and INTDIS */
1374         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1375         /* INTDIS only when we really resume, not during debug execution */
1376         if (!debug_execution)
1377                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1378         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1379
1380         arm7_9_restart_core(target);
1381
1382         target->debug_reason = DBG_REASON_NOTHALTED;
1383
1384         if (!debug_execution)
1385         {
1386                 /* registers are now invalid */
1387                 armv4_5_invalidate_core_regs(target);
1388                 target->state = TARGET_RUNNING;
1389                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1390         }
1391         else
1392         {
1393                 target->state = TARGET_DEBUG_RUNNING;
1394                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1395         }
1396
1397         DEBUG("target resumed");
1398
1399         return ERROR_OK;
1400 }
1401
1402 void arm7_9_enable_eice_step(target_t *target)
1403 {
1404         armv4_5_common_t *armv4_5 = target->arch_info;
1405         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1406
1407         /* setup an inverse breakpoint on the current PC
1408         * - comparator 1 matches the current address
1409         * - rangeout from comparator 1 is connected to comparator 0 rangein
1410         * - comparator 0 matches any address, as long as rangein is low */
1411         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1412         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1413         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1414         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1415         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1416         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1417         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1418         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1419         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1420 }
1421
1422 void arm7_9_disable_eice_step(target_t *target)
1423 {
1424         armv4_5_common_t *armv4_5 = target->arch_info;
1425         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1426
1427         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1428         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1429         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1430         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1431         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1432         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1433         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1434         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1435         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1436 }
1437
1438 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1439 {
1440         armv4_5_common_t *armv4_5 = target->arch_info;
1441         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1442         breakpoint_t *breakpoint = target->breakpoints;
1443
1444         if (target->state != TARGET_HALTED)
1445         {
1446                 WARNING("target not halted");
1447                 return ERROR_TARGET_NOT_HALTED;
1448         }
1449
1450         /* current = 1: continue on current pc, otherwise continue at <address> */
1451         if (!current)
1452                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1453
1454         /* the front-end may request us not to handle breakpoints */
1455         if (handle_breakpoints)
1456                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1457                         arm7_9_unset_breakpoint(target, breakpoint);
1458
1459         target->debug_reason = DBG_REASON_SINGLESTEP;
1460
1461         arm7_9_restore_context(target);
1462
1463         arm7_9->enable_single_step(target);
1464
1465         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1466         {
1467                 arm7_9->branch_resume(target);
1468         }
1469         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1470         {
1471                 arm7_9->branch_resume_thumb(target);
1472         }
1473         else
1474         {
1475                 ERROR("unhandled core state");
1476                 exit(-1);
1477         }
1478
1479         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1480
1481         arm7_9_execute_sys_speed(target);
1482         arm7_9->disable_single_step(target);
1483
1484         /* registers are now invalid */
1485         armv4_5_invalidate_core_regs(target);
1486
1487         arm7_9_debug_entry(target);
1488
1489         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1490
1491         if (breakpoint)
1492                 arm7_9_set_breakpoint(target, breakpoint);
1493
1494         DEBUG("target stepped");
1495
1496         return ERROR_OK;
1497
1498 }
1499
1500 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1501 {
1502         u32* reg_p[16];
1503         int retval;
1504         armv4_5_common_t *armv4_5 = target->arch_info;
1505         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1506         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1507
1508         if ((num < 0) || (num > 16))
1509                 return ERROR_INVALID_ARGUMENTS;
1510
1511         if ((mode != ARMV4_5_MODE_ANY)
1512                         && (mode != armv4_5->core_mode)
1513                         && (reg_mode != ARMV4_5_MODE_ANY))
1514         {
1515                 u32 tmp_cpsr;
1516
1517                 /* change processor mode */
1518                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1519                 tmp_cpsr |= mode;
1520                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1521         }
1522
1523         if ((num >= 0) && (num <= 15))
1524         {
1525                 /* read a normal core register */
1526                 reg_p[num] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value;
1527
1528                 arm7_9->read_core_regs(target, 1 << num, reg_p);
1529         }
1530         else
1531         {
1532                 /* read a program status register
1533                  * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1534                  */
1535                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1536                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1537
1538                 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, spsr);
1539         }
1540
1541         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1542         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1543
1544         if ((mode != ARMV4_5_MODE_ANY)
1545                         && (mode != armv4_5->core_mode)
1546                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1547                 /* restore processor mode */
1548                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
1549         }
1550
1551         if ((retval = jtag_execute_queue()) != ERROR_OK)
1552         {
1553                 ERROR("JTAG failure");
1554                 exit(-1);
1555         }
1556
1557         return ERROR_OK;
1558
1559 }
1560
1561 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1562 {
1563         u32 reg[16];
1564         int retval;
1565         armv4_5_common_t *armv4_5 = target->arch_info;
1566         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1567         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1568
1569         if ((num < 0) || (num > 16))
1570                 return ERROR_INVALID_ARGUMENTS;
1571
1572         if ((mode != ARMV4_5_MODE_ANY)
1573                         && (mode != armv4_5->core_mode)
1574                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1575                 u32 tmp_cpsr;
1576
1577                 /* change processor mode */
1578                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1579                 tmp_cpsr |= mode;
1580                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1581         }
1582
1583         if ((num >= 0) && (num <= 15))
1584         {
1585                 /* write a normal core register */
1586                 reg[num] = value;
1587
1588                 arm7_9->write_core_regs(target, 1 << num, reg);
1589         }
1590         else
1591         {
1592                 /* write a program status register
1593                 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1594                 */
1595                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1596                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1597
1598                 arm7_9->write_xpsr(target, value, spsr);
1599         }
1600
1601         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1602         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1603
1604         if ((mode != ARMV4_5_MODE_ANY)
1605                         && (mode != armv4_5->core_mode)
1606                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1607                 /* restore processor mode */
1608                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
1609         }
1610
1611         if ((retval = jtag_execute_queue()) != ERROR_OK)
1612         {
1613                 ERROR("JTAG failure");
1614                 exit(-1);
1615         }
1616
1617         return ERROR_OK;
1618
1619 }
1620
1621 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1622 {
1623         armv4_5_common_t *armv4_5 = target->arch_info;
1624         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1625
1626         u32 reg[16];
1627         int num_accesses = 0;
1628         int thisrun_accesses;
1629         int i;
1630         u32 cpsr;
1631         int retval;
1632         int last_reg = 0;
1633
1634         DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1635
1636         if (target->state != TARGET_HALTED)
1637         {
1638                 WARNING("target not halted");
1639                 return ERROR_TARGET_NOT_HALTED;
1640         }
1641
1642         /* sanitize arguments */
1643         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1644                 return ERROR_INVALID_ARGUMENTS;
1645
1646         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1647                 return ERROR_TARGET_UNALIGNED_ACCESS;
1648
1649         /* load the base register with the address of the first word */
1650         reg[0] = address;
1651         arm7_9->write_core_regs(target, 0x1, reg);
1652
1653         switch (size)
1654         {
1655                 case 4:
1656                         while (num_accesses < count)
1657                         {
1658                                 u32 reg_list;
1659                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1660                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1661
1662                                 if (last_reg <= thisrun_accesses)
1663                                         last_reg = thisrun_accesses;
1664
1665                                 arm7_9->load_word_regs(target, reg_list);
1666
1667                                 /* fast memory reads are only safe when the target is running
1668                                  * from a sufficiently high clock (32 kHz is usually too slow)
1669                                  */
1670                                 if (arm7_9->fast_memory_access)
1671                                         arm7_9_execute_fast_sys_speed(target);
1672                                 else
1673                                         arm7_9_execute_sys_speed(target);
1674
1675                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1676
1677                                 /* advance buffer, count number of accesses */
1678                                 buffer += thisrun_accesses * 4;
1679                                 num_accesses += thisrun_accesses;
1680                         }
1681                         break;
1682                 case 2:
1683                         while (num_accesses < count)
1684                         {
1685                                 u32 reg_list;
1686                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1687                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1688
1689                                 for (i = 1; i <= thisrun_accesses; i++)
1690                                 {
1691                                         if (i > last_reg)
1692                                                 last_reg = i;
1693                                         arm7_9->load_hword_reg(target, i);
1694                                         /* fast memory reads are only safe when the target is running
1695                                          * from a sufficiently high clock (32 kHz is usually too slow)
1696                                          */
1697                                         if (arm7_9->fast_memory_access)
1698                                                 arm7_9_execute_fast_sys_speed(target);
1699                                         else
1700                                                 arm7_9_execute_sys_speed(target);
1701                                 }
1702
1703                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1704
1705                                 /* advance buffer, count number of accesses */
1706                                 buffer += thisrun_accesses * 2;
1707                                 num_accesses += thisrun_accesses;
1708                         }
1709                         break;
1710                 case 1:
1711                         while (num_accesses < count)
1712                         {
1713                                 u32 reg_list;
1714                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1715                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1716
1717                                 for (i = 1; i <= thisrun_accesses; i++)
1718                                 {
1719                                         if (i > last_reg)
1720                                                 last_reg = i;
1721                                         arm7_9->load_byte_reg(target, i);
1722                                         /* fast memory reads are only safe when the target is running
1723                                          * from a sufficiently high clock (32 kHz is usually too slow)
1724                                          */
1725                                         if (arm7_9->fast_memory_access)
1726                                                 arm7_9_execute_fast_sys_speed(target);
1727                                         else
1728                                                 arm7_9_execute_sys_speed(target);
1729                                 }
1730
1731                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1732
1733                                 /* advance buffer, count number of accesses */
1734                                 buffer += thisrun_accesses * 1;
1735                                 num_accesses += thisrun_accesses;
1736                         }
1737                         break;
1738                 default:
1739                         ERROR("BUG: we shouldn't get here");
1740                         exit(-1);
1741                         break;
1742         }
1743
1744         for (i=0; i<=last_reg; i++)
1745                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1746
1747         arm7_9->read_xpsr(target, &cpsr, 0);
1748         if ((retval = jtag_execute_queue()) != ERROR_OK)
1749         {
1750                 ERROR("JTAG error while reading cpsr");
1751                 exit(-1);
1752         }
1753
1754         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1755         {
1756                 ERROR("memory read caused data abort");
1757
1758                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
1759
1760                 return ERROR_TARGET_DATA_ABORT;
1761         }
1762
1763         return ERROR_OK;
1764 }
1765
1766 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1767 {
1768         armv4_5_common_t *armv4_5 = target->arch_info;
1769         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1770         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1771
1772         u32 reg[16];
1773         int num_accesses = 0;
1774         int thisrun_accesses;
1775         int i;
1776         u32 cpsr;
1777         int retval;
1778         int last_reg = 0;
1779
1780         DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1781
1782         if (target->state != TARGET_HALTED)
1783         {
1784                 WARNING("target not halted");
1785                 return ERROR_TARGET_NOT_HALTED;
1786         }
1787
1788         /* sanitize arguments */
1789         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1790                 return ERROR_INVALID_ARGUMENTS;
1791
1792         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1793                 return ERROR_TARGET_UNALIGNED_ACCESS;
1794
1795         /* load the base register with the address of the first word */
1796         reg[0] = address;
1797         arm7_9->write_core_regs(target, 0x1, reg);
1798
1799         /* Clear DBGACK, to make sure memory fetches work as expected */
1800         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1801         embeddedice_store_reg(dbg_ctrl);
1802
1803         switch (size)
1804         {
1805                 case 4:
1806                         while (num_accesses < count)
1807                         {
1808                                 u32 reg_list;
1809                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1810                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1811
1812                                 for (i = 1; i <= thisrun_accesses; i++)
1813                                 {
1814                                         if (i > last_reg)
1815                                                 last_reg = i;
1816                                         reg[i] = target_buffer_get_u32(target, buffer);
1817                                         buffer += 4;
1818                                 }
1819
1820                                 arm7_9->write_core_regs(target, reg_list, reg);
1821
1822                                 arm7_9->store_word_regs(target, reg_list);
1823
1824                                 /* fast memory writes are only safe when the target is running
1825                                  * from a sufficiently high clock (32 kHz is usually too slow)
1826                                  */
1827                                 if (arm7_9->fast_memory_access)
1828                                         arm7_9_execute_fast_sys_speed(target);
1829                                 else
1830                                         arm7_9_execute_sys_speed(target);
1831
1832                                 num_accesses += thisrun_accesses;
1833                         }
1834                         break;
1835                 case 2:
1836                         while (num_accesses < count)
1837                         {
1838                                 u32 reg_list;
1839                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1840                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1841
1842                                 for (i = 1; i <= thisrun_accesses; i++)
1843                                 {
1844                                         if (i > last_reg)
1845                                                 last_reg = i;
1846                                         reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1847                                         buffer += 2;
1848                                 }
1849
1850                                 arm7_9->write_core_regs(target, reg_list, reg);
1851
1852                                 for (i = 1; i <= thisrun_accesses; i++)
1853                                 {
1854                                         arm7_9->store_hword_reg(target, i);
1855
1856                                         /* fast memory writes are only safe when the target is running
1857                                          * from a sufficiently high clock (32 kHz is usually too slow)
1858                                          */
1859                                         if (arm7_9->fast_memory_access)
1860                                                 arm7_9_execute_fast_sys_speed(target);
1861                                         else
1862                                                 arm7_9_execute_sys_speed(target);
1863                                 }
1864
1865                                 num_accesses += thisrun_accesses;
1866                         }
1867                         break;
1868                 case 1:
1869                         while (num_accesses < count)
1870                         {
1871                                 u32 reg_list;
1872                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1873                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1874
1875                                 for (i = 1; i <= thisrun_accesses; i++)
1876                                 {
1877                                         if (i > last_reg)
1878                                                 last_reg = i;
1879                                         reg[i] = *buffer++ & 0xff;
1880                                 }
1881
1882                                 arm7_9->write_core_regs(target, reg_list, reg);
1883
1884                                 for (i = 1; i <= thisrun_accesses; i++)
1885                                 {
1886                                         arm7_9->store_byte_reg(target, i);
1887                                         /* fast memory writes are only safe when the target is running
1888                                          * from a sufficiently high clock (32 kHz is usually too slow)
1889                                          */
1890                                         if (arm7_9->fast_memory_access)
1891                                                 arm7_9_execute_fast_sys_speed(target);
1892                                         else
1893                                                 arm7_9_execute_sys_speed(target);
1894                                 }
1895
1896                                 num_accesses += thisrun_accesses;
1897                         }
1898                         break;
1899                 default:
1900                         ERROR("BUG: we shouldn't get here");
1901                         exit(-1);
1902                         break;
1903         }
1904
1905         /* Re-Set DBGACK */
1906         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1907         embeddedice_store_reg(dbg_ctrl);
1908
1909         for (i=0; i<=last_reg; i++)
1910                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1911
1912         arm7_9->read_xpsr(target, &cpsr, 0);
1913         if ((retval = jtag_execute_queue()) != ERROR_OK)
1914         {
1915                 ERROR("JTAG error while reading cpsr");
1916                 exit(-1);
1917         }
1918
1919         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1920         {
1921                 ERROR("memory write caused data abort");
1922
1923                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
1924
1925                 return ERROR_TARGET_DATA_ABORT;
1926         }
1927
1928         return ERROR_OK;
1929 }
1930
1931 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
1932 {
1933         armv4_5_common_t *armv4_5 = target->arch_info;
1934         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1935         enum armv4_5_state core_state = armv4_5->core_state;
1936         u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
1937         u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
1938         u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1939         int i;
1940
1941         u32 dcc_code[] =
1942         {
1943                 /* MRC      TST         BNE         MRC         STR         B */
1944                 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1945         };
1946
1947         if (!arm7_9->dcc_downloads)
1948                 return target->type->write_memory(target, address, 4, count, buffer);
1949
1950         /* regrab previously allocated working_area, or allocate a new one */
1951         if (!arm7_9->dcc_working_area)
1952         {
1953                 u8 dcc_code_buf[6 * 4];
1954
1955                 /* make sure we have a working area */
1956                 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
1957                 {
1958                         INFO("no working area available, falling back to memory writes");
1959                         return target->type->write_memory(target, address, 4, count, buffer);
1960                 }
1961
1962                 /* copy target instructions to target endianness */
1963                 for (i = 0; i < 6; i++)
1964                 {
1965                         target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
1966                 }
1967
1968                 /* write DCC code to working area */
1969                 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
1970         }
1971
1972         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
1973         armv4_5->core_cache->reg_list[0].valid = 1;
1974         armv4_5->core_cache->reg_list[0].dirty = 1;
1975         armv4_5->core_state = ARMV4_5_STATE_ARM;
1976
1977         arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
1978
1979         for (i = 0; i < count; i++)
1980         {
1981                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
1982                 buffer += 4;
1983         }
1984
1985         target->type->halt(target);
1986
1987         while (target->state != TARGET_HALTED)
1988                 target->type->poll(target);
1989
1990         /* restore target state */
1991         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
1992         armv4_5->core_cache->reg_list[0].valid = 1;
1993         armv4_5->core_cache->reg_list[0].dirty = 1;
1994         buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
1995         armv4_5->core_cache->reg_list[1].valid = 1;
1996         armv4_5->core_cache->reg_list[1].dirty = 1;
1997         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
1998         armv4_5->core_cache->reg_list[15].valid = 1;
1999         armv4_5->core_cache->reg_list[15].dirty = 1;
2000         armv4_5->core_state = core_state;
2001
2002         return ERROR_OK;
2003 }
2004
2005 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2006 {
2007         command_t *arm7_9_cmd;
2008
2009         arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2010
2011         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2012         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2013
2014         register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2015
2016         register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2017         register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2018         register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2019                 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2020         register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2021                  COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2022         register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2023                  COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2024         register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2025                 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2026
2027         armv4_5_register_commands(cmd_ctx);
2028
2029         return ERROR_OK;
2030 }
2031
2032 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2033 {
2034         u32 value;
2035         int spsr;
2036         int retval;
2037         target_t *target = get_current_target(cmd_ctx);
2038         armv4_5_common_t *armv4_5;
2039         arm7_9_common_t *arm7_9;
2040
2041         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2042         {
2043                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2044                 return ERROR_OK;
2045         }
2046
2047         if (target->state != TARGET_HALTED)
2048         {
2049                 command_print(cmd_ctx, "can't write registers while running");
2050                 return ERROR_OK;
2051         }
2052
2053         if (argc < 2)
2054         {
2055                 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2056                 return ERROR_OK;
2057         }
2058
2059         value = strtoul(args[0], NULL, 0);
2060         spsr = strtol(args[1], NULL, 0);
2061
2062         arm7_9->write_xpsr(target, value, spsr);
2063         if ((retval = jtag_execute_queue()) != ERROR_OK)
2064         {
2065                 ERROR("JTAG error while writing to xpsr");
2066                 exit(-1);
2067         }
2068
2069         return ERROR_OK;
2070 }
2071
2072 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2073 {
2074         u32 value;
2075         int rotate;
2076         int spsr;
2077         int retval;
2078         target_t *target = get_current_target(cmd_ctx);
2079         armv4_5_common_t *armv4_5;
2080         arm7_9_common_t *arm7_9;
2081
2082         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2083         {
2084                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2085                 return ERROR_OK;
2086         }
2087
2088         if (target->state != TARGET_HALTED)
2089         {
2090                 command_print(cmd_ctx, "can't write registers while running");
2091                 return ERROR_OK;
2092         }
2093
2094         if (argc < 3)
2095         {
2096                 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2097                 return ERROR_OK;
2098         }
2099
2100         value = strtoul(args[0], NULL, 0);
2101         rotate = strtol(args[1], NULL, 0);
2102         spsr = strtol(args[2], NULL, 0);
2103
2104         arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2105         if ((retval = jtag_execute_queue()) != ERROR_OK)
2106         {
2107                 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2108                 exit(-1);
2109         }
2110
2111         return ERROR_OK;
2112 }
2113
2114 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2115 {
2116         u32 value;
2117         u32 mode;
2118         int num;
2119         target_t *target = get_current_target(cmd_ctx);
2120         armv4_5_common_t *armv4_5;
2121         arm7_9_common_t *arm7_9;
2122
2123         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2124         {
2125                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2126                 return ERROR_OK;
2127         }
2128
2129         if (target->state != TARGET_HALTED)
2130         {
2131                 command_print(cmd_ctx, "can't write registers while running");
2132                 return ERROR_OK;
2133         }
2134
2135         if (argc < 3)
2136         {
2137                 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2138                 return ERROR_OK;
2139         }
2140
2141         num = strtol(args[0], NULL, 0);
2142         mode = strtoul(args[1], NULL, 0);
2143         value = strtoul(args[2], NULL, 0);
2144
2145         arm7_9_write_core_reg(target, num, mode, value);
2146
2147         return ERROR_OK;
2148 }
2149
2150 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2151 {
2152         target_t *target = get_current_target(cmd_ctx);
2153         armv4_5_common_t *armv4_5;
2154         arm7_9_common_t *arm7_9;
2155
2156         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2157         {
2158                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2159                 return ERROR_OK;
2160         }
2161
2162         if (argc == 0)
2163         {
2164                 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2165                 return ERROR_OK;
2166         }
2167
2168         if (strcmp("enable", args[0]) == 0)
2169         {
2170                 if (arm7_9->sw_bkpts_use_wp)
2171                 {
2172                         arm7_9_enable_sw_bkpts(target);
2173                 }
2174                 else
2175                 {
2176                         arm7_9->sw_bkpts_enabled = 1;
2177                 }
2178         }
2179         else if (strcmp("disable", args[0]) == 0)
2180         {
2181                 if (arm7_9->sw_bkpts_use_wp)
2182                 {
2183                         arm7_9_disable_sw_bkpts(target);
2184                 }
2185                 else
2186                 {
2187                         arm7_9->sw_bkpts_enabled = 0;
2188                 }
2189         }
2190         else
2191         {
2192                 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2193         }
2194
2195         command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2196
2197         return ERROR_OK;
2198 }
2199
2200 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2201 {
2202         target_t *target = get_current_target(cmd_ctx);
2203         armv4_5_common_t *armv4_5;
2204         arm7_9_common_t *arm7_9;
2205
2206         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2207         {
2208                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2209                 return ERROR_OK;
2210         }
2211
2212         if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2213         {
2214                 arm7_9->force_hw_bkpts = 1;
2215                 if (arm7_9->sw_bkpts_use_wp)
2216                 {
2217                         arm7_9_disable_sw_bkpts(target);
2218                 }
2219         }
2220         else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2221         {
2222                 arm7_9->force_hw_bkpts = 0;
2223         }
2224         else
2225         {
2226                 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2227         }
2228
2229         command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2230
2231         return ERROR_OK;
2232 }
2233
2234 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2235 {
2236         target_t *target = get_current_target(cmd_ctx);
2237         armv4_5_common_t *armv4_5;
2238         arm7_9_common_t *arm7_9;
2239
2240         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2241         {
2242                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2243                 return ERROR_OK;
2244         }
2245
2246         if (argc > 0)
2247         {
2248                 if (strcmp("enable", args[0]) == 0)
2249                 {
2250                         arm7_9->use_dbgrq = 1;
2251                 }
2252                 else if (strcmp("disable", args[0]) == 0)
2253                 {
2254                         arm7_9->use_dbgrq = 0;
2255                 }
2256                 else
2257                 {
2258                         command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2259                 }
2260         }
2261
2262         command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2263
2264         return ERROR_OK;
2265 }
2266
2267 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2268 {
2269         target_t *target = get_current_target(cmd_ctx);
2270         armv4_5_common_t *armv4_5;
2271         arm7_9_common_t *arm7_9;
2272
2273         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2274         {
2275                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2276                 return ERROR_OK;
2277         }
2278
2279         if (argc > 0)
2280         {
2281                 if (strcmp("enable", args[0]) == 0)
2282                 {
2283                         arm7_9->fast_memory_access = 1;
2284                 }
2285                 else if (strcmp("disable", args[0]) == 0)
2286                 {
2287                         arm7_9->fast_memory_access = 0;
2288                 }
2289                 else
2290                 {
2291                         command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2292                 }
2293         }
2294
2295         command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2296
2297         return ERROR_OK;
2298 }
2299
2300 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2301 {
2302         target_t *target = get_current_target(cmd_ctx);
2303         armv4_5_common_t *armv4_5;
2304         arm7_9_common_t *arm7_9;
2305
2306         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2307         {
2308                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2309                 return ERROR_OK;
2310         }
2311
2312         if (argc > 0)
2313         {
2314                 if (strcmp("enable", args[0]) == 0)
2315                 {
2316                         arm7_9->dcc_downloads = 1;
2317                 }
2318                 else if (strcmp("disable", args[0]) == 0)
2319                 {
2320                         arm7_9->dcc_downloads = 0;
2321                 }
2322                 else
2323                 {
2324                         command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2325                 }
2326         }
2327
2328         command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2329
2330         return ERROR_OK;
2331 }
2332
2333 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2334 {
2335         armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2336
2337         arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2338
2339         arm_jtag_setup_connection(&arm7_9->jtag_info);
2340         arm7_9->wp_available = 2;
2341         arm7_9->wp0_used = 0;
2342         arm7_9->wp1_used = 0;
2343         arm7_9->force_hw_bkpts = 0;
2344         arm7_9->use_dbgrq = 0;
2345         arm7_9->has_etm = 0;
2346
2347         arm7_9->reinit_embeddedice = 0;
2348
2349         arm7_9->dcc_working_area = NULL;
2350
2351         arm7_9->fast_memory_access = 0;
2352         arm7_9->dcc_downloads = 0;
2353
2354         jtag_register_event_callback(arm7_9_jtag_callback, target);
2355
2356         armv4_5->arch_info = arm7_9;
2357         armv4_5->read_core_reg = arm7_9_read_core_reg;
2358         armv4_5->write_core_reg = arm7_9_write_core_reg;
2359         armv4_5->full_context = arm7_9_full_context;
2360
2361         armv4_5_init_arch_info(target, armv4_5);
2362
2363         return ERROR_OK;
2364 }