1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include <helper/time_support.h>
29 #include "target_type.h"
31 #include "arm_opcodes.h"
35 * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
36 * ARM DDI 0229C especially Chapter 9 about debug support.
40 #define _DEBUG_INSTRUCTION_EXECUTION_
43 static int arm720t_scan_cp15(struct target *target,
44 uint32_t out, uint32_t *in, int instruction, int clock_arg)
47 struct arm720t_common *arm720t = target_to_arm720(target);
48 struct arm_jtag *jtag_info;
49 struct scan_field fields[2];
51 uint8_t instruction_buf = instruction;
53 jtag_info = &arm720t->arm7_9_common.jtag_info;
55 buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
57 if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
61 if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
66 fields[0].num_bits = 1;
67 fields[0].out_value = &instruction_buf;
68 fields[0].in_value = NULL;
70 fields[1].num_bits = 32;
71 fields[1].out_value = out_buf;
72 fields[1].in_value = NULL;
76 fields[1].in_value = (uint8_t *)in;
77 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
78 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
81 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
85 jtag_add_runtest(0, TAP_DRPAUSE);
87 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
88 if ((retval = jtag_execute_queue()) != ERROR_OK)
94 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
96 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg);
98 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
104 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
106 /* fetch CP15 opcode */
107 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
109 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
110 /* "EXECUTE" stage (1) */
111 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
112 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
113 /* "EXECUTE" stage (2) */
114 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
115 /* "EXECUTE" stage (3), CDATA is read */
116 arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
121 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
123 /* fetch CP15 opcode */
124 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
126 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
127 /* "EXECUTE" stage (1) */
128 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
129 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
130 /* "EXECUTE" stage (2) */
131 arm720t_scan_cp15(target, value, NULL, 0, 1);
132 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
137 static int arm720t_get_ttb(struct target *target, uint32_t *result)
143 retval = arm720t_read_cp15(target, 0xee120f10, &ttb);
144 if (retval != ERROR_OK)
146 retval = jtag_execute_queue();
147 if (retval != ERROR_OK)
157 static int arm720t_disable_mmu_caches(struct target *target,
158 int mmu, int d_u_cache, int i_cache)
160 uint32_t cp15_control;
163 /* read cp15 control register */
164 retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
165 if (retval != ERROR_OK)
167 retval = jtag_execute_queue();
168 if (retval != ERROR_OK)
172 cp15_control &= ~0x1U;
174 if (d_u_cache || i_cache)
175 cp15_control &= ~0x4U;
177 retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
181 static int arm720t_enable_mmu_caches(struct target *target,
182 int mmu, int d_u_cache, int i_cache)
184 uint32_t cp15_control;
187 /* read cp15 control register */
188 retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
189 if (retval != ERROR_OK)
191 retval = jtag_execute_queue();
192 if (retval != ERROR_OK)
196 cp15_control |= 0x1U;
198 if (d_u_cache || i_cache)
199 cp15_control |= 0x4U;
201 retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
205 static void arm720t_post_debug_entry(struct target *target)
207 struct arm720t_common *arm720t = target_to_arm720(target);
209 /* examine cp15 control reg */
210 arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
211 jtag_execute_queue();
212 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
214 arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
215 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
216 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
218 /* save i/d fault status and address register */
219 arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
220 arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
221 jtag_execute_queue();
224 static void arm720t_pre_restore_context(struct target *target)
226 struct arm720t_common *arm720t = target_to_arm720(target);
228 /* restore i/d fault status and address register */
229 arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
230 arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
233 static int arm720t_verify_pointer(struct command_context *cmd_ctx,
234 struct arm720t_common *arm720t)
236 if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
237 command_print(cmd_ctx, "target is not an ARM720");
238 return ERROR_TARGET_INVALID;
243 static int arm720t_arch_state(struct target *target)
245 struct arm720t_common *arm720t = target_to_arm720(target);
248 static const char *state[] =
250 "disabled", "enabled"
253 armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
255 arm_arch_state(target);
256 LOG_USER("MMU: %s, Cache: %s",
257 state[arm720t->armv4_5_mmu.mmu_enabled],
258 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
263 static int arm720_mmu(struct target *target, int *enabled)
265 if (target->state != TARGET_HALTED) {
266 LOG_ERROR("%s: target not halted", __func__);
267 return ERROR_TARGET_INVALID;
270 *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
274 static int arm720_virt2phys(struct target *target,
275 uint32_t virtual, uint32_t *physical)
278 struct arm720t_common *arm720t = target_to_arm720(target);
281 int retval = armv4_5_mmu_translate_va(target,
282 &arm720t->armv4_5_mmu, virtual, &cb, &ret);
283 if (retval != ERROR_OK)
289 static int arm720t_read_memory(struct target *target,
290 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
293 struct arm720t_common *arm720t = target_to_arm720(target);
295 /* disable cache, but leave MMU enabled */
296 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
298 retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
299 if (retval != ERROR_OK)
302 retval = arm7_9_read_memory(target, address, size, count, buffer);
304 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
306 retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
307 if (retval != ERROR_OK)
314 static int arm720t_read_phys_memory(struct target *target,
315 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
317 struct arm720t_common *arm720t = target_to_arm720(target);
319 return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
322 static int arm720t_write_phys_memory(struct target *target,
323 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
325 struct arm720t_common *arm720t = target_to_arm720(target);
327 return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
330 static int arm720t_soft_reset_halt(struct target *target)
332 int retval = ERROR_OK;
333 struct arm720t_common *arm720t = target_to_arm720(target);
334 struct reg *dbg_stat = &arm720t->arm7_9_common
335 .eice_cache->reg_list[EICE_DBG_STAT];
336 struct arm *armv4_5 = &arm720t->arm7_9_common
339 if ((retval = target_halt(target)) != ERROR_OK)
344 long long then = timeval_ms();
346 while (!(timeout = ((timeval_ms()-then) > 1000)))
348 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
350 embeddedice_read_reg(dbg_stat);
351 if ((retval = jtag_execute_queue()) != ERROR_OK)
359 if (debug_level >= 3)
369 LOG_ERROR("Failed to halt CPU after 1 sec");
370 return ERROR_TARGET_TIMEOUT;
373 target->state = TARGET_HALTED;
375 /* SVC, ARM state, IRQ and FIQ disabled */
378 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
381 arm_set_cpsr(armv4_5, cpsr);
382 armv4_5->cpsr->dirty = 1;
384 /* start fetching from 0x0 */
385 buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
386 armv4_5->pc->dirty = 1;
387 armv4_5->pc->valid = 1;
389 retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
390 if (retval != ERROR_OK)
392 arm720t->armv4_5_mmu.mmu_enabled = 0;
393 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
394 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
396 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
404 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
406 return arm7tdmi_init_target(cmd_ctx, target);
409 /* FIXME remove forward decls */
410 static int arm720t_mrc(struct target *target, int cpnum,
411 uint32_t op1, uint32_t op2,
412 uint32_t CRn, uint32_t CRm,
414 static int arm720t_mcr(struct target *target, int cpnum,
415 uint32_t op1, uint32_t op2,
416 uint32_t CRn, uint32_t CRm,
419 static int arm720t_init_arch_info(struct target *target,
420 struct arm720t_common *arm720t, struct jtag_tap *tap)
422 struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
424 arm7_9->armv4_5_common.mrc = arm720t_mrc;
425 arm7_9->armv4_5_common.mcr = arm720t_mcr;
427 arm7tdmi_init_arch_info(target, arm7_9, tap);
429 arm720t->common_magic = ARM720T_COMMON_MAGIC;
431 arm7_9->post_debug_entry = arm720t_post_debug_entry;
432 arm7_9->pre_restore_context = arm720t_pre_restore_context;
434 arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
435 arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
436 arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
437 arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
438 arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
439 arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
440 arm720t->armv4_5_mmu.has_tiny_pages = 0;
441 arm720t->armv4_5_mmu.mmu_enabled = 0;
446 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
448 struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
450 arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
451 return arm720t_init_arch_info(target, arm720t, target->tap);
454 COMMAND_HANDLER(arm720t_handle_cp15_command)
457 struct target *target = get_current_target(CMD_CTX);
458 struct arm720t_common *arm720t = target_to_arm720(target);
459 struct arm_jtag *jtag_info;
461 retval = arm720t_verify_pointer(CMD_CTX, arm720t);
462 if (retval != ERROR_OK)
465 jtag_info = &arm720t->arm7_9_common.jtag_info;
467 if (target->state != TARGET_HALTED)
469 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
473 /* one or more argument, access a single register (write if second argument is given */
477 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
482 if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
484 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
488 if ((retval = jtag_execute_queue()) != ERROR_OK)
493 command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
495 else if (CMD_ARGC == 2)
498 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
500 if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
502 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
505 command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
512 static int arm720t_mrc(struct target *target, int cpnum,
513 uint32_t op1, uint32_t op2,
514 uint32_t CRn, uint32_t CRm,
519 LOG_ERROR("Only cp15 is supported");
524 return arm720t_read_cp15(target,
525 ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
530 static int arm720t_mcr(struct target *target, int cpnum,
531 uint32_t op1, uint32_t op2,
532 uint32_t CRn, uint32_t CRm,
537 LOG_ERROR("Only cp15 is supported");
541 /* write "from" r0 */
542 return arm720t_write_cp15(target,
543 ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
547 static const struct command_registration arm720t_exec_command_handlers[] = {
550 .handler = arm720t_handle_cp15_command,
551 .mode = COMMAND_EXEC,
552 /* prefer using less error-prone "arm mcr" or "arm mrc" */
553 .help = "display/modify cp15 register using ARM opcode"
555 .usage = "instruction [value]",
557 COMMAND_REGISTRATION_DONE
560 static const struct command_registration arm720t_command_handlers[] = {
562 .chain = arm7_9_command_handlers,
567 .help = "arm720t command group",
568 .chain = arm720t_exec_command_handlers,
570 COMMAND_REGISTRATION_DONE
573 /** Holds methods for ARM720 targets. */
574 struct target_type arm720t_target =
579 .arch_state = arm720t_arch_state,
582 .resume = arm7_9_resume,
585 .assert_reset = arm7_9_assert_reset,
586 .deassert_reset = arm7_9_deassert_reset,
587 .soft_reset_halt = arm720t_soft_reset_halt,
589 .get_gdb_reg_list = arm_get_gdb_reg_list,
591 .read_memory = arm720t_read_memory,
592 .write_memory = arm7_9_write_memory,
593 .read_phys_memory = arm720t_read_phys_memory,
594 .write_phys_memory = arm720t_write_phys_memory,
596 .virt2phys = arm720_virt2phys,
598 .bulk_write_memory = arm7_9_bulk_write_memory,
600 .checksum_memory = arm_checksum_memory,
601 .blank_check_memory = arm_blank_check_memory,
603 .run_algorithm = armv4_5_run_algorithm,
605 .add_breakpoint = arm7_9_add_breakpoint,
606 .remove_breakpoint = arm7_9_remove_breakpoint,
607 .add_watchpoint = arm7_9_add_watchpoint,
608 .remove_watchpoint = arm7_9_remove_watchpoint,
610 .commands = arm720t_command_handlers,
611 .target_create = arm720t_target_create,
612 .init_target = arm720t_init_target,
613 .examine = arm7_9_examine,
614 .check_reset = arm7_9_check_reset,