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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm720t.h"
  25 #include "time_support.h"
  26 #include "target_type.h"
  27
  28
  29 #if 0
  30 #define _DEBUG_INSTRUCTION_EXECUTION_
  31 #endif
  32
  33 /* cli handling */
  34 int arm720t_register_commands(struct command_context_s *cmd_ctx);
  35
  36 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  37 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  38 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39
  40 /* forward declarations */
  41 int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
  42 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  43 int arm720t_quit(void);
  44 int arm720t_arch_state(struct target_s *target);
  45 int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  46 int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  47 int arm720t_soft_reset_halt(struct target_s *target);
  48
  49 target_type_t arm720t_target =
  50 {
  51         .name = "arm720t",
  52
  53         .poll = arm7_9_poll,
  54         .arch_state = arm720t_arch_state,
  55
  56         .halt = arm7_9_halt,
  57         .resume = arm7_9_resume,
  58         .step = arm7_9_step,
  59
  60         .assert_reset = arm7_9_assert_reset,
  61         .deassert_reset = arm7_9_deassert_reset,
  62         .soft_reset_halt = arm720t_soft_reset_halt,
  63
  64         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  65
  66         .read_memory = arm720t_read_memory,
  67         .write_memory = arm720t_write_memory,
  68         .bulk_write_memory = arm7_9_bulk_write_memory,
  69         .checksum_memory = arm7_9_checksum_memory,
  70         .blank_check_memory = arm7_9_blank_check_memory,
  71
  72         .run_algorithm = armv4_5_run_algorithm,
  73
  74         .add_breakpoint = arm7_9_add_breakpoint,
  75         .remove_breakpoint = arm7_9_remove_breakpoint,
  76         .add_watchpoint = arm7_9_add_watchpoint,
  77         .remove_watchpoint = arm7_9_remove_watchpoint,
  78
  79         .register_commands = arm720t_register_commands,
  80         .target_create = arm720t_target_create,
  81         .init_target = arm720t_init_target,
  82         .examine = arm7tdmi_examine,
  83         .quit = arm720t_quit
  84 };
  85
  86 int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruction, int clock)
  87 {
  88         int retval = ERROR_OK;
  89         armv4_5_common_t *armv4_5 = target->arch_info;
  90         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  91         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  92         scan_field_t fields[2];
  93         uint8_t out_buf[4];
  94         uint8_t instruction_buf = instruction;
  95
  96         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  97
  98         jtag_set_end_state(TAP_DRPAUSE);
  99         if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 100         {
 101                 return retval;
 102         }
 103         if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
 104         {
 105                 return retval;
 106         }
 107
 108         fields[0].tap = jtag_info->tap;
 109         fields[0].num_bits = 1;
 110         fields[0].out_value = &instruction_buf;
 111         fields[0].in_value = NULL;
 112
 113         fields[1].tap = jtag_info->tap;
 114         fields[1].num_bits = 32;
 115         fields[1].out_value = out_buf;
 116         fields[1].in_value = NULL;
 117
 118         if (in)
 119         {
 120                 fields[1].in_value = (uint8_t *)in;
 121                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 122                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
 123         } else
 124         {
 125                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 126         }
 127
 128         if (clock)
 129                 jtag_add_runtest(0, jtag_get_end_state());
 130
 131 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 132         if ((retval = jtag_execute_queue()) != ERROR_OK)
 133         {
 134                 return retval;
 135         }
 136
 137         if (in)
 138                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
 139         else
 140                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 141 #else
 142                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
 143 #endif
 144
 145         return ERROR_OK;
 146 }
 147
 148 int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value)
 149 {
 150         /* fetch CP15 opcode */
 151         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 152         /* "DECODE" stage */
 153         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 154         /* "EXECUTE" stage (1) */
 155         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 156         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 157         /* "EXECUTE" stage (2) */
 158         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 159         /* "EXECUTE" stage (3), CDATA is read */
 160         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 161
 162         return ERROR_OK;
 163 }
 164
 165 int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value)
 166 {
 167         /* fetch CP15 opcode */
 168         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 169         /* "DECODE" stage */
 170         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 171         /* "EXECUTE" stage (1) */
 172         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 173         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 174         /* "EXECUTE" stage (2) */
 175         arm720t_scan_cp15(target, value, NULL, 0, 1);
 176         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 177
 178         return ERROR_OK;
 179 }
 180
 181 uint32_t arm720t_get_ttb(target_t *target)
 182 {
 183         uint32_t ttb = 0x0;
 184
 185         arm720t_read_cp15(target, 0xee120f10, &ttb);
 186         jtag_execute_queue();
 187
 188         ttb &= 0xffffc000;
 189
 190         return ttb;
 191 }
 192
 193 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 194 {
 195         uint32_t cp15_control;
 196
 197         /* read cp15 control register */
 198         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 199         jtag_execute_queue();
 200
 201         if (mmu)
 202                 cp15_control &= ~0x1U;
 203
 204         if (d_u_cache || i_cache)
 205                 cp15_control &= ~0x4U;
 206
 207         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 208 }
 209
 210 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 211 {
 212         uint32_t cp15_control;
 213
 214         /* read cp15 control register */
 215         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 216         jtag_execute_queue();
 217
 218         if (mmu)
 219                 cp15_control |= 0x1U;
 220
 221         if (d_u_cache || i_cache)
 222                 cp15_control |= 0x4U;
 223
 224         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 225 }
 226
 227 void arm720t_post_debug_entry(target_t *target)
 228 {
 229         armv4_5_common_t *armv4_5 = target->arch_info;
 230         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 231         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 232         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 233
 234         /* examine cp15 control reg */
 235         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 236         jtag_execute_queue();
 237         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 238
 239         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 240         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 241         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 242
 243         /* save i/d fault status and address register */
 244         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 245         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 246         jtag_execute_queue();
 247 }
 248
 249 void arm720t_pre_restore_context(target_t *target)
 250 {
 251         armv4_5_common_t *armv4_5 = target->arch_info;
 252         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 253         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 254         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 255
 256         /* restore i/d fault status and address register */
 257         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 258         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 259 }
 260
 261 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
 262 {
 263         armv4_5_common_t *armv4_5 = target->arch_info;
 264         arm7_9_common_t *arm7_9;
 265         arm7tdmi_common_t *arm7tdmi;
 266         arm720t_common_t *arm720t;
 267
 268         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 269         {
 270                 return -1;
 271         }
 272
 273         arm7_9 = armv4_5->arch_info;
 274         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 275         {
 276                 return -1;
 277         }
 278
 279         arm7tdmi = arm7_9->arch_info;
 280         if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
 281         {
 282                 return -1;
 283         }
 284
 285         arm720t = arm7tdmi->arch_info;
 286         if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
 287         {
 288                 return -1;
 289         }
 290
 291         *armv4_5_p = armv4_5;
 292         *arm7_9_p = arm7_9;
 293         *arm7tdmi_p = arm7tdmi;
 294         *arm720t_p = arm720t;
 295
 296         return ERROR_OK;
 297 }
 298
 299 int arm720t_arch_state(struct target_s *target)
 300 {
 301         armv4_5_common_t *armv4_5 = target->arch_info;
 302         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 303         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 304         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 305
 306         char *state[] =
 307         {
 308                 "disabled", "enabled"
 309         };
 310
 311         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 312         {
 313                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 314                 exit(-1);
 315         }
 316
 317         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 318                         "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 319                         "MMU: %s, Cache: %s",
 320                          armv4_5_state_strings[armv4_5->core_state],
 321                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 322                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 323                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 324                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 325                          state[arm720t->armv4_5_mmu.mmu_enabled],
 326                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 327
 328         return ERROR_OK;
 329 }
 330
 331 int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 332 {
 333         int retval;
 334         armv4_5_common_t *armv4_5 = target->arch_info;
 335         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 336         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 337         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 338
 339         /* disable cache, but leave MMU enabled */
 340         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 341                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 342
 343         retval = arm7_9_read_memory(target, address, size, count, buffer);
 344
 345         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 346                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 347
 348         return retval;
 349 }
 350
 351 int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 352 {
 353         int retval;
 354
 355         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 356                 return retval;
 357
 358         return retval;
 359 }
 360
 361 int arm720t_soft_reset_halt(struct target_s *target)
 362 {
 363         int retval = ERROR_OK;
 364         armv4_5_common_t *armv4_5 = target->arch_info;
 365         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 366         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 367         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 368         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 369
 370         if ((retval = target_halt(target)) != ERROR_OK)
 371         {
 372                 return retval;
 373         }
 374
 375         long long then = timeval_ms();
 376         int timeout;
 377         while (!(timeout = ((timeval_ms()-then) > 1000)))
 378         {
 379                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 380                 {
 381                         embeddedice_read_reg(dbg_stat);
 382                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 383                         {
 384                                 return retval;
 385                         }
 386                 } else
 387                 {
 388                         break;
 389                 }
 390                 if (debug_level >= 3)
 391                 {
 392                         alive_sleep(100);
 393                 } else
 394                 {
 395                         keep_alive();
 396                 }
 397         }
 398         if (timeout)
 399         {
 400                 LOG_ERROR("Failed to halt CPU after 1 sec");
 401                 return ERROR_TARGET_TIMEOUT;
 402         }
 403
 404         target->state = TARGET_HALTED;
 405
 406         /* SVC, ARM state, IRQ and FIQ disabled */
 407         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 408         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 409         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 410
 411         /* start fetching from 0x0 */
 412         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 413         armv4_5->core_cache->reg_list[15].dirty = 1;
 414         armv4_5->core_cache->reg_list[15].valid = 1;
 415
 416         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 417         armv4_5->core_state = ARMV4_5_STATE_ARM;
 418
 419         arm720t_disable_mmu_caches(target, 1, 1, 1);
 420         arm720t->armv4_5_mmu.mmu_enabled = 0;
 421         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 422         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 423
 424         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 425         {
 426                 return retval;
 427         }
 428
 429         return ERROR_OK;
 430 }
 431
 432 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 433 {
 434         arm7tdmi_init_target(cmd_ctx, target);
 435
 436         return ERROR_OK;
 437 }
 438
 439 int arm720t_quit(void)
 440 {
 441         return ERROR_OK;
 442 }
 443
 444 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
 445 {
 446         arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
 447         arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
 448
 449         arm7tdmi_init_arch_info(target, arm7tdmi, tap);
 450
 451         arm7tdmi->arch_info = arm720t;
 452         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 453
 454         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 455         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 456
 457         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 458         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 459         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 460         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 461         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 462         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 463         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 464         arm720t->armv4_5_mmu.mmu_enabled = 0;
 465
 466         return ERROR_OK;
 467 }
 468
 469 int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
 470 {
 471         arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
 472
 473         arm720t_init_arch_info(target, arm720t, target->tap);
 474
 475         return ERROR_OK;
 476 }
 477
 478 int arm720t_register_commands(struct command_context_s *cmd_ctx)
 479 {
 480         int retval;
 481         command_t *arm720t_cmd;
 482
 483
 484         retval = arm7tdmi_register_commands(cmd_ctx);
 485
 486         arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
 487
 488         register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
 489
 490         register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 491         register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 492         register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 493
 494         register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 495         register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 496         register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 497
 498         return ERROR_OK;
 499 }
 500
 501 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 502 {
 503         int retval;
 504         target_t *target = get_current_target(cmd_ctx);
 505         armv4_5_common_t *armv4_5;
 506         arm7_9_common_t *arm7_9;
 507         arm7tdmi_common_t *arm7tdmi;
 508         arm720t_common_t *arm720t;
 509         arm_jtag_t *jtag_info;
 510
 511         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 512         {
 513                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 514                 return ERROR_OK;
 515         }
 516
 517         jtag_info = &arm7_9->jtag_info;
 518
 519         if (target->state != TARGET_HALTED)
 520         {
 521                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 522                 return ERROR_OK;
 523         }
 524
 525         /* one or more argument, access a single register (write if second argument is given */
 526         if (argc >= 1)
 527         {
 528                 uint32_t opcode = strtoul(args[0], NULL, 0);
 529
 530                 if (argc == 1)
 531                 {
 532                         uint32_t value;
 533                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 534                         {
 535                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 536                                 return ERROR_OK;
 537                         }
 538
 539                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 540                         {
 541                                 return retval;
 542                         }
 543
 544                         command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 545                 }
 546                 else if (argc == 2)
 547                 {
 548                         uint32_t value = strtoul(args[1], NULL, 0);
 549                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 550                         {
 551                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 552                                 return ERROR_OK;
 553                         }
 554                         command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 555                 }
 556         }
 557
 558         return ERROR_OK;
 559 }
 560
 561 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 562 {
 563         target_t *target = get_current_target(cmd_ctx);
 564         armv4_5_common_t *armv4_5;
 565         arm7_9_common_t *arm7_9;
 566         arm7tdmi_common_t *arm7tdmi;
 567         arm720t_common_t *arm720t;
 568         arm_jtag_t *jtag_info;
 569
 570         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 571         {
 572                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 573                 return ERROR_OK;
 574         }
 575
 576         jtag_info = &arm7_9->jtag_info;
 577
 578         if (target->state != TARGET_HALTED)
 579         {
 580                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 581                 return ERROR_OK;
 582         }
 583
 584         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 585 }
 586
 587 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 588 {
 589         target_t *target = get_current_target(cmd_ctx);
 590         armv4_5_common_t *armv4_5;
 591         arm7_9_common_t *arm7_9;
 592         arm7tdmi_common_t *arm7tdmi;
 593         arm720t_common_t *arm720t;
 594         arm_jtag_t *jtag_info;
 595
 596         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 597         {
 598                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 599                 return ERROR_OK;
 600         }
 601
 602         jtag_info = &arm7_9->jtag_info;
 603
 604         if (target->state != TARGET_HALTED)
 605         {
 606                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 607                 return ERROR_OK;
 608         }
 609
 610         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 611 }