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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm720t.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27 #include "time_support.h"
  28
  29 #include <stdlib.h>
  30 #include <string.h>
  31
  32 #if 0
  33 #define _DEBUG_INSTRUCTION_EXECUTION_
  34 #endif
  35
  36 /* cli handling */
  37 int arm720t_register_commands(struct command_context_s *cmd_ctx);
  38
  39 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43
  44 /* forward declarations */
  45 int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
  46 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  47 int arm720t_quit(void);
  48 int arm720t_arch_state(struct target_s *target);
  49 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  50 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  51 int arm720t_soft_reset_halt(struct target_s *target);
  52
  53 target_type_t arm720t_target =
  54 {
  55         .name = "arm720t",
  56
  57         .poll = arm7_9_poll,
  58         .arch_state = arm720t_arch_state,
  59
  60         .halt = arm7_9_halt,
  61         .resume = arm7_9_resume,
  62         .step = arm7_9_step,
  63
  64         .assert_reset = arm7_9_assert_reset,
  65         .deassert_reset = arm7_9_deassert_reset,
  66         .soft_reset_halt = arm720t_soft_reset_halt,
  67
  68         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  69
  70         .read_memory = arm720t_read_memory,
  71         .write_memory = arm720t_write_memory,
  72         .bulk_write_memory = arm7_9_bulk_write_memory,
  73         .checksum_memory = arm7_9_checksum_memory,
  74         .blank_check_memory = arm7_9_blank_check_memory,
  75
  76         .run_algorithm = armv4_5_run_algorithm,
  77
  78         .add_breakpoint = arm7_9_add_breakpoint,
  79         .remove_breakpoint = arm7_9_remove_breakpoint,
  80         .add_watchpoint = arm7_9_add_watchpoint,
  81         .remove_watchpoint = arm7_9_remove_watchpoint,
  82
  83         .register_commands = arm720t_register_commands,
  84         .target_create = arm720t_target_create,
  85         .init_target = arm720t_init_target,
  86         .examine = arm7tdmi_examine,
  87         .quit = arm720t_quit
  88 };
  89
  90 int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
  91 {
  92         int retval = ERROR_OK;
  93         armv4_5_common_t *armv4_5 = target->arch_info;
  94         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  95         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  96         scan_field_t fields[2];
  97         u8 out_buf[4];
  98         u8 instruction_buf = instruction;
  99
 100         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 101
 102         jtag_add_end_state(TAP_DRPAUSE);
 103         if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 104         {
 105                 return retval;
 106         }
 107         if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
 108         {
 109                 return retval;
 110         }
 111
 112         fields[0].tap = jtag_info->tap;
 113         fields[0].num_bits = 1;
 114         fields[0].out_value = &instruction_buf;
 115         fields[0].in_value = NULL;
 116
 117
 118         fields[1].tap = jtag_info->tap;
 119         fields[1].num_bits = 32;
 120         fields[1].out_value = out_buf;
 121         fields[1].in_value = NULL;
 122
 123         if (in)
 124         {
 125                 u8 tmp[4];
 126                 fields[1].in_value = tmp;
 127                 jtag_add_dr_scan_now(2, fields, TAP_INVALID);
 128                 *in=flip_u32(le_to_h_u32(tmp), 32);
 129         } else
 130         {
 131                 jtag_add_dr_scan(2, fields, TAP_INVALID);
 132         }
 133
 134         if (clock)
 135                 jtag_add_runtest(0, TAP_INVALID);
 136
 137 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 138         if((retval = jtag_execute_queue()) != ERROR_OK)
 139         {
 140                 return retval;
 141         }
 142
 143         if (in)
 144                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
 145         else
 146                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 147 #else
 148                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 149 #endif
 150
 151         return ERROR_OK;
 152 }
 153
 154 int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
 155 {
 156         /* fetch CP15 opcode */
 157         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 158         /* "DECODE" stage */
 159         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 160         /* "EXECUTE" stage (1) */
 161         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 162         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 163         /* "EXECUTE" stage (2) */
 164         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 165         /* "EXECUTE" stage (3), CDATA is read */
 166         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 167
 168         return ERROR_OK;
 169 }
 170
 171 int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
 172 {
 173         /* fetch CP15 opcode */
 174         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 175         /* "DECODE" stage */
 176         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 177         /* "EXECUTE" stage (1) */
 178         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 179         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 180         /* "EXECUTE" stage (2) */
 181         arm720t_scan_cp15(target, value, NULL, 0, 1);
 182         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 183
 184         return ERROR_OK;
 185 }
 186
 187 u32 arm720t_get_ttb(target_t *target)
 188 {
 189         u32 ttb = 0x0;
 190
 191         arm720t_read_cp15(target, 0xee120f10, &ttb);
 192         jtag_execute_queue();
 193
 194         ttb &= 0xffffc000;
 195
 196         return ttb;
 197 }
 198
 199 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 200 {
 201         u32 cp15_control;
 202
 203         /* read cp15 control register */
 204         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 205         jtag_execute_queue();
 206
 207         if (mmu)
 208                 cp15_control &= ~0x1U;
 209
 210         if (d_u_cache || i_cache)
 211                 cp15_control &= ~0x4U;
 212
 213         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 214 }
 215
 216 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 217 {
 218         u32 cp15_control;
 219
 220         /* read cp15 control register */
 221         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 222         jtag_execute_queue();
 223
 224         if (mmu)
 225                 cp15_control |= 0x1U;
 226
 227         if (d_u_cache || i_cache)
 228                 cp15_control |= 0x4U;
 229
 230         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 231 }
 232
 233 void arm720t_post_debug_entry(target_t *target)
 234 {
 235         armv4_5_common_t *armv4_5 = target->arch_info;
 236         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 237         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 238         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 239
 240         /* examine cp15 control reg */
 241         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 242         jtag_execute_queue();
 243         LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
 244
 245         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 246         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 247         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 248
 249         /* save i/d fault status and address register */
 250         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 251         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 252         jtag_execute_queue();
 253 }
 254
 255 void arm720t_pre_restore_context(target_t *target)
 256 {
 257         armv4_5_common_t *armv4_5 = target->arch_info;
 258         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 259         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 260         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 261
 262         /* restore i/d fault status and address register */
 263         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 264         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 265 }
 266
 267 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
 268 {
 269         armv4_5_common_t *armv4_5 = target->arch_info;
 270         arm7_9_common_t *arm7_9;
 271         arm7tdmi_common_t *arm7tdmi;
 272         arm720t_common_t *arm720t;
 273
 274         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 275         {
 276                 return -1;
 277         }
 278
 279         arm7_9 = armv4_5->arch_info;
 280         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 281         {
 282                 return -1;
 283         }
 284
 285         arm7tdmi = arm7_9->arch_info;
 286         if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
 287         {
 288                 return -1;
 289         }
 290
 291         arm720t = arm7tdmi->arch_info;
 292         if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
 293         {
 294                 return -1;
 295         }
 296
 297         *armv4_5_p = armv4_5;
 298         *arm7_9_p = arm7_9;
 299         *arm7tdmi_p = arm7tdmi;
 300         *arm720t_p = arm720t;
 301
 302         return ERROR_OK;
 303 }
 304
 305 int arm720t_arch_state(struct target_s *target)
 306 {
 307         armv4_5_common_t *armv4_5 = target->arch_info;
 308         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 309         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 310         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 311
 312         char *state[] =
 313         {
 314                 "disabled", "enabled"
 315         };
 316
 317         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 318         {
 319                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 320                 exit(-1);
 321         }
 322
 323         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 324                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 325                         "MMU: %s, Cache: %s",
 326                          armv4_5_state_strings[armv4_5->core_state],
 327                          Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
 328                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 329                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 330                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 331                          state[arm720t->armv4_5_mmu.mmu_enabled],
 332                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 333
 334         return ERROR_OK;
 335 }
 336
 337 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 338 {
 339         int retval;
 340         armv4_5_common_t *armv4_5 = target->arch_info;
 341         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 342         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 343         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 344
 345         /* disable cache, but leave MMU enabled */
 346         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 347                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 348
 349         retval = arm7_9_read_memory(target, address, size, count, buffer);
 350
 351         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 352                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 353
 354         return retval;
 355 }
 356
 357 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 358 {
 359         int retval;
 360
 361         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 362                 return retval;
 363
 364         return retval;
 365 }
 366
 367 int arm720t_soft_reset_halt(struct target_s *target)
 368 {
 369         int retval = ERROR_OK;
 370         armv4_5_common_t *armv4_5 = target->arch_info;
 371         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 372         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 373         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 374         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 375
 376         if ((retval = target_halt(target)) != ERROR_OK)
 377         {
 378                 return retval;
 379         }
 380
 381         long long then=timeval_ms();
 382         int timeout;
 383         while (!(timeout=((timeval_ms()-then)>1000)))
 384         {
 385                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 386                 {
 387                         embeddedice_read_reg(dbg_stat);
 388                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 389                         {
 390                                 return retval;
 391                         }
 392                 } else
 393                 {
 394                         break;
 395                 }
 396                 if (debug_level>=3)
 397                 {
 398                         alive_sleep(100);
 399                 } else
 400                 {
 401                         keep_alive();
 402                 }
 403         }
 404         if (timeout)
 405         {
 406                 LOG_ERROR("Failed to halt CPU after 1 sec");
 407                 return ERROR_TARGET_TIMEOUT;
 408         }
 409
 410         target->state = TARGET_HALTED;
 411
 412         /* SVC, ARM state, IRQ and FIQ disabled */
 413         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 414         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 415         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 416
 417         /* start fetching from 0x0 */
 418         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 419         armv4_5->core_cache->reg_list[15].dirty = 1;
 420         armv4_5->core_cache->reg_list[15].valid = 1;
 421
 422         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 423         armv4_5->core_state = ARMV4_5_STATE_ARM;
 424
 425         arm720t_disable_mmu_caches(target, 1, 1, 1);
 426         arm720t->armv4_5_mmu.mmu_enabled = 0;
 427         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 428         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 429
 430         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 431         {
 432                 return retval;
 433         }
 434
 435         return ERROR_OK;
 436 }
 437
 438 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 439 {
 440         arm7tdmi_init_target(cmd_ctx, target);
 441
 442         return ERROR_OK;
 443 }
 444
 445 int arm720t_quit(void)
 446 {
 447         return ERROR_OK;
 448 }
 449
 450 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
 451 {
 452         arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
 453         arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
 454
 455         arm7tdmi_init_arch_info(target, arm7tdmi, tap);
 456
 457         arm7tdmi->arch_info = arm720t;
 458         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 459
 460         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 461         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 462
 463         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 464         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 465         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 466         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 467         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 468         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 469         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 470         arm720t->armv4_5_mmu.mmu_enabled = 0;
 471
 472         return ERROR_OK;
 473 }
 474
 475 int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
 476 {
 477         arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
 478
 479         arm720t_init_arch_info(target, arm720t, target->tap);
 480
 481         return ERROR_OK;
 482 }
 483
 484 int arm720t_register_commands(struct command_context_s *cmd_ctx)
 485 {
 486         int retval;
 487         command_t *arm720t_cmd;
 488
 489
 490         retval = arm7tdmi_register_commands(cmd_ctx);
 491
 492         arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
 493
 494         register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
 495         register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 496
 497         register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 498         register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 499         register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 500
 501         register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 502         register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 503         register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 504
 505         return ERROR_OK;
 506 }
 507
 508 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 509 {
 510         int retval;
 511         target_t *target = get_current_target(cmd_ctx);
 512         armv4_5_common_t *armv4_5;
 513         arm7_9_common_t *arm7_9;
 514         arm7tdmi_common_t *arm7tdmi;
 515         arm720t_common_t *arm720t;
 516         arm_jtag_t *jtag_info;
 517
 518         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 519         {
 520                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 521                 return ERROR_OK;
 522         }
 523
 524         jtag_info = &arm7_9->jtag_info;
 525
 526         if (target->state != TARGET_HALTED)
 527         {
 528                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 529                 return ERROR_OK;
 530         }
 531
 532         /* one or more argument, access a single register (write if second argument is given */
 533         if (argc >= 1)
 534         {
 535                 u32 opcode = strtoul(args[0], NULL, 0);
 536
 537                 if (argc == 1)
 538                 {
 539                         u32 value;
 540                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 541                         {
 542                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
 543                                 return ERROR_OK;
 544                         }
 545
 546                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 547                         {
 548                                 return retval;
 549                         }
 550
 551                         command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
 552                 }
 553                 else if (argc == 2)
 554                 {
 555                         u32 value = strtoul(args[1], NULL, 0);
 556                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 557                         {
 558                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
 559                                 return ERROR_OK;
 560                         }
 561                         command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
 562                 }
 563         }
 564
 565         return ERROR_OK;
 566 }
 567
 568 int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 569 {
 570         target_t *target = get_current_target(cmd_ctx);
 571         armv4_5_common_t *armv4_5;
 572         arm7_9_common_t *arm7_9;
 573         arm7tdmi_common_t *arm7tdmi;
 574         arm720t_common_t *arm720t;
 575         arm_jtag_t *jtag_info;
 576
 577         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 578         {
 579                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 580                 return ERROR_OK;
 581         }
 582
 583         jtag_info = &arm7_9->jtag_info;
 584
 585         if (target->state != TARGET_HALTED)
 586         {
 587                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 588                 return ERROR_OK;
 589         }
 590
 591         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 592 }
 593
 594 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 595 {
 596         target_t *target = get_current_target(cmd_ctx);
 597         armv4_5_common_t *armv4_5;
 598         arm7_9_common_t *arm7_9;
 599         arm7tdmi_common_t *arm7tdmi;
 600         arm720t_common_t *arm720t;
 601         arm_jtag_t *jtag_info;
 602
 603         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 604         {
 605                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 606                 return ERROR_OK;
 607         }
 608
 609         jtag_info = &arm7_9->jtag_info;
 610
 611         if (target->state != TARGET_HALTED)
 612         {
 613                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 614                 return ERROR_OK;
 615         }
 616
 617         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 618 }
 619
 620 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 621 {
 622         target_t *target = get_current_target(cmd_ctx);
 623         armv4_5_common_t *armv4_5;
 624         arm7_9_common_t *arm7_9;
 625         arm7tdmi_common_t *arm7tdmi;
 626         arm720t_common_t *arm720t;
 627         arm_jtag_t *jtag_info;
 628
 629         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 630         {
 631                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 632                 return ERROR_OK;
 633         }
 634
 635         jtag_info = &arm7_9->jtag_info;
 636
 637         if (target->state != TARGET_HALTED)
 638         {
 639                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 640                 return ERROR_OK;
 641         }
 642
 643         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 644 }