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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "arm720t.h"
  28 #include <helper/time_support.h>
  29 #include "target_type.h"
  30 #include "register.h"
  31 #include "arm_opcodes.h"
  32
  33
  34 /*
  35  * ARM720 is an ARM7TDMI-S with MMU and ETM7.  For information, see
  36  * ARM DDI 0229C especially Chapter 9 about debug support.
  37  */
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 static int arm720t_scan_cp15(struct target *target,
  44                 uint32_t out, uint32_t *in, int instruction, int clock)
  45 {
  46         int retval;
  47         struct arm720t_common *arm720t = target_to_arm720(target);
  48         struct arm_jtag *jtag_info;
  49         struct scan_field fields[2];
  50         uint8_t out_buf[4];
  51         uint8_t instruction_buf = instruction;
  52
  53         jtag_info = &arm720t->arm7_9_common.jtag_info;
  54
  55         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  56
  57         jtag_set_end_state(TAP_DRPAUSE);
  58         if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  59         {
  60                 return retval;
  61         }
  62         if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
  63         {
  64                 return retval;
  65         }
  66
  67         fields[0].tap = jtag_info->tap;
  68         fields[0].num_bits = 1;
  69         fields[0].out_value = &instruction_buf;
  70         fields[0].in_value = NULL;
  71
  72         fields[1].tap = jtag_info->tap;
  73         fields[1].num_bits = 32;
  74         fields[1].out_value = out_buf;
  75         fields[1].in_value = NULL;
  76
  77         if (in)
  78         {
  79                 fields[1].in_value = (uint8_t *)in;
  80                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
  81                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
  82         } else
  83         {
  84                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
  85         }
  86
  87         if (clock)
  88                 jtag_add_runtest(0, jtag_get_end_state());
  89
  90 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  91         if ((retval = jtag_execute_queue()) != ERROR_OK)
  92         {
  93                 return retval;
  94         }
  95
  96         if (in)
  97                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
  98         else
  99                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 100 #else
 101                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
 102 #endif
 103
 104         return ERROR_OK;
 105 }
 106
 107 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
 108 {
 109         /* fetch CP15 opcode */
 110         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 111         /* "DECODE" stage */
 112         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 113         /* "EXECUTE" stage (1) */
 114         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 115         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 116         /* "EXECUTE" stage (2) */
 117         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 118         /* "EXECUTE" stage (3), CDATA is read */
 119         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 120
 121         return ERROR_OK;
 122 }
 123
 124 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
 125 {
 126         /* fetch CP15 opcode */
 127         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 128         /* "DECODE" stage */
 129         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 130         /* "EXECUTE" stage (1) */
 131         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 132         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 133         /* "EXECUTE" stage (2) */
 134         arm720t_scan_cp15(target, value, NULL, 0, 1);
 135         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 136
 137         return ERROR_OK;
 138 }
 139
 140 static uint32_t arm720t_get_ttb(struct target *target)
 141 {
 142         uint32_t ttb = 0x0;
 143
 144         arm720t_read_cp15(target, 0xee120f10, &ttb);
 145         jtag_execute_queue();
 146
 147         ttb &= 0xffffc000;
 148
 149         return ttb;
 150 }
 151
 152 static void arm720t_disable_mmu_caches(struct target *target,
 153                 int mmu, int d_u_cache, int i_cache)
 154 {
 155         uint32_t cp15_control;
 156
 157         /* read cp15 control register */
 158         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 159         jtag_execute_queue();
 160
 161         if (mmu)
 162                 cp15_control &= ~0x1U;
 163
 164         if (d_u_cache || i_cache)
 165                 cp15_control &= ~0x4U;
 166
 167         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 168 }
 169
 170 static void arm720t_enable_mmu_caches(struct target *target,
 171                 int mmu, int d_u_cache, int i_cache)
 172 {
 173         uint32_t cp15_control;
 174
 175         /* read cp15 control register */
 176         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 177         jtag_execute_queue();
 178
 179         if (mmu)
 180                 cp15_control |= 0x1U;
 181
 182         if (d_u_cache || i_cache)
 183                 cp15_control |= 0x4U;
 184
 185         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 186 }
 187
 188 static void arm720t_post_debug_entry(struct target *target)
 189 {
 190         struct arm720t_common *arm720t = target_to_arm720(target);
 191
 192         /* examine cp15 control reg */
 193         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 194         jtag_execute_queue();
 195         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 196
 197         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 198         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 199         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 200
 201         /* save i/d fault status and address register */
 202         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 203         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 204         jtag_execute_queue();
 205 }
 206
 207 static void arm720t_pre_restore_context(struct target *target)
 208 {
 209         struct arm720t_common *arm720t = target_to_arm720(target);
 210
 211         /* restore i/d fault status and address register */
 212         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 213         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 214 }
 215
 216 static int arm720t_verify_pointer(struct command_context *cmd_ctx,
 217                 struct arm720t_common *arm720t)
 218 {
 219         if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
 220                 command_print(cmd_ctx, "target is not an ARM720");
 221                 return ERROR_TARGET_INVALID;
 222         }
 223         return ERROR_OK;
 224 }
 225
 226 static int arm720t_arch_state(struct target *target)
 227 {
 228         struct arm720t_common *arm720t = target_to_arm720(target);
 229         struct arm *armv4_5;
 230
 231         static const char *state[] =
 232         {
 233                 "disabled", "enabled"
 234         };
 235
 236         armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
 237
 238         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 239                         "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 240                         "MMU: %s, Cache: %s",
 241                          arm_state_strings[armv4_5->core_state],
 242                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 243                          arm_mode_name(armv4_5->core_mode),
 244                          buf_get_u32(armv4_5->cpsr->value, 0, 32),
 245                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 246                          state[arm720t->armv4_5_mmu.mmu_enabled],
 247                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 248
 249         return ERROR_OK;
 250 }
 251
 252 static int arm720_mmu(struct target *target, int *enabled)
 253 {
 254         if (target->state != TARGET_HALTED) {
 255                 LOG_ERROR("%s: target not halted", __func__);
 256                 return ERROR_TARGET_INVALID;
 257         }
 258
 259         *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
 260         return ERROR_OK;
 261 }
 262
 263 static int arm720_virt2phys(struct target *target,
 264                 uint32_t virt, uint32_t *phys)
 265 {
 266         /** @todo Implement this!  */
 267         LOG_ERROR("%s: not implemented", __func__);
 268         return ERROR_FAIL;
 269 }
 270
 271 static int arm720t_read_memory(struct target *target,
 272                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 273 {
 274         int retval;
 275         struct arm720t_common *arm720t = target_to_arm720(target);
 276
 277         /* disable cache, but leave MMU enabled */
 278         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 279                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 280
 281         retval = arm7_9_read_memory(target, address, size, count, buffer);
 282
 283         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 284                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 285
 286         return retval;
 287 }
 288
 289 static int arm720t_read_phys_memory(struct target *target,
 290                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 291 {
 292         struct arm720t_common *arm720t = target_to_arm720(target);
 293
 294         return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 295 }
 296
 297 static int arm720t_write_phys_memory(struct target *target,
 298                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 299 {
 300         struct arm720t_common *arm720t = target_to_arm720(target);
 301
 302         return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 303 }
 304
 305 static int arm720t_soft_reset_halt(struct target *target)
 306 {
 307         int retval = ERROR_OK;
 308         struct arm720t_common *arm720t = target_to_arm720(target);
 309         struct reg *dbg_stat = &arm720t->arm7_9_common
 310                         .eice_cache->reg_list[EICE_DBG_STAT];
 311         struct arm *armv4_5 = &arm720t->arm7_9_common
 312                         .armv4_5_common;
 313
 314         if ((retval = target_halt(target)) != ERROR_OK)
 315         {
 316                 return retval;
 317         }
 318
 319         long long then = timeval_ms();
 320         int timeout;
 321         while (!(timeout = ((timeval_ms()-then) > 1000)))
 322         {
 323                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 324                 {
 325                         embeddedice_read_reg(dbg_stat);
 326                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 327                         {
 328                                 return retval;
 329                         }
 330                 } else
 331                 {
 332                         break;
 333                 }
 334                 if (debug_level >= 3)
 335                 {
 336                         alive_sleep(100);
 337                 } else
 338                 {
 339                         keep_alive();
 340                 }
 341         }
 342         if (timeout)
 343         {
 344                 LOG_ERROR("Failed to halt CPU after 1 sec");
 345                 return ERROR_TARGET_TIMEOUT;
 346         }
 347
 348         target->state = TARGET_HALTED;
 349
 350         /* SVC, ARM state, IRQ and FIQ disabled */
 351         uint32_t cpsr;
 352
 353         cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
 354         cpsr &= ~0xff;
 355         cpsr |= 0xd3;
 356         arm_set_cpsr(armv4_5, cpsr);
 357         armv4_5->cpsr->dirty = 1;
 358
 359         /* start fetching from 0x0 */
 360         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 361         armv4_5->core_cache->reg_list[15].dirty = 1;
 362         armv4_5->core_cache->reg_list[15].valid = 1;
 363
 364         arm720t_disable_mmu_caches(target, 1, 1, 1);
 365         arm720t->armv4_5_mmu.mmu_enabled = 0;
 366         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 367         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 368
 369         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 370         {
 371                 return retval;
 372         }
 373
 374         return ERROR_OK;
 375 }
 376
 377 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
 378 {
 379         return arm7tdmi_init_target(cmd_ctx, target);
 380 }
 381
 382 /* FIXME remove forward decls */
 383 static int arm720t_mrc(struct target *target, int cpnum,
 384                 uint32_t op1, uint32_t op2,
 385                 uint32_t CRn, uint32_t CRm,
 386                 uint32_t *value);
 387 static int arm720t_mcr(struct target *target, int cpnum,
 388                 uint32_t op1, uint32_t op2,
 389                 uint32_t CRn, uint32_t CRm,
 390                 uint32_t value);
 391
 392 static int arm720t_init_arch_info(struct target *target,
 393                 struct arm720t_common *arm720t, struct jtag_tap *tap)
 394 {
 395         struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
 396
 397         arm7_9->armv4_5_common.mrc = arm720t_mrc;
 398         arm7_9->armv4_5_common.mcr = arm720t_mcr;
 399
 400         arm7tdmi_init_arch_info(target, arm7_9, tap);
 401
 402         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 403
 404         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 405         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 406
 407         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 408         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 409         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 410         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 411         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 412         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 413         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 414         arm720t->armv4_5_mmu.mmu_enabled = 0;
 415
 416         return ERROR_OK;
 417 }
 418
 419 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
 420 {
 421         struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
 422
 423         arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
 424         return arm720t_init_arch_info(target, arm720t, target->tap);
 425 }
 426
 427 COMMAND_HANDLER(arm720t_handle_cp15_command)
 428 {
 429         int retval;
 430         struct target *target = get_current_target(CMD_CTX);
 431         struct arm720t_common *arm720t = target_to_arm720(target);
 432         struct arm_jtag *jtag_info;
 433
 434         retval = arm720t_verify_pointer(CMD_CTX, arm720t);
 435         if (retval != ERROR_OK)
 436                 return retval;
 437
 438         jtag_info = &arm720t->arm7_9_common.jtag_info;
 439
 440         if (target->state != TARGET_HALTED)
 441         {
 442                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 443                 return ERROR_OK;
 444         }
 445
 446         /* one or more argument, access a single register (write if second argument is given */
 447         if (CMD_ARGC >= 1)
 448         {
 449                 uint32_t opcode;
 450                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
 451
 452                 if (CMD_ARGC == 1)
 453                 {
 454                         uint32_t value;
 455                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 456                         {
 457                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 458                                 return ERROR_OK;
 459                         }
 460
 461                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 462                         {
 463                                 return retval;
 464                         }
 465
 466                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 467                 }
 468                 else if (CMD_ARGC == 2)
 469                 {
 470                         uint32_t value;
 471                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 472
 473                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 474                         {
 475                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 476                                 return ERROR_OK;
 477                         }
 478                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 479                 }
 480         }
 481
 482         return ERROR_OK;
 483 }
 484
 485 static int arm720t_mrc(struct target *target, int cpnum,
 486                 uint32_t op1, uint32_t op2,
 487                 uint32_t CRn, uint32_t CRm,
 488                 uint32_t *value)
 489 {
 490         if (cpnum!=15)
 491         {
 492                 LOG_ERROR("Only cp15 is supported");
 493                 return ERROR_FAIL;
 494         }
 495
 496         /* read "to" r0 */
 497         return arm720t_read_cp15(target,
 498                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
 499                         value);
 500
 501 }
 502
 503 static int arm720t_mcr(struct target *target, int cpnum,
 504                 uint32_t op1, uint32_t op2,
 505                 uint32_t CRn, uint32_t CRm,
 506                 uint32_t value)
 507 {
 508         if (cpnum!=15)
 509         {
 510                 LOG_ERROR("Only cp15 is supported");
 511                 return ERROR_FAIL;
 512         }
 513
 514         /* write "from" r0 */
 515         return arm720t_write_cp15(target,
 516                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
 517                         value);
 518 }
 519
 520 static const struct command_registration arm720t_exec_command_handlers[] = {
 521         {
 522                 .name = "cp15",
 523                 .handler = arm720t_handle_cp15_command,
 524                 .mode = COMMAND_EXEC,
 525                 .usage = "<opcode> [value]",
 526                 .help = "display/modify cp15 register",
 527         },
 528         COMMAND_REGISTRATION_DONE
 529 };
 530
 531 static const struct command_registration arm720t_command_handlers[] = {
 532         {
 533                 .chain = arm7_9_command_handlers,
 534         },
 535         {
 536                 .name = "arm720t",
 537                 .mode = COMMAND_ANY,
 538                 .help = "arm720t command group",
 539                 .chain = arm720t_exec_command_handlers,
 540         },
 541         COMMAND_REGISTRATION_DONE
 542 };
 543
 544 /** Holds methods for ARM720 targets. */
 545 struct target_type arm720t_target =
 546 {
 547         .name = "arm720t",
 548
 549         .poll = arm7_9_poll,
 550         .arch_state = arm720t_arch_state,
 551
 552         .halt = arm7_9_halt,
 553         .resume = arm7_9_resume,
 554         .step = arm7_9_step,
 555
 556         .assert_reset = arm7_9_assert_reset,
 557         .deassert_reset = arm7_9_deassert_reset,
 558         .soft_reset_halt = arm720t_soft_reset_halt,
 559
 560         .get_gdb_reg_list = arm_get_gdb_reg_list,
 561
 562         .read_memory = arm720t_read_memory,
 563         .write_memory = arm7_9_write_memory,
 564         .read_phys_memory = arm720t_read_phys_memory,
 565         .write_phys_memory = arm720t_write_phys_memory,
 566         .mmu = arm720_mmu,
 567         .virt2phys = arm720_virt2phys,
 568
 569         .bulk_write_memory = arm7_9_bulk_write_memory,
 570
 571         .checksum_memory = arm_checksum_memory,
 572         .blank_check_memory = arm_blank_check_memory,
 573
 574         .run_algorithm = armv4_5_run_algorithm,
 575
 576         .add_breakpoint = arm7_9_add_breakpoint,
 577         .remove_breakpoint = arm7_9_remove_breakpoint,
 578         .add_watchpoint = arm7_9_add_watchpoint,
 579         .remove_watchpoint = arm7_9_remove_watchpoint,
 580
 581         .commands = arm720t_command_handlers,
 582         .target_create = arm720t_target_create,
 583         .init_target = arm720t_init_target,
 584         .examine = arm7_9_examine,
 585 };