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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm720t.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30
  31 #if 0
  32 #define _DEBUG_INSTRUCTION_EXECUTION_
  33 #endif
  34
  35 /* cli handling */
  36 int arm720t_register_commands(struct command_context_s *cmd_ctx);
  37
  38 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42
  43 /* forward declarations */
  44 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  45 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  46 int arm720t_quit(void);
  47 int arm720t_arch_state(struct target_s *target);
  48 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  49 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  50 int arm720t_soft_reset_halt(struct target_s *target);
  51
  52 target_type_t arm720t_target =
  53 {
  54         .name = "arm720t",
  55
  56         .poll = arm7_9_poll,
  57         .arch_state = arm720t_arch_state,
  58
  59         .halt = arm7_9_halt,
  60         .resume = arm7_9_resume,
  61         .step = arm7_9_step,
  62
  63         .assert_reset = arm7_9_assert_reset,
  64         .deassert_reset = arm7_9_deassert_reset,
  65         .soft_reset_halt = arm720t_soft_reset_halt,
  66
  67         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  68
  69         .read_memory = arm720t_read_memory,
  70         .write_memory = arm720t_write_memory,
  71         .bulk_write_memory = arm7_9_bulk_write_memory,
  72         .checksum_memory = arm7_9_checksum_memory,
  73         .blank_check_memory = arm7_9_blank_check_memory,
  74
  75         .run_algorithm = armv4_5_run_algorithm,
  76
  77         .add_breakpoint = arm7_9_add_breakpoint,
  78         .remove_breakpoint = arm7_9_remove_breakpoint,
  79         .add_watchpoint = arm7_9_add_watchpoint,
  80         .remove_watchpoint = arm7_9_remove_watchpoint,
  81
  82         .register_commands = arm720t_register_commands,
  83         .target_command = arm720t_target_command,
  84         .init_target = arm720t_init_target,
  85         .examine = arm7tdmi_examine,
  86         .quit = arm720t_quit
  87 };
  88
  89 int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
  90 {
  91         armv4_5_common_t *armv4_5 = target->arch_info;
  92         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  93         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  94         scan_field_t fields[2];
  95         u8 out_buf[4];
  96         u8 instruction_buf = instruction;
  97
  98         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  99
 100         jtag_add_end_state(TAP_PD);
 101         arm_jtag_scann(jtag_info, 0xf);
 102         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 103
 104         fields[0].device = jtag_info->chain_pos;
 105         fields[0].num_bits = 1;
 106         fields[0].out_value = &instruction_buf;
 107         fields[0].out_mask = NULL;
 108         fields[0].in_value = NULL;
 109         fields[0].in_check_value = NULL;
 110         fields[0].in_check_mask = NULL;
 111         fields[0].in_handler = NULL;
 112         fields[0].in_handler_priv = NULL;
 113
 114         fields[1].device = jtag_info->chain_pos;
 115         fields[1].num_bits = 32;
 116         fields[1].out_value = out_buf;
 117         fields[1].out_mask = NULL;
 118         fields[1].in_value = NULL;
 119         if (in)
 120         {
 121                 fields[1].in_handler = arm_jtag_buf_to_u32_flip;
 122                 fields[1].in_handler_priv = in;
 123         } else
 124         {
 125                 fields[1].in_handler = NULL;
 126                 fields[1].in_handler_priv = NULL;
 127         }
 128         fields[1].in_check_value = NULL;
 129         fields[1].in_check_mask = NULL;
 130
 131         jtag_add_dr_scan(2, fields, -1);
 132
 133         if (clock)
 134                 jtag_add_runtest(0, -1);
 135
 136 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 137         jtag_execute_queue();
 138
 139         if (in)
 140                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
 141         else
 142                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 143 #else
 144                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 145 #endif
 146
 147         return ERROR_OK;
 148 }
 149
 150 int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
 151 {
 152         /* fetch CP15 opcode */
 153         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 154         /* "DECODE" stage */
 155         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 156         /* "EXECUTE" stage (1) */
 157         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 158         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 159         /* "EXECUTE" stage (2) */
 160         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 161         /* "EXECUTE" stage (3), CDATA is read */
 162         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 163
 164         return ERROR_OK;
 165 }
 166
 167 int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
 168 {
 169         /* fetch CP15 opcode */
 170         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 171         /* "DECODE" stage */
 172         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 173         /* "EXECUTE" stage (1) */
 174         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 175         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 176         /* "EXECUTE" stage (2) */
 177         arm720t_scan_cp15(target, value, NULL, 0, 1);
 178         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 179
 180         return ERROR_OK;
 181 }
 182
 183 u32 arm720t_get_ttb(target_t *target)
 184 {
 185         u32 ttb = 0x0;
 186
 187         arm720t_read_cp15(target, 0xee120f10, &ttb);
 188         jtag_execute_queue();
 189
 190         ttb &= 0xffffc000;
 191
 192         return ttb;
 193 }
 194
 195 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 196 {
 197         u32 cp15_control;
 198
 199         /* read cp15 control register */
 200         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 201         jtag_execute_queue();
 202
 203         if (mmu)
 204                 cp15_control &= ~0x1U;
 205
 206         if (d_u_cache || i_cache)
 207                 cp15_control &= ~0x4U;
 208
 209         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 210 }
 211
 212 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 213 {
 214         u32 cp15_control;
 215
 216         /* read cp15 control register */
 217         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 218         jtag_execute_queue();
 219
 220         if (mmu)
 221                 cp15_control |= 0x1U;
 222
 223         if (d_u_cache || i_cache)
 224                 cp15_control |= 0x4U;
 225
 226         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 227 }
 228
 229 void arm720t_post_debug_entry(target_t *target)
 230 {
 231         armv4_5_common_t *armv4_5 = target->arch_info;
 232         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 233         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 234         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 235
 236         /* examine cp15 control reg */
 237         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 238         jtag_execute_queue();
 239         LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
 240
 241         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 242         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 243         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 244
 245         /* save i/d fault status and address register */
 246         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 247         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 248         jtag_execute_queue();
 249 }
 250
 251 void arm720t_pre_restore_context(target_t *target)
 252 {
 253         armv4_5_common_t *armv4_5 = target->arch_info;
 254         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 255         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 256         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 257
 258         /* restore i/d fault status and address register */
 259         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 260         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 261 }
 262
 263 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
 264 {
 265         armv4_5_common_t *armv4_5 = target->arch_info;
 266         arm7_9_common_t *arm7_9;
 267         arm7tdmi_common_t *arm7tdmi;
 268         arm720t_common_t *arm720t;
 269
 270         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 271         {
 272                 return -1;
 273         }
 274
 275         arm7_9 = armv4_5->arch_info;
 276         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 277         {
 278                 return -1;
 279         }
 280
 281         arm7tdmi = arm7_9->arch_info;
 282         if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
 283         {
 284                 return -1;
 285         }
 286
 287         arm720t = arm7tdmi->arch_info;
 288         if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
 289         {
 290                 return -1;
 291         }
 292
 293         *armv4_5_p = armv4_5;
 294         *arm7_9_p = arm7_9;
 295         *arm7tdmi_p = arm7tdmi;
 296         *arm720t_p = arm720t;
 297
 298         return ERROR_OK;
 299 }
 300
 301 int arm720t_arch_state(struct target_s *target)
 302 {
 303         armv4_5_common_t *armv4_5 = target->arch_info;
 304         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 305         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 306         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 307
 308         char *state[] =
 309         {
 310                 "disabled", "enabled"
 311         };
 312
 313         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 314         {
 315                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 316                 exit(-1);
 317         }
 318
 319         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 320                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 321                         "MMU: %s, Cache: %s",
 322                          armv4_5_state_strings[armv4_5->core_state],
 323                          target_debug_reason_strings[target->debug_reason],
 324                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 325                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 326                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 327                          state[arm720t->armv4_5_mmu.mmu_enabled],
 328                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 329
 330         return ERROR_OK;
 331 }
 332
 333 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 334 {
 335         int retval;
 336         armv4_5_common_t *armv4_5 = target->arch_info;
 337         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 338         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 339         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 340
 341         /* disable cache, but leave MMU enabled */
 342         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 343                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 344
 345         retval = arm7_9_read_memory(target, address, size, count, buffer);
 346
 347         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 348                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 349
 350         return retval;
 351 }
 352
 353 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 354 {
 355         int retval;
 356
 357         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 358                 return retval;
 359
 360         return retval;
 361 }
 362
 363 int arm720t_soft_reset_halt(struct target_s *target)
 364 {
 365         armv4_5_common_t *armv4_5 = target->arch_info;
 366         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 367         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 368         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 369         int i;
 370         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 371
 372         target_halt(target);
 373
 374         for (i=0; i<10; i++)
 375         {
 376                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 377                 {
 378                         embeddedice_read_reg(dbg_stat);
 379                         jtag_execute_queue();
 380                 } else
 381                 {
 382                         break;
 383                 }
 384                 /* do not eat all CPU, time out after 1 se*/
 385                 usleep(100*1000);
 386         }
 387         if (i==10)
 388         {
 389                 LOG_ERROR("Failed to halt CPU after 1 sec");
 390                 return ERROR_TARGET_TIMEOUT;
 391         }
 392
 393         target->state = TARGET_HALTED;
 394
 395         /* SVC, ARM state, IRQ and FIQ disabled */
 396         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 397         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 398         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 399
 400         /* start fetching from 0x0 */
 401         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 402         armv4_5->core_cache->reg_list[15].dirty = 1;
 403         armv4_5->core_cache->reg_list[15].valid = 1;
 404
 405         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 406         armv4_5->core_state = ARMV4_5_STATE_ARM;
 407
 408         arm720t_disable_mmu_caches(target, 1, 1, 1);
 409         arm720t->armv4_5_mmu.mmu_enabled = 0;
 410         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 411         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 412
 413         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 414
 415         return ERROR_OK;
 416 }
 417
 418 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 419 {
 420         arm7tdmi_init_target(cmd_ctx, target);
 421
 422         return ERROR_OK;
 423
 424 }
 425
 426 int arm720t_quit(void)
 427 {
 428
 429         return ERROR_OK;
 430 }
 431
 432 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chain_pos, char *variant)
 433 {
 434         arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
 435         arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
 436
 437         arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);
 438
 439         arm7tdmi->arch_info = arm720t;
 440         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 441
 442         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 443         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 444
 445         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 446         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 447         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 448         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 449         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 450         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 451         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 452         arm720t->armv4_5_mmu.mmu_enabled = 0;
 453
 454         return ERROR_OK;
 455 }
 456
 457 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 458 {
 459         int chain_pos;
 460         char *variant = NULL;
 461         arm720t_common_t *arm720t = malloc(sizeof(arm720t_common_t));
 462         memset(arm720t, 0, sizeof(*arm720t));
 463
 464         if (argc < 4)
 465         {
 466                 LOG_ERROR("'target arm720t' requires at least one additional argument");
 467                 exit(-1);
 468         }
 469
 470         chain_pos = strtoul(args[3], NULL, 0);
 471
 472         if (argc >= 5)
 473                 variant = args[4];
 474
 475         LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
 476
 477         arm720t_init_arch_info(target, arm720t, chain_pos, variant);
 478
 479         return ERROR_OK;
 480 }
 481
 482 int arm720t_register_commands(struct command_context_s *cmd_ctx)
 483 {
 484         int retval;
 485         command_t *arm720t_cmd;
 486
 487
 488         retval = arm7tdmi_register_commands(cmd_ctx);
 489
 490         arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
 491
 492         register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
 493         register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 494
 495         register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 496         register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 497         register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 498
 499         register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 500         register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 501         register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 502
 503         return ERROR_OK;
 504 }
 505
 506 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 507 {
 508         int retval;
 509         target_t *target = get_current_target(cmd_ctx);
 510         armv4_5_common_t *armv4_5;
 511         arm7_9_common_t *arm7_9;
 512         arm7tdmi_common_t *arm7tdmi;
 513         arm720t_common_t *arm720t;
 514         arm_jtag_t *jtag_info;
 515
 516         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 517         {
 518                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 519                 return ERROR_OK;
 520         }
 521
 522         jtag_info = &arm7_9->jtag_info;
 523
 524         if (target->state != TARGET_HALTED)
 525         {
 526                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 527                 return ERROR_OK;
 528         }
 529
 530         /* one or more argument, access a single register (write if second argument is given */
 531         if (argc >= 1)
 532         {
 533                 u32 opcode = strtoul(args[0], NULL, 0);
 534
 535                 if (argc == 1)
 536                 {
 537                         u32 value;
 538                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 539                         {
 540                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
 541                                 return ERROR_OK;
 542                         }
 543                         jtag_execute_queue();
 544
 545                         command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
 546                 }
 547                 else if (argc == 2)
 548                 {
 549                         u32 value = strtoul(args[1], NULL, 0);
 550                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 551                         {
 552                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
 553                                 return ERROR_OK;
 554                         }
 555                         command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
 556                 }
 557         }
 558
 559         return ERROR_OK;
 560 }
 561
 562 int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 563 {
 564         target_t *target = get_current_target(cmd_ctx);
 565         armv4_5_common_t *armv4_5;
 566         arm7_9_common_t *arm7_9;
 567         arm7tdmi_common_t *arm7tdmi;
 568         arm720t_common_t *arm720t;
 569         arm_jtag_t *jtag_info;
 570
 571         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 572         {
 573                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 574                 return ERROR_OK;
 575         }
 576
 577         jtag_info = &arm7_9->jtag_info;
 578
 579         if (target->state != TARGET_HALTED)
 580         {
 581                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 582                 return ERROR_OK;
 583         }
 584
 585         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 586 }
 587
 588 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 589 {
 590         target_t *target = get_current_target(cmd_ctx);
 591         armv4_5_common_t *armv4_5;
 592         arm7_9_common_t *arm7_9;
 593         arm7tdmi_common_t *arm7tdmi;
 594         arm720t_common_t *arm720t;
 595         arm_jtag_t *jtag_info;
 596
 597         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 598         {
 599                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 600                 return ERROR_OK;
 601         }
 602
 603         jtag_info = &arm7_9->jtag_info;
 604
 605         if (target->state != TARGET_HALTED)
 606         {
 607                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 608                 return ERROR_OK;
 609         }
 610
 611         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 612 }
 613
 614 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 615 {
 616         target_t *target = get_current_target(cmd_ctx);
 617         armv4_5_common_t *armv4_5;
 618         arm7_9_common_t *arm7_9;
 619         arm7tdmi_common_t *arm7tdmi;
 620         arm720t_common_t *arm720t;
 621         arm_jtag_t *jtag_info;
 622
 623         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 624         {
 625                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 626                 return ERROR_OK;
 627         }
 628
 629         jtag_info = &arm7_9->jtag_info;
 630
 631         if (target->state != TARGET_HALTED)
 632         {
 633                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 634                 return ERROR_OK;
 635         }
 636
 637         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 638 }
 639