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   1 /***************************************************************************\r
   2  *   Copyright (C) 2005 by Dominic Rath                                    *\r
   3  *   Dominic.Rath@gmx.de                                                   *\r
   4  *                                                                         *\r
   5  *   This program is free software; you can redistribute it and/or modify  *\r
   6  *   it under the terms of the GNU General Public License as published by  *\r
   7  *   the Free Software Foundation; either version 2 of the License, or     *\r
   8  *   (at your option) any later version.                                   *\r
   9  *                                                                         *\r
  10  *   This program is distributed in the hope that it will be useful,       *\r
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
  13  *   GNU General Public License for more details.                          *\r
  14  *                                                                         *\r
  15  *   You should have received a copy of the GNU General Public License     *\r
  16  *   along with this program; if not, write to the                         *\r
  17  *   Free Software Foundation, Inc.,                                       *\r
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
  19  ***************************************************************************/\r
  20 #ifdef HAVE_CONFIG_H\r
  21 #include "config.h"\r
  22 #endif\r
  23 \r
  24 #include "arm720t.h"\r
  25 #include "jtag.h"\r
  26 #include "log.h"\r
  27 \r
  28 #include <stdlib.h>\r
  29 #include <string.h>\r
  30 \r
  31 #if 0\r
  32 #define _DEBUG_INSTRUCTION_EXECUTION_\r
  33 #endif\r
  34 \r
  35 /* cli handling */\r
  36 int arm720t_register_commands(struct command_context_s *cmd_ctx);\r
  37 \r
  38 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  39 int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  40 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  41 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  42 \r
  43 /* forward declarations */\r
  44 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);\r
  45 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);\r
  46 int arm720t_quit();\r
  47 int arm720t_arch_state(struct target_s *target);\r
  48 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);\r
  49 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);\r
  50 int arm720t_soft_reset_halt(struct target_s *target);\r
  51 \r
  52 target_type_t arm720t_target =\r
  53 {\r
  54         .name = "arm720t",\r
  55 \r
  56         .poll = arm7_9_poll,\r
  57         .arch_state = arm720t_arch_state,\r
  58 \r
  59         .halt = arm7_9_halt,\r
  60         .resume = arm7_9_resume,\r
  61         .step = arm7_9_step,\r
  62 \r
  63         .assert_reset = arm7_9_assert_reset,\r
  64         .deassert_reset = arm7_9_deassert_reset,\r
  65         .soft_reset_halt = arm720t_soft_reset_halt,\r
  66         .prepare_reset_halt = arm7_9_prepare_reset_halt,\r
  67         \r
  68         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,\r
  69 \r
  70         .read_memory = arm720t_read_memory,\r
  71         .write_memory = arm720t_write_memory,\r
  72         .bulk_write_memory = arm7_9_bulk_write_memory,\r
  73         .checksum_memory = arm7_9_checksum_memory,\r
  74         \r
  75         .run_algorithm = armv4_5_run_algorithm,\r
  76 \r
  77         .add_breakpoint = arm7_9_add_breakpoint,\r
  78         .remove_breakpoint = arm7_9_remove_breakpoint,\r
  79         .add_watchpoint = arm7_9_add_watchpoint,\r
  80         .remove_watchpoint = arm7_9_remove_watchpoint,\r
  81 \r
  82         .register_commands = arm720t_register_commands,\r
  83         .target_command = arm720t_target_command,\r
  84         .init_target = arm720t_init_target,\r
  85         .quit = arm720t_quit\r
  86 };\r
  87 \r
  88 int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)\r
  89 {\r
  90         armv4_5_common_t *armv4_5 = target->arch_info;\r
  91         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
  92         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
  93         scan_field_t fields[2];\r
  94         u8 out_buf[4];\r
  95         u8 instruction_buf = instruction;\r
  96         \r
  97         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));\r
  98         \r
  99         jtag_add_end_state(TAP_PD);\r
 100         arm_jtag_scann(jtag_info, 0xf);\r
 101         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
 102                 \r
 103         fields[0].device = jtag_info->chain_pos;\r
 104         fields[0].num_bits = 1;\r
 105         fields[0].out_value = &instruction_buf;\r
 106         fields[0].out_mask = NULL;\r
 107         fields[0].in_value = NULL;\r
 108         fields[0].in_check_value = NULL;\r
 109         fields[0].in_check_mask = NULL;\r
 110         fields[0].in_handler = NULL;\r
 111         fields[0].in_handler_priv = NULL;\r
 112 \r
 113         fields[1].device = jtag_info->chain_pos;\r
 114         fields[1].num_bits = 32;\r
 115         fields[1].out_value = out_buf;\r
 116         fields[1].out_mask = NULL;\r
 117         fields[1].in_value = NULL;\r
 118         if (in)\r
 119         {\r
 120                 fields[1].in_handler = arm_jtag_buf_to_u32_flip;\r
 121                 fields[1].in_handler_priv = in;\r
 122         } else\r
 123         {\r
 124                 fields[1].in_handler = NULL;\r
 125                 fields[1].in_handler_priv = NULL;\r
 126         }\r
 127         fields[1].in_check_value = NULL;\r
 128         fields[1].in_check_mask = NULL;\r
 129         \r
 130         jtag_add_dr_scan(2, fields, -1);\r
 131 \r
 132         if (clock)\r
 133                 jtag_add_runtest(0, -1);\r
 134 \r
 135 #ifdef _DEBUG_INSTRUCTION_EXECUTION_\r
 136         jtag_execute_queue();\r
 137 \r
 138         if (in)\r
 139                 DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);\r
 140         else\r
 141                 DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);\r
 142 #else\r
 143                 DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);\r
 144 #endif\r
 145 \r
 146         return ERROR_OK;\r
 147 }\r
 148 \r
 149 int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)\r
 150 {\r
 151         /* fetch CP15 opcode */\r
 152         arm720t_scan_cp15(target, opcode, NULL, 1, 1);\r
 153         /* "DECODE" stage */\r
 154         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);\r
 155         /* "EXECUTE" stage (1) */\r
 156         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);\r
 157         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);\r
 158         /* "EXECUTE" stage (2) */\r
 159         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);\r
 160         /* "EXECUTE" stage (3), CDATA is read */\r
 161         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);\r
 162         \r
 163         return ERROR_OK;\r
 164 }\r
 165 \r
 166 int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)\r
 167 {\r
 168         /* fetch CP15 opcode */\r
 169         arm720t_scan_cp15(target, opcode, NULL, 1, 1);\r
 170         /* "DECODE" stage */\r
 171         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);\r
 172         /* "EXECUTE" stage (1) */\r
 173         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);\r
 174         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);\r
 175         /* "EXECUTE" stage (2) */\r
 176         arm720t_scan_cp15(target, value, NULL, 0, 1);\r
 177         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);\r
 178 \r
 179         return ERROR_OK;\r
 180 }\r
 181 \r
 182 u32 arm720t_get_ttb(target_t *target)\r
 183 {\r
 184         u32 ttb = 0x0;\r
 185 \r
 186         arm720t_read_cp15(target, 0xee120f10, &ttb);\r
 187         jtag_execute_queue();\r
 188         \r
 189         ttb &= 0xffffc000;\r
 190         \r
 191         return ttb;\r
 192 }\r
 193 \r
 194 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)\r
 195 {\r
 196         u32 cp15_control;\r
 197 \r
 198         /* read cp15 control register */\r
 199         arm720t_read_cp15(target, 0xee110f10, &cp15_control);\r
 200         jtag_execute_queue();\r
 201                 \r
 202         if (mmu)\r
 203                 cp15_control &= ~0x1U;\r
 204         \r
 205         if (d_u_cache || i_cache)\r
 206                 cp15_control &= ~0x4U;\r
 207 \r
 208         arm720t_write_cp15(target, 0xee010f10, cp15_control);\r
 209 }\r
 210 \r
 211 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)\r
 212 {\r
 213         u32 cp15_control;\r
 214 \r
 215         /* read cp15 control register */\r
 216         arm720t_read_cp15(target, 0xee110f10, &cp15_control);\r
 217         jtag_execute_queue();\r
 218                 \r
 219         if (mmu)\r
 220                 cp15_control |= 0x1U;\r
 221         \r
 222         if (d_u_cache || i_cache)\r
 223                 cp15_control |= 0x4U;\r
 224         \r
 225         arm720t_write_cp15(target, 0xee010f10, cp15_control);\r
 226 }\r
 227 \r
 228 void arm720t_post_debug_entry(target_t *target)\r
 229 {\r
 230         armv4_5_common_t *armv4_5 = target->arch_info;\r
 231         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 232         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;\r
 233         arm720t_common_t *arm720t = arm7tdmi->arch_info;\r
 234         \r
 235         /* examine cp15 control reg */\r
 236         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);\r
 237         jtag_execute_queue();\r
 238         DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);\r
 239 \r
 240         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;\r
 241         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;\r
 242         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;\r
 243 \r
 244         /* save i/d fault status and address register */\r
 245         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);\r
 246         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);\r
 247         jtag_execute_queue();\r
 248 }\r
 249 \r
 250 void arm720t_pre_restore_context(target_t *target)\r
 251 {\r
 252         armv4_5_common_t *armv4_5 = target->arch_info;\r
 253         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 254         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;\r
 255         arm720t_common_t *arm720t = arm7tdmi->arch_info;\r
 256         \r
 257         /* restore i/d fault status and address register */\r
 258         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);\r
 259         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);\r
 260 }\r
 261 \r
 262 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)\r
 263 {\r
 264         armv4_5_common_t *armv4_5 = target->arch_info;\r
 265         arm7_9_common_t *arm7_9;\r
 266         arm7tdmi_common_t *arm7tdmi;\r
 267         arm720t_common_t *arm720t;\r
 268         \r
 269         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)\r
 270         {\r
 271                 return -1;\r
 272         }\r
 273         \r
 274         arm7_9 = armv4_5->arch_info;\r
 275         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)\r
 276         {\r
 277                 return -1;\r
 278         }\r
 279         \r
 280         arm7tdmi = arm7_9->arch_info;\r
 281         if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)\r
 282         {\r
 283                 return -1;\r
 284         }\r
 285         \r
 286         arm720t = arm7tdmi->arch_info;\r
 287         if (arm720t->common_magic != ARM720T_COMMON_MAGIC)\r
 288         {\r
 289                 return -1;\r
 290         }\r
 291         \r
 292         *armv4_5_p = armv4_5;\r
 293         *arm7_9_p = arm7_9;\r
 294         *arm7tdmi_p = arm7tdmi;\r
 295         *arm720t_p = arm720t;\r
 296         \r
 297         return ERROR_OK;\r
 298 }\r
 299 \r
 300 int arm720t_arch_state(struct target_s *target)\r
 301 {\r
 302         armv4_5_common_t *armv4_5 = target->arch_info;\r
 303         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 304         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;\r
 305         arm720t_common_t *arm720t = arm7tdmi->arch_info;\r
 306         \r
 307         char *state[] = \r
 308         {\r
 309                 "disabled", "enabled"\r
 310         };\r
 311         \r
 312         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)\r
 313         {\r
 314                 ERROR("BUG: called for a non-ARMv4/5 target");\r
 315                 exit(-1);\r
 316         }\r
 317         \r
 318         USER("target halted in %s state due to %s, current mode: %s\n"\r
 319                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"\r
 320                         "MMU: %s, Cache: %s",\r
 321                          armv4_5_state_strings[armv4_5->core_state],\r
 322                          target_debug_reason_strings[target->debug_reason],\r
 323                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],\r
 324                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),\r
 325                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),\r
 326                          state[arm720t->armv4_5_mmu.mmu_enabled],\r
 327                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);\r
 328         \r
 329         return ERROR_OK;\r
 330 }\r
 331 \r
 332 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)\r
 333 {\r
 334         int retval;\r
 335         armv4_5_common_t *armv4_5 = target->arch_info;\r
 336         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 337         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;\r
 338         arm720t_common_t *arm720t = arm7tdmi->arch_info;\r
 339         \r
 340         /* disable cache, but leave MMU enabled */\r
 341         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)\r
 342                 arm720t_disable_mmu_caches(target, 0, 1, 0);\r
 343         \r
 344         retval = arm7_9_read_memory(target, address, size, count, buffer);\r
 345         \r
 346         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)\r
 347                 arm720t_enable_mmu_caches(target, 0, 1, 0);\r
 348         \r
 349         return retval;\r
 350 }\r
 351 \r
 352 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)\r
 353 {\r
 354         int retval;\r
 355         \r
 356         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)\r
 357                 return retval;\r
 358 \r
 359         return retval;\r
 360 }\r
 361 \r
 362 int arm720t_soft_reset_halt(struct target_s *target)\r
 363 {\r
 364         armv4_5_common_t *armv4_5 = target->arch_info;\r
 365         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 366         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;\r
 367         arm720t_common_t *arm720t = arm7tdmi->arch_info;\r
 368         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];\r
 369         \r
 370         if (target->state == TARGET_RUNNING)\r
 371         {\r
 372                 target->type->halt(target);\r
 373         }\r
 374         \r
 375         while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)\r
 376         {\r
 377                 embeddedice_read_reg(dbg_stat);\r
 378                 jtag_execute_queue();\r
 379         }\r
 380         \r
 381         target->state = TARGET_HALTED;\r
 382         \r
 383         /* SVC, ARM state, IRQ and FIQ disabled */\r
 384         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);\r
 385         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;\r
 386         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;\r
 387         \r
 388         /* start fetching from 0x0 */\r
 389         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);\r
 390         armv4_5->core_cache->reg_list[15].dirty = 1;\r
 391         armv4_5->core_cache->reg_list[15].valid = 1;\r
 392         \r
 393         armv4_5->core_mode = ARMV4_5_MODE_SVC;\r
 394         armv4_5->core_state = ARMV4_5_STATE_ARM;\r
 395         \r
 396         arm720t_disable_mmu_caches(target, 1, 1, 1);\r
 397         arm720t->armv4_5_mmu.mmu_enabled = 0;\r
 398         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;\r
 399         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;\r
 400 \r
 401         target_call_event_callbacks(target, TARGET_EVENT_HALTED);\r
 402         \r
 403         return ERROR_OK;\r
 404 }\r
 405 \r
 406 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)\r
 407 {\r
 408         arm7tdmi_init_target(cmd_ctx, target);\r
 409                 \r
 410         return ERROR_OK;\r
 411         \r
 412 }\r
 413 \r
 414 int arm720t_quit()\r
 415 {\r
 416         \r
 417         return ERROR_OK;\r
 418 }\r
 419 \r
 420 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chain_pos, char *variant)\r
 421 {\r
 422         arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;\r
 423         arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;\r
 424         \r
 425         arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);\r
 426 \r
 427         arm7tdmi->arch_info = arm720t;\r
 428         arm720t->common_magic = ARM720T_COMMON_MAGIC;\r
 429         \r
 430         arm7_9->post_debug_entry = arm720t_post_debug_entry;\r
 431         arm7_9->pre_restore_context = arm720t_pre_restore_context;\r
 432         \r
 433         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;\r
 434         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;\r
 435         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;\r
 436         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;\r
 437         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;\r
 438         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;\r
 439         arm720t->armv4_5_mmu.has_tiny_pages = 0;\r
 440         arm720t->armv4_5_mmu.mmu_enabled = 0;\r
 441         \r
 442         return ERROR_OK;\r
 443 }\r
 444 \r
 445 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)\r
 446 {\r
 447         int chain_pos;\r
 448         char *variant = NULL;\r
 449         arm720t_common_t *arm720t = malloc(sizeof(arm720t_common_t));\r
 450         \r
 451         if (argc < 4)\r
 452         {\r
 453                 ERROR("'target arm720t' requires at least one additional argument");\r
 454                 exit(-1);\r
 455         }\r
 456         \r
 457         chain_pos = strtoul(args[3], NULL, 0);\r
 458         \r
 459         if (argc >= 5)\r
 460                 variant = args[4];\r
 461         \r
 462         DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);\r
 463         \r
 464         arm720t_init_arch_info(target, arm720t, chain_pos, variant);\r
 465 \r
 466         return ERROR_OK;\r
 467 }\r
 468 \r
 469 int arm720t_register_commands(struct command_context_s *cmd_ctx)\r
 470 {\r
 471         int retval;\r
 472         command_t *arm720t_cmd;\r
 473         \r
 474                 \r
 475         retval = arm7tdmi_register_commands(cmd_ctx);\r
 476         \r
 477         arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");\r
 478 \r
 479         register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");\r
 480         register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");\r
 481 \r
 482         register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");\r
 483         register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");\r
 484         register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");\r
 485 \r
 486         register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");\r
 487         register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");\r
 488         register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");\r
 489         \r
 490         return ERROR_OK;\r
 491 }\r
 492 \r
 493 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
 494 {\r
 495         int retval;\r
 496         target_t *target = get_current_target(cmd_ctx);\r
 497         armv4_5_common_t *armv4_5;\r
 498         arm7_9_common_t *arm7_9;\r
 499         arm7tdmi_common_t *arm7tdmi;\r
 500         arm720t_common_t *arm720t;\r
 501         arm_jtag_t *jtag_info;\r
 502 \r
 503         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)\r
 504         {\r
 505                 command_print(cmd_ctx, "current target isn't an ARM720t target");\r
 506                 return ERROR_OK;\r
 507         }\r
 508         \r
 509         jtag_info = &arm7_9->jtag_info;\r
 510         \r
 511         if (target->state != TARGET_HALTED)\r
 512         {\r
 513                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
 514                 return ERROR_OK;\r
 515         }\r
 516 \r
 517         /* one or more argument, access a single register (write if second argument is given */\r
 518         if (argc >= 1)\r
 519         {\r
 520                 u32 opcode = strtoul(args[0], NULL, 0);\r
 521 \r
 522                 if (argc == 1)\r
 523                 {\r
 524                         u32 value;\r
 525                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)\r
 526                         {\r
 527                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);\r
 528                                 return ERROR_OK;\r
 529                         }\r
 530                         jtag_execute_queue();\r
 531                         \r
 532                         command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);\r
 533                 }\r
 534                 else if (argc == 2)\r
 535                 {\r
 536                         u32 value = strtoul(args[1], NULL, 0);\r
 537                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)\r
 538                         {\r
 539                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);\r
 540                                 return ERROR_OK;\r
 541                         }\r
 542                         command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);\r
 543                 }\r
 544         }\r
 545 \r
 546         return ERROR_OK;\r
 547 }\r
 548 \r
 549 int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)\r
 550 {       \r
 551         target_t *target = get_current_target(cmd_ctx);\r
 552         armv4_5_common_t *armv4_5;\r
 553         arm7_9_common_t *arm7_9;\r
 554         arm7tdmi_common_t *arm7tdmi;\r
 555         arm720t_common_t *arm720t;\r
 556         arm_jtag_t *jtag_info;\r
 557 \r
 558         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)\r
 559         {\r
 560                 command_print(cmd_ctx, "current target isn't an ARM720t target");\r
 561                 return ERROR_OK;\r
 562         }\r
 563         \r
 564         jtag_info = &arm7_9->jtag_info;\r
 565         \r
 566         if (target->state != TARGET_HALTED)\r
 567         {\r
 568                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
 569                 return ERROR_OK;\r
 570         }\r
 571                 \r
 572         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);\r
 573 }\r
 574 \r
 575 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)\r
 576 {       \r
 577         target_t *target = get_current_target(cmd_ctx);\r
 578         armv4_5_common_t *armv4_5;\r
 579         arm7_9_common_t *arm7_9;\r
 580         arm7tdmi_common_t *arm7tdmi;\r
 581         arm720t_common_t *arm720t;\r
 582         arm_jtag_t *jtag_info;\r
 583 \r
 584         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)\r
 585         {\r
 586                 command_print(cmd_ctx, "current target isn't an ARM720t target");\r
 587                 return ERROR_OK;\r
 588         }\r
 589         \r
 590         jtag_info = &arm7_9->jtag_info;\r
 591         \r
 592         if (target->state != TARGET_HALTED)\r
 593         {\r
 594                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
 595                 return ERROR_OK;\r
 596         }\r
 597         \r
 598         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);\r
 599 }\r
 600 \r
 601 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)\r
 602 {       \r
 603         target_t *target = get_current_target(cmd_ctx);\r
 604         armv4_5_common_t *armv4_5;\r
 605         arm7_9_common_t *arm7_9;\r
 606         arm7tdmi_common_t *arm7tdmi;\r
 607         arm720t_common_t *arm720t;\r
 608         arm_jtag_t *jtag_info;\r
 609 \r
 610         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)\r
 611         {\r
 612                 command_print(cmd_ctx, "current target isn't an ARM720t target");\r
 613                 return ERROR_OK;\r
 614         }\r
 615         \r
 616         jtag_info = &arm7_9->jtag_info;\r
 617         \r
 618         if (target->state != TARGET_HALTED)\r
 619         {\r
 620                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
 621                 return ERROR_OK;\r
 622         }\r
 623         \r
 624         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);\r
 625 }\r
 626 \r