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1 /***************************************************************************
2  *   Copyright (C) 2008 digenius technology GmbH.                          *
3  *                                                                         *
4  *   This program is free software; you can redistribute it and/or modify  *
5  *   it under the terms of the GNU General Public License as published by  *
6  *   the Free Software Foundation; either version 2 of the License, or     *
7  *   (at your option) any later version.                                   *
8  *                                                                         *
9  *   This program is distributed in the hope that it will be useful,       *
10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
12  *   GNU General Public License for more details.                          *
13  *                                                                         *
14  *   You should have received a copy of the GNU General Public License     *
15  *   along with this program; if not, write to the                         *
16  *   Free Software Foundation, Inc.,                                       *
17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
18  ***************************************************************************/
19
20 #ifndef ARM11_H
21 #define ARM11_H
22
23 #include "target.h"
24 #include "register.h"
25 #include "embeddedice.h"
26 #include "arm_jtag.h"
27
28
29 #define asizeof(x)      (sizeof(x) / sizeof((x)[0]))
30
31 #define NEW(type, variable, items) \
32     type * variable = malloc(sizeof(type) * items)
33
34
35 #define ARM11_REGCACHE_MODEREGS         0
36 #define ARM11_REGCACHE_FREGS            0
37
38 #define ARM11_REGCACHE_COUNT            (20 +                                   \
39                                          23 * ARM11_REGCACHE_MODEREGS +         \
40                                           9 * ARM11_REGCACHE_FREGS)
41
42
43 typedef struct arm11_register_history_s
44 {
45     u32     value;
46     u8      valid;
47 }arm11_register_history_t;
48
49 enum arm11_debug_version
50 {
51     ARM11_DEBUG_V6      = 0x01,
52     ARM11_DEBUG_V61     = 0x02,
53     ARM11_DEBUG_V7      = 0x03,
54     ARM11_DEBUG_V7_CP14 = 0x04,
55 };
56
57 typedef struct arm11_common_s
58 {
59     target_t *  target;
60
61     arm_jtag_t  jtag_info;
62
63     /** \name Processor type detection */
64     /*@{*/
65
66     u32         device_id;          /**< IDCODE readout                         */
67     u32         didr;               /**< DIDR readout (debug capabilities)      */
68     u8          implementor;        /**< DIDR Implementor readout               */
69
70     size_t      brp;                /**< Number of Breakpoint Register Pairs from DIDR  */
71     size_t      wrp;                /**< Number of Watchpoint Register Pairs from DIDR  */
72
73     enum arm11_debug_version
74                 debug_version;      /**< ARM debug architecture from DIDR       */
75     /*@}*/
76
77
78     u32         last_dscr;          /**< Last retrieved DSCR value;
79                                      *   Can be used to detect changes          */
80
81     u8          trst_active;
82     u8          halt_requested;
83
84     /** \name Shadow registers to save processor state */
85     /*@{*/
86
87     reg_t *     reg_list;                               /**< target register list */
88     u32         reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
89
90     /*@}*/
91
92     arm11_register_history_t
93                 reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
94
95
96     size_t      free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
97     size_t      free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
98
99 } arm11_common_t;
100
101
102 /**
103  * ARM11 DBGTAP instructions 
104  * 
105  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
106  */
107 enum arm11_instructions
108 {
109     ARM11_EXTEST    = 0x00,
110     ARM11_SCAN_N    = 0x02,
111     ARM11_RESTART   = 0x04,
112     ARM11_HALT      = 0x08,
113     ARM11_INTEST    = 0x0C,
114     ARM11_ITRSEL    = 0x1D,
115     ARM11_IDCODE    = 0x1E,
116     ARM11_BYPASS    = 0x1F,
117 };
118
119 enum arm11_dscr
120 {
121     ARM11_DSCR_CORE_HALTED                              = 1 << 0,
122     ARM11_DSCR_CORE_RESTARTED                           = 1 << 1,
123
124     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK               = 0x0F << 2,
125     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT               = 0x00 << 2,
126     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT         = 0x01 << 2,
127     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT         = 0x02 << 2,
128     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION   = 0x03 << 2,
129     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ             = 0x04 << 2,
130     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH       = 0x05 << 2,
131
132     ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                = 1 << 6,
133     ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT              = 1 << 7,
134     ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE           = 1 << 13,
135     ARM11_DSCR_MODE_SELECT                              = 1 << 14,
136     ARM11_DSCR_WDTR_FULL                                = 1 << 29,
137     ARM11_DSCR_RDTR_FULL                                = 1 << 30,
138 };
139
140 enum arm11_cpsr
141 {
142     ARM11_CPSR_T                                = 1 << 5,
143     ARM11_CPSR_J                                = 1 << 24,
144 };
145
146 enum arm11_sc7
147 {
148     ARM11_SC7_NULL                              = 0,
149     ARM11_SC7_VCR                               = 7,
150     ARM11_SC7_PC                                = 8,
151     ARM11_SC7_BVR0                              = 64,
152     ARM11_SC7_BCR0                              = 80,
153     ARM11_SC7_WVR0                              = 96,
154     ARM11_SC7_WCR0                              = 112,
155 };
156
157
158
159 typedef struct arm11_reg_state_s
160 {
161     u32                         def_index;
162     target_t *                  target;
163 } arm11_reg_state_t;
164
165
166
167
168 /* poll current target status */
169 int arm11_poll(struct target_s *target);
170 /* architecture specific status reply */
171 int arm11_arch_state(struct target_s *target);
172
173 /* target request support */
174 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
175
176 /* target execution control */
177 int arm11_halt(struct target_s *target);
178 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
179 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
180
181 /* target reset control */
182 int arm11_assert_reset(struct target_s *target);
183 int arm11_deassert_reset(struct target_s *target);
184 int arm11_soft_reset_halt(struct target_s *target);
185 int arm11_prepare_reset_halt(struct target_s *target);
186
187 /* target register access for gdb */
188 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
189
190 /* target memory access 
191 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
192 * count: number of items of <size>
193 */
194 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
195 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
196
197 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
198 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
199
200 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
201
202 /* target break-/watchpoint control 
203 * rw: 0 = write, 1 = read, 2 = access
204 */
205 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
206 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
207 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
208 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
209
210 /* target algorithm support */
211 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
212
213 int arm11_register_commands(struct command_context_s *cmd_ctx);
214 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
215 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
216 int arm11_quit(void);
217
218
219 /* helpers */
220 void arm11_build_reg_cache(target_t *target);
221
222 void arm11_record_register_history(arm11_common_t * arm11);
223 void arm11_dump_reg_changes(arm11_common_t * arm11);
224
225
226 /* internals */
227
228 void arm11_setup_field          (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
229 void arm11_add_IR               (arm11_common_t * arm11, u8 instr, enum tap_state state);
230 void arm11_add_debug_SCAN_N     (arm11_common_t * arm11, u8 chain, enum tap_state state);
231 void arm11_add_debug_INST       (arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state);
232 u32  arm11_read_DSCR            (arm11_common_t * arm11);
233 void arm11_write_DSCR           (arm11_common_t * arm11, u32 dscr);
234
235 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
236
237 void arm11_run_instr_data_prepare               (arm11_common_t * arm11);
238 void arm11_run_instr_data_finish                (arm11_common_t * arm11);
239 void arm11_run_instr_no_data                    (arm11_common_t * arm11, u32 * opcode, size_t count);
240 void arm11_run_instr_no_data1                   (arm11_common_t * arm11, u32 opcode);
241 void arm11_run_instr_data_to_core               (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
242 void arm11_run_instr_data_to_core_noack         (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
243 void arm11_run_instr_data_to_core1              (arm11_common_t * arm11, u32 opcode, u32 data);
244 void arm11_run_instr_data_from_core             (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
245 void arm11_run_instr_data_from_core_via_r0      (arm11_common_t * arm11, u32 opcode, u32 * data);
246 void arm11_run_instr_data_to_core_via_r0        (arm11_common_t * arm11, u32 opcode, u32 data);
247
248 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
249 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
250
251
252 /** Used to make a list of read/write commands for scan chain 7
253  *
254  *  Use with arm11_sc7_run()
255  */
256 typedef struct arm11_sc7_action_s
257 {
258     int    write;                               /**< Access mode: true for write, false for read.       */
259     u8      address;                            /**< Register address mode. Use enum #arm11_sc7         */
260     u32     value;                              /**< If write then set this to value to be written.
261                                                      In read mode this receives the read value when the
262                                                      function returns.                                  */
263 } arm11_sc7_action_t;
264
265 void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
266
267 /* Mid-level helper functions */
268 void arm11_sc7_clear_vbw(arm11_common_t * arm11);
269 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
270
271 void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
272
273
274
275 #endif /* ARM11_H */