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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 #ifndef ARM11_H
  24 #define ARM11_H
  25
  26 #include "armv4_5.h"
  27 #include "arm_dpm.h"
  28
  29 /* TEMPORARY -- till we switch to the shared infrastructure */
  30 #define ARM11_REGCACHE_COUNT            20
  31
  32 #define ARM11_TAP_DEFAULT                       TAP_INVALID
  33
  34 #define CHECK_RETVAL(action)                    \
  35         do {                                    \
  36                 int __retval = (action);        \
  37                 if (__retval != ERROR_OK) {     \
  38                         LOG_DEBUG("error while calling \"%s\"", \
  39                                 # action );     \
  40                         return __retval;        \
  41                 }                               \
  42         } while (0)
  43
  44 struct arm11_register_history
  45 {
  46         uint32_t                value;
  47         uint8_t         valid;
  48 };
  49
  50 enum arm11_debug_version
  51 {
  52         ARM11_DEBUG_V6                  = 0x01,
  53         ARM11_DEBUG_V61                 = 0x02,
  54         ARM11_DEBUG_V7                  = 0x03,
  55         ARM11_DEBUG_V7_CP14             = 0x04,
  56 };
  57
  58 struct arm11_common
  59 {
  60         struct arm      arm;
  61         struct target * target;         /**< Reference back to the owner */
  62
  63         /** Debug module state. */
  64         struct arm_dpm dpm;
  65
  66         /** \name Processor type detection */
  67         /*@{*/
  68
  69         size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
  70         size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
  71
  72         /*@}*/
  73
  74         uint32_t                last_dscr;              /**< Last retrieved DSCR value;
  75                                                              Use only for debug message generation              */
  76
  77         bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
  78
  79         /** \name Shadow registers to save processor state */
  80         /*@{*/
  81
  82         struct reg *    reg_list;                                                       /**< target register list */
  83         uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
  84
  85         /*@}*/
  86
  87         struct arm11_register_history
  88                 reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
  89
  90         size_t  free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
  91         size_t  free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
  92
  93         // GA
  94         struct reg_cache *core_cache;
  95
  96         struct arm_jtag jtag_info;
  97 };
  98
  99 static inline struct arm11_common *target_to_arm11(struct target *target)
 100 {
 101         return container_of(target->arch_info, struct arm11_common,
 102                         arm);
 103 }
 104
 105 /**
 106  * ARM11 DBGTAP instructions
 107  *
 108  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
 109  */
 110 enum arm11_instructions
 111 {
 112         ARM11_EXTEST    = 0x00,
 113         ARM11_SCAN_N    = 0x02,
 114         ARM11_RESTART   = 0x04,
 115         ARM11_HALT          = 0x08,
 116         ARM11_INTEST    = 0x0C,
 117         ARM11_ITRSEL    = 0x1D,
 118         ARM11_IDCODE    = 0x1E,
 119         ARM11_BYPASS    = 0x1F,
 120 };
 121
 122 enum arm11_dscr
 123 {
 124         ARM11_DSCR_CORE_HALTED                                                                  = 1 << 0,
 125         ARM11_DSCR_CORE_RESTARTED                                                               = 1 << 1,
 126
 127         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK                                   = 0x0F << 2,
 128         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT                                   = 0x00 << 2,
 129         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT                             = 0x01 << 2,
 130         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT                             = 0x02 << 2,
 131         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION               = 0x03 << 2,
 132         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ                                 = 0x04 << 2,
 133         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH                   = 0x05 << 2,
 134
 135         ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                                    = 1 << 6,
 136         ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT                                  = 1 << 7,
 137         ARM11_DSCR_INTERRUPTS_DISABLE                                                   = 1 << 11,
 138         ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE                               = 1 << 13,
 139         ARM11_DSCR_MODE_SELECT                                                                  = 1 << 14,
 140         ARM11_DSCR_WDTR_FULL                                                                    = 1 << 29,
 141         ARM11_DSCR_RDTR_FULL                                                                    = 1 << 30,
 142 };
 143
 144 enum arm11_cpsr
 145 {
 146         ARM11_CPSR_T                            = 1 << 5,
 147         ARM11_CPSR_J                            = 1 << 24,
 148 };
 149
 150 enum arm11_sc7
 151 {
 152         ARM11_SC7_NULL                          = 0,
 153         ARM11_SC7_VCR                           = 7,
 154         ARM11_SC7_PC                            = 8,
 155         ARM11_SC7_BVR0                          = 64,
 156         ARM11_SC7_BCR0                          = 80,
 157         ARM11_SC7_WVR0                          = 96,
 158         ARM11_SC7_WCR0                          = 112,
 159 };
 160
 161 struct arm11_reg_state
 162 {
 163         uint32_t                                def_index;
 164         struct target *                 target;
 165 };
 166
 167 #endif /* ARM11_H */