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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *                                                                         *
   4  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   5  *                                                                         *
   6  *   This program is free software; you can redistribute it and/or modify  *
   7  *   it under the terms of the GNU General Public License as published by  *
   8  *   the Free Software Foundation; either version 2 of the License, or     *
   9  *   (at your option) any later version.                                   *
  10  *                                                                         *
  11  *   This program is distributed in the hope that it will be useful,       *
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  14  *   GNU General Public License for more details.                          *
  15  *                                                                         *
  16  *   You should have received a copy of the GNU General Public License     *
  17  *   along with this program; if not, write to the                         *
  18  *   Free Software Foundation, Inc.,                                       *
  19  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  20  ***************************************************************************/
  21
  22 #ifndef ARM11_H
  23 #define ARM11_H
  24
  25 #include "target.h"
  26 #include "register.h"
  27 #include "embeddedice.h"
  28 #include "arm_jtag.h"
  29 #include <stdbool.h>
  30
  31 #define asizeof(x)      (sizeof(x) / sizeof((x)[0]))
  32
  33 #define NEW(type, variable, items)                      \
  34         type * variable = calloc(1, sizeof(type) * items)
  35
  36 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
  37
  38 #ifndef __MSVCRT__
  39 #define ZU              "%zu"
  40 #else
  41 #define ZU              "%Iu"
  42 #endif
  43
  44 #define ARM11_REGCACHE_MODEREGS         0
  45 #define ARM11_REGCACHE_FREGS            0
  46
  47 #define ARM11_REGCACHE_COUNT            (20 +                                   \
  48                                          23 * ARM11_REGCACHE_MODEREGS +         \
  49                                           9 * ARM11_REGCACHE_FREGS)
  50
  51 typedef struct arm11_register_history_s
  52 {
  53         u32             value;
  54         u8              valid;
  55 }arm11_register_history_t;
  56
  57 enum arm11_debug_version
  58 {
  59         ARM11_DEBUG_V6  = 0x01,
  60         ARM11_DEBUG_V61 = 0x02,
  61         ARM11_DEBUG_V7  = 0x03,
  62         ARM11_DEBUG_V7_CP14     = 0x04,
  63 };
  64
  65 typedef struct arm11_common_s
  66 {
  67         target_t *      target;
  68
  69         arm_jtag_t      jtag_info;
  70
  71         /** \name Processor type detection */
  72         /*@{*/
  73
  74         u32             device_id;              /**< IDCODE readout                             */
  75         u32             didr;                   /**< DIDR readout (debug capabilities)  */
  76         u8              implementor;    /**< DIDR Implementor readout           */
  77
  78         size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
  79         size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
  80
  81         enum arm11_debug_version
  82                 debug_version;          /**< ARM debug architecture from DIDR   */
  83         /*@}*/
  84
  85         u32             last_dscr;              /**< Last retrieved DSCR value;
  86                                                          * Can be used to detect changes                */
  87
  88         bool    trst_active;
  89         bool    halt_requested;
  90         bool    simulate_reset_on_next_halt;
  91
  92         /** \name Shadow registers to save processor state */
  93         /*@{*/
  94
  95         reg_t * reg_list;                                                       /**< target register list */
  96         u32             reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
  97
  98         /*@}*/
  99
 100         arm11_register_history_t
 101                 reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
 102
 103         size_t  free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
 104         size_t  free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
 105
 106         // GA
 107         reg_cache_t *core_cache;
 108 } arm11_common_t;
 109
 110
 111 /**
 112  * ARM11 DBGTAP instructions
 113  *
 114  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
 115  */
 116 enum arm11_instructions
 117 {
 118         ARM11_EXTEST    = 0x00,
 119         ARM11_SCAN_N    = 0x02,
 120         ARM11_RESTART   = 0x04,
 121         ARM11_HALT          = 0x08,
 122         ARM11_INTEST    = 0x0C,
 123         ARM11_ITRSEL    = 0x1D,
 124         ARM11_IDCODE    = 0x1E,
 125         ARM11_BYPASS    = 0x1F,
 126 };
 127
 128 enum arm11_dscr
 129 {
 130         ARM11_DSCR_CORE_HALTED                          = 1 << 0,
 131         ARM11_DSCR_CORE_RESTARTED                               = 1 << 1,
 132
 133         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK           = 0x0F << 2,
 134         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT           = 0x00 << 2,
 135         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT             = 0x01 << 2,
 136         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT             = 0x02 << 2,
 137         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION       = 0x03 << 2,
 138         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ         = 0x04 << 2,
 139         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH   = 0x05 << 2,
 140
 141         ARM11_DSCR_STICKY_PRECISE_DATA_ABORT            = 1 << 6,
 142         ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT          = 1 << 7,
 143         ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE               = 1 << 13,
 144         ARM11_DSCR_MODE_SELECT                          = 1 << 14,
 145         ARM11_DSCR_WDTR_FULL                            = 1 << 29,
 146         ARM11_DSCR_RDTR_FULL                            = 1 << 30,
 147 };
 148
 149 enum arm11_cpsr
 150 {
 151         ARM11_CPSR_T                            = 1 << 5,
 152         ARM11_CPSR_J                            = 1 << 24,
 153 };
 154
 155 enum arm11_sc7
 156 {
 157         ARM11_SC7_NULL                          = 0,
 158         ARM11_SC7_VCR                           = 7,
 159         ARM11_SC7_PC                            = 8,
 160         ARM11_SC7_BVR0                          = 64,
 161         ARM11_SC7_BCR0                          = 80,
 162         ARM11_SC7_WVR0                          = 96,
 163         ARM11_SC7_WCR0                          = 112,
 164 };
 165
 166 typedef struct arm11_reg_state_s
 167 {
 168         u32                             def_index;
 169         target_t *                      target;
 170 } arm11_reg_state_t;
 171
 172 /* poll current target status */
 173 int arm11_poll(struct target_s *target);
 174 /* architecture specific status reply */
 175 int arm11_arch_state(struct target_s *target);
 176
 177 /* target request support */
 178 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
 179
 180 /* target execution control */
 181 int arm11_halt(struct target_s *target);
 182 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
 183 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
 184 int arm11_examine(struct target_s *target);
 185
 186 /* target reset control */
 187 int arm11_assert_reset(struct target_s *target);
 188 int arm11_deassert_reset(struct target_s *target);
 189 int arm11_soft_reset_halt(struct target_s *target);
 190
 191 /* target register access for gdb */
 192 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
 193
 194 /* target memory access
 195 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 196 * count: number of items of <size>
 197 */
 198 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 199 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 200
 201 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
 202 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
 203
 204 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
 205
 206 /* target break-/watchpoint control
 207 * rw: 0 = write, 1 = read, 2 = access
 208 */
 209 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 210 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 211 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 212 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 213
 214 /* target algorithm support */
 215 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
 216
 217 int arm11_register_commands(struct command_context_s *cmd_ctx);
 218 int arm11_target_create(struct target_s *target, Jim_Interp *interp);
 219 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 220 int arm11_quit(void);
 221
 222 /* helpers */
 223 void arm11_build_reg_cache(target_t *target);
 224 int arm11_set_reg(reg_t *reg, u8 *buf);
 225 int arm11_get_reg(reg_t *reg);
 226
 227 void arm11_record_register_history(arm11_common_t * arm11);
 228 void arm11_dump_reg_changes(arm11_common_t * arm11);
 229
 230 /* internals */
 231
 232 void arm11_setup_field          (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
 233 void arm11_add_IR               (arm11_common_t * arm11, u8 instr, enum tap_state state);
 234 void arm11_add_debug_SCAN_N     (arm11_common_t * arm11, u8 chain, enum tap_state state);
 235 void arm11_add_debug_INST       (arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state);
 236 u32  arm11_read_DSCR            (arm11_common_t * arm11);
 237 void arm11_write_DSCR           (arm11_common_t * arm11, u32 dscr);
 238
 239 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
 240
 241 void arm11_run_instr_data_prepare               (arm11_common_t * arm11);
 242 void arm11_run_instr_data_finish                (arm11_common_t * arm11);
 243 void arm11_run_instr_no_data                    (arm11_common_t * arm11, u32 * opcode, size_t count);
 244 void arm11_run_instr_no_data1                   (arm11_common_t * arm11, u32 opcode);
 245 void arm11_run_instr_data_to_core               (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
 246 void arm11_run_instr_data_to_core_noack         (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
 247 void arm11_run_instr_data_to_core1              (arm11_common_t * arm11, u32 opcode, u32 data);
 248 void arm11_run_instr_data_from_core             (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
 249 void arm11_run_instr_data_from_core_via_r0      (arm11_common_t * arm11, u32 opcode, u32 * data);
 250 void arm11_run_instr_data_to_core_via_r0        (arm11_common_t * arm11, u32 opcode, u32 data);
 251
 252 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
 253 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
 254
 255 /** Used to make a list of read/write commands for scan chain 7
 256  *
 257  *  Use with arm11_sc7_run()
 258  */
 259 typedef struct arm11_sc7_action_s
 260 {
 261         bool    write;                          /**< Access mode: true for write, false for read.       */
 262         u8              address;                                /**< Register address mode. Use enum #arm11_sc7         */
 263         u32             value;                          /**< If write then set this to value to be written.
 264                                                                 In read mode this receives the read value when the
 265                                                                 function returns.                                       */
 266 } arm11_sc7_action_t;
 267
 268 void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
 269
 270 /* Mid-level helper functions */
 271 void arm11_sc7_clear_vbw(arm11_common_t * arm11);
 272 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
 273
 274 void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
 275
 276 #endif /* ARM11_H */