git.gag.com Git - fw/openocd/blob - src/target/arm11.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 #ifndef ARM11_H
  24 #define ARM11_H
  25
  26 #include "armv4_5.h"
  27
  28 /* TEMPORARY -- till we switch to the shared infrastructure */
  29 #define ARM11_REGCACHE_COUNT            20
  30
  31 #define ARM11_TAP_DEFAULT                       TAP_INVALID
  32
  33 #define CHECK_RETVAL(action)                    \
  34         do {                                    \
  35                 int __retval = (action);        \
  36                 if (__retval != ERROR_OK) {     \
  37                         LOG_DEBUG("error while calling \"%s\"", \
  38                                 # action );     \
  39                         return __retval;        \
  40                 }                               \
  41         } while (0)
  42
  43 struct arm11_register_history
  44 {
  45         uint32_t                value;
  46         uint8_t         valid;
  47 };
  48
  49 enum arm11_debug_version
  50 {
  51         ARM11_DEBUG_V6                  = 0x01,
  52         ARM11_DEBUG_V61                 = 0x02,
  53         ARM11_DEBUG_V7                  = 0x03,
  54         ARM11_DEBUG_V7_CP14             = 0x04,
  55 };
  56
  57 struct arm11_common
  58 {
  59         struct arm      arm;
  60         struct target * target;         /**< Reference back to the owner */
  61
  62         /** \name Processor type detection */
  63         /*@{*/
  64
  65         size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
  66         size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
  67
  68         /*@}*/
  69
  70         uint32_t                last_dscr;              /**< Last retrieved DSCR value;
  71                                                              Use only for debug message generation              */
  72
  73         bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
  74
  75         /** \name Shadow registers to save processor state */
  76         /*@{*/
  77
  78         struct reg *    reg_list;                                                       /**< target register list */
  79         uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
  80
  81         /*@}*/
  82
  83         struct arm11_register_history
  84                 reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
  85
  86         size_t  free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
  87         size_t  free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
  88
  89         // GA
  90         struct reg_cache *core_cache;
  91
  92         struct arm_jtag jtag_info;
  93 };
  94
  95 static inline struct arm11_common *target_to_arm11(struct target *target)
  96 {
  97         return container_of(target->arch_info, struct arm11_common,
  98                         arm);
  99 }
 100
 101 /**
 102  * ARM11 DBGTAP instructions
 103  *
 104  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
 105  */
 106 enum arm11_instructions
 107 {
 108         ARM11_EXTEST    = 0x00,
 109         ARM11_SCAN_N    = 0x02,
 110         ARM11_RESTART   = 0x04,
 111         ARM11_HALT          = 0x08,
 112         ARM11_INTEST    = 0x0C,
 113         ARM11_ITRSEL    = 0x1D,
 114         ARM11_IDCODE    = 0x1E,
 115         ARM11_BYPASS    = 0x1F,
 116 };
 117
 118 enum arm11_dscr
 119 {
 120         ARM11_DSCR_CORE_HALTED                                                                  = 1 << 0,
 121         ARM11_DSCR_CORE_RESTARTED                                                               = 1 << 1,
 122
 123         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK                                   = 0x0F << 2,
 124         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT                                   = 0x00 << 2,
 125         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT                             = 0x01 << 2,
 126         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT                             = 0x02 << 2,
 127         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION               = 0x03 << 2,
 128         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ                                 = 0x04 << 2,
 129         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH                   = 0x05 << 2,
 130
 131         ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                                    = 1 << 6,
 132         ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT                                  = 1 << 7,
 133         ARM11_DSCR_INTERRUPTS_DISABLE                                                   = 1 << 11,
 134         ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE                               = 1 << 13,
 135         ARM11_DSCR_MODE_SELECT                                                                  = 1 << 14,
 136         ARM11_DSCR_WDTR_FULL                                                                    = 1 << 29,
 137         ARM11_DSCR_RDTR_FULL                                                                    = 1 << 30,
 138 };
 139
 140 enum arm11_cpsr
 141 {
 142         ARM11_CPSR_T                            = 1 << 5,
 143         ARM11_CPSR_J                            = 1 << 24,
 144 };
 145
 146 enum arm11_sc7
 147 {
 148         ARM11_SC7_NULL                          = 0,
 149         ARM11_SC7_VCR                           = 7,
 150         ARM11_SC7_PC                            = 8,
 151         ARM11_SC7_BVR0                          = 64,
 152         ARM11_SC7_BCR0                          = 80,
 153         ARM11_SC7_WVR0                          = 96,
 154         ARM11_SC7_WCR0                          = 112,
 155 };
 156
 157 struct arm11_reg_state
 158 {
 159         uint32_t                                def_index;
 160         struct target *                 target;
 161 };
 162
 163 #endif /* ARM11_H */