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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 #ifndef ARM11_H
  24 #define ARM11_H
  25
  26 #include "armv4_5.h"
  27
  28 #define NEW(type, variable, items)                      \
  29         type * variable = calloc(1, sizeof(type) * items)
  30
  31 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
  32 /* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW    */
  33
  34 #if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO))
  35 #define ZU              "%zu"
  36 #else
  37 #define ZU              "%Iu"
  38 #endif
  39
  40 #define ARM11_REGCACHE_MODEREGS         0
  41 #define ARM11_REGCACHE_FREGS            0
  42
  43 #define ARM11_REGCACHE_COUNT            (20 +                                   \
  44                                          23 * ARM11_REGCACHE_MODEREGS +                 \
  45                                           9 * ARM11_REGCACHE_FREGS)
  46
  47 #define ARM11_TAP_DEFAULT                       TAP_INVALID
  48
  49
  50 #define CHECK_RETVAL(action)                                                            \
  51 do {                                                                                                            \
  52         int __retval = (action);                                                                \
  53                                                                                                                         \
  54         if (__retval != ERROR_OK)                                                               \
  55         {                                                                                                               \
  56                 LOG_DEBUG("error while calling \"" # action "\"");      \
  57                 return __retval;                                                                        \
  58         }                                                                                                               \
  59                                                                                                                         \
  60 } while (0)
  61
  62
  63 struct arm11_register_history
  64 {
  65         uint32_t                value;
  66         uint8_t         valid;
  67 };
  68
  69 enum arm11_debug_version
  70 {
  71         ARM11_DEBUG_V6                  = 0x01,
  72         ARM11_DEBUG_V61                 = 0x02,
  73         ARM11_DEBUG_V7                  = 0x03,
  74         ARM11_DEBUG_V7_CP14             = 0x04,
  75 };
  76
  77 struct arm11_common
  78 {
  79         struct arm      arm;
  80         struct target * target;         /**< Reference back to the owner */
  81
  82         /** \name Processor type detection */
  83         /*@{*/
  84
  85         uint32_t                device_id;              /**< IDCODE readout                             */
  86         uint32_t                didr;                   /**< DIDR readout (debug capabilities)  */
  87         uint8_t         implementor;    /**< DIDR Implementor readout           */
  88
  89         size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
  90         size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
  91
  92         enum arm11_debug_version
  93                 debug_version;          /**< ARM debug architecture from DIDR   */
  94         /*@}*/
  95
  96         uint32_t                last_dscr;              /**< Last retrieved DSCR value;
  97                                                              Use only for debug message generation              */
  98
  99         bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
 100
 101         /** \name Shadow registers to save processor state */
 102         /*@{*/
 103
 104         struct reg *    reg_list;                                                       /**< target register list */
 105         uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
 106
 107         /*@}*/
 108
 109         struct arm11_register_history
 110                 reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
 111
 112         size_t  free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
 113         size_t  free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
 114
 115         // GA
 116         struct reg_cache *core_cache;
 117
 118         struct arm_jtag jtag_info;
 119 };
 120
 121 static inline struct arm11_common *target_to_arm11(struct target *target)
 122 {
 123         return container_of(target->arch_info, struct arm11_common,
 124                         arm);
 125 }
 126
 127 /**
 128  * ARM11 DBGTAP instructions
 129  *
 130  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
 131  */
 132 enum arm11_instructions
 133 {
 134         ARM11_EXTEST    = 0x00,
 135         ARM11_SCAN_N    = 0x02,
 136         ARM11_RESTART   = 0x04,
 137         ARM11_HALT          = 0x08,
 138         ARM11_INTEST    = 0x0C,
 139         ARM11_ITRSEL    = 0x1D,
 140         ARM11_IDCODE    = 0x1E,
 141         ARM11_BYPASS    = 0x1F,
 142 };
 143
 144 enum arm11_dscr
 145 {
 146         ARM11_DSCR_CORE_HALTED                                                                  = 1 << 0,
 147         ARM11_DSCR_CORE_RESTARTED                                                               = 1 << 1,
 148
 149         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK                                   = 0x0F << 2,
 150         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT                                   = 0x00 << 2,
 151         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT                             = 0x01 << 2,
 152         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT                             = 0x02 << 2,
 153         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION               = 0x03 << 2,
 154         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ                                 = 0x04 << 2,
 155         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH                   = 0x05 << 2,
 156
 157         ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                                    = 1 << 6,
 158         ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT                                  = 1 << 7,
 159         ARM11_DSCR_INTERRUPTS_DISABLE                                                   = 1 << 11,
 160         ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE                               = 1 << 13,
 161         ARM11_DSCR_MODE_SELECT                                                                  = 1 << 14,
 162         ARM11_DSCR_WDTR_FULL                                                                    = 1 << 29,
 163         ARM11_DSCR_RDTR_FULL                                                                    = 1 << 30,
 164 };
 165
 166 enum arm11_cpsr
 167 {
 168         ARM11_CPSR_T                            = 1 << 5,
 169         ARM11_CPSR_J                            = 1 << 24,
 170 };
 171
 172 enum arm11_sc7
 173 {
 174         ARM11_SC7_NULL                          = 0,
 175         ARM11_SC7_VCR                           = 7,
 176         ARM11_SC7_PC                            = 8,
 177         ARM11_SC7_BVR0                          = 64,
 178         ARM11_SC7_BCR0                          = 80,
 179         ARM11_SC7_WVR0                          = 96,
 180         ARM11_SC7_WCR0                          = 112,
 181 };
 182
 183 struct arm11_reg_state
 184 {
 185         uint32_t                                def_index;
 186         struct target *                 target;
 187 };
 188
 189 #endif /* ARM11_H */