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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 #ifndef ARM11_H
  24 #define ARM11_H
  25
  26 #include "target.h"
  27 #include "register.h"
  28 #include "jtag.h"
  29
  30 #define asizeof(x)      (sizeof(x) / sizeof((x)[0]))
  31
  32 #define NEW(type, variable, items)                      \
  33         type * variable = calloc(1, sizeof(type) * items)
  34
  35 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
  36
  37 #ifndef __MSVCRT__
  38 #define ZU              "%zu"
  39 #else
  40 #define ZU              "%Iu"
  41 #endif
  42
  43 #define ARM11_REGCACHE_MODEREGS         0
  44 #define ARM11_REGCACHE_FREGS            0
  45
  46 #define ARM11_REGCACHE_COUNT            (20 +                                   \
  47                                          23 * ARM11_REGCACHE_MODEREGS +                 \
  48                                           9 * ARM11_REGCACHE_FREGS)
  49
  50 #define ARM11_TAP_DEFAULT                       TAP_INVALID
  51
  52
  53 #define CHECK_RETVAL(action)                                                            \
  54 do {                                                                                                            \
  55         int __retval = (action);                                                                \
  56                                                                                                                         \
  57         if (__retval != ERROR_OK)                                                               \
  58         {                                                                                                               \
  59                 LOG_DEBUG("error while calling \"" # action "\"");      \
  60                 return __retval;                                                                        \
  61         }                                                                                                               \
  62                                                                                                                         \
  63 } while (0)
  64
  65
  66 typedef struct arm11_register_history_s
  67 {
  68         u32             value;
  69         u8              valid;
  70 }arm11_register_history_t;
  71
  72 enum arm11_debug_version
  73 {
  74         ARM11_DEBUG_V6                  = 0x01,
  75         ARM11_DEBUG_V61                 = 0x02,
  76         ARM11_DEBUG_V7                  = 0x03,
  77         ARM11_DEBUG_V7_CP14             = 0x04,
  78 };
  79
  80 typedef struct arm11_common_s
  81 {
  82         target_t *      target;         /**< Reference back to the owner */
  83
  84         /** \name Processor type detection */
  85         /*@{*/
  86
  87         u32             device_id;              /**< IDCODE readout                             */
  88         u32             didr;                   /**< DIDR readout (debug capabilities)  */
  89         u8              implementor;    /**< DIDR Implementor readout           */
  90
  91         size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
  92         size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
  93
  94         enum arm11_debug_version
  95                 debug_version;          /**< ARM debug architecture from DIDR   */
  96         /*@}*/
  97
  98         u32             last_dscr;              /**< Last retrieved DSCR value;
  99                                                              Use only for debug message generation              */
 100
 101         bool    trst_active;
 102         bool    halt_requested;                                 /**< Keep track if arm11_halt() calls occured
 103                                                                                                  during reset. Otherwise do it ASAP. */
 104
 105         bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
 106
 107         /** \name Shadow registers to save processor state */
 108         /*@{*/
 109
 110         reg_t * reg_list;                                                       /**< target register list */
 111         u32             reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
 112
 113         /*@}*/
 114
 115         arm11_register_history_t
 116                 reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
 117
 118         size_t  free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
 119         size_t  free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
 120
 121         // GA
 122         reg_cache_t *core_cache;
 123 } arm11_common_t;
 124
 125
 126 /**
 127  * ARM11 DBGTAP instructions
 128  *
 129  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
 130  */
 131 enum arm11_instructions
 132 {
 133         ARM11_EXTEST    = 0x00,
 134         ARM11_SCAN_N    = 0x02,
 135         ARM11_RESTART   = 0x04,
 136         ARM11_HALT          = 0x08,
 137         ARM11_INTEST    = 0x0C,
 138         ARM11_ITRSEL    = 0x1D,
 139         ARM11_IDCODE    = 0x1E,
 140         ARM11_BYPASS    = 0x1F,
 141 };
 142
 143 enum arm11_dscr
 144 {
 145         ARM11_DSCR_CORE_HALTED                                                                  = 1 << 0,
 146         ARM11_DSCR_CORE_RESTARTED                                                               = 1 << 1,
 147
 148         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK                                   = 0x0F << 2,
 149         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT                                   = 0x00 << 2,
 150         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT                             = 0x01 << 2,
 151         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT                             = 0x02 << 2,
 152         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION               = 0x03 << 2,
 153         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ                                 = 0x04 << 2,
 154         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH                   = 0x05 << 2,
 155
 156         ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                                    = 1 << 6,
 157         ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT                                  = 1 << 7,
 158         ARM11_DSCR_INTERRUPTS_DISABLE                                                   = 1 << 11,
 159         ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE                               = 1 << 13,
 160         ARM11_DSCR_MODE_SELECT                                                                  = 1 << 14,
 161         ARM11_DSCR_WDTR_FULL                                                                    = 1 << 29,
 162         ARM11_DSCR_RDTR_FULL                                                                    = 1 << 30,
 163 };
 164
 165 enum arm11_cpsr
 166 {
 167         ARM11_CPSR_T                            = 1 << 5,
 168         ARM11_CPSR_J                            = 1 << 24,
 169 };
 170
 171 enum arm11_sc7
 172 {
 173         ARM11_SC7_NULL                          = 0,
 174         ARM11_SC7_VCR                           = 7,
 175         ARM11_SC7_PC                            = 8,
 176         ARM11_SC7_BVR0                          = 64,
 177         ARM11_SC7_BCR0                          = 80,
 178         ARM11_SC7_WVR0                          = 96,
 179         ARM11_SC7_WCR0                          = 112,
 180 };
 181
 182 typedef struct arm11_reg_state_s
 183 {
 184         u32                             def_index;
 185         target_t *                      target;
 186 } arm11_reg_state_t;
 187
 188 /* poll current target status */
 189 int arm11_poll(struct target_s *target);
 190 /* architecture specific status reply */
 191 int arm11_arch_state(struct target_s *target);
 192
 193 /* target request support */
 194 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
 195
 196 /* target execution control */
 197 int arm11_halt(struct target_s *target);
 198 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
 199 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
 200 int arm11_examine(struct target_s *target);
 201
 202 /* target reset control */
 203 int arm11_assert_reset(struct target_s *target);
 204 int arm11_deassert_reset(struct target_s *target);
 205 int arm11_soft_reset_halt(struct target_s *target);
 206
 207 /* target register access for gdb */
 208 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
 209
 210 /* target memory access
 211 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 212 * count: number of items of <size>
 213 */
 214 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 215 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 216
 217 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
 218 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
 219
 220 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
 221
 222 /* target break-/watchpoint control
 223 * rw: 0 = write, 1 = read, 2 = access
 224 */
 225 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 226 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 227 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 228 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 229
 230 /* target algorithm support */
 231 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
 232
 233 int arm11_register_commands(struct command_context_s *cmd_ctx);
 234 int arm11_target_create(struct target_s *target, Jim_Interp *interp);
 235 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 236 int arm11_quit(void);
 237
 238 /* helpers */
 239 int arm11_build_reg_cache(target_t *target);
 240 int arm11_set_reg(reg_t *reg, u8 *buf);
 241 int arm11_get_reg(reg_t *reg);
 242
 243 void arm11_record_register_history(arm11_common_t * arm11);
 244 void arm11_dump_reg_changes(arm11_common_t * arm11);
 245
 246 /* internals */
 247
 248 void arm11_setup_field                  (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
 249 void arm11_add_IR                               (arm11_common_t * arm11, u8 instr, tap_state_t state);
 250 void arm11_add_debug_SCAN_N             (arm11_common_t * arm11, u8 chain, tap_state_t state);
 251 void arm11_add_debug_INST               (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
 252 int arm11_read_DSCR                             (arm11_common_t * arm11, u32 *dscr);
 253 int arm11_write_DSCR                    (arm11_common_t * arm11, u32 dscr);
 254
 255 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
 256
 257 void arm11_run_instr_data_prepare                       (arm11_common_t * arm11);
 258 void arm11_run_instr_data_finish                        (arm11_common_t * arm11);
 259 int arm11_run_instr_no_data                                     (arm11_common_t * arm11, u32 * opcode, size_t count);
 260 void arm11_run_instr_no_data1                           (arm11_common_t * arm11, u32 opcode);
 261 int arm11_run_instr_data_to_core                        (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
 262 int arm11_run_instr_data_to_core_noack          (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
 263 int arm11_run_instr_data_to_core1                       (arm11_common_t * arm11, u32 opcode, u32 data);
 264 int arm11_run_instr_data_from_core                      (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
 265 void arm11_run_instr_data_from_core_via_r0      (arm11_common_t * arm11, u32 opcode, u32 * data);
 266 void arm11_run_instr_data_to_core_via_r0        (arm11_common_t * arm11, u32 opcode, u32 data);
 267
 268 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
 269 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
 270
 271 /** Used to make a list of read/write commands for scan chain 7
 272  *
 273  *  Use with arm11_sc7_run()
 274  */
 275 typedef struct arm11_sc7_action_s
 276 {
 277         bool    write;                          /**< Access mode: true for write, false for read.       */
 278         u8              address;                        /**< Register address mode. Use enum #arm11_sc7         */
 279         u32             value;                          /**< If write then set this to value to be written.
 280                                                                          In read mode this receives the read value when the
 281                                                                          function returns.                                      */
 282 } arm11_sc7_action_t;
 283
 284 int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
 285
 286 /* Mid-level helper functions */
 287 void arm11_sc7_clear_vbw(arm11_common_t * arm11);
 288 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
 289
 290 int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
 291
 292 #endif /* ARM11_H */