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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "etm.h"
  30 #include "breakpoints.h"
  31 #include "arm11_dbgtap.h"
  32 #include "arm_simulator.h"
  33 #include <helper/time_support.h>
  34 #include "target_type.h"
  35 #include "algorithm.h"
  36 #include "register.h"
  37 #include "arm_opcodes.h"
  38
  39
  40 #if 0
  41 #define _DEBUG_INSTRUCTION_EXECUTION_
  42 #endif
  43
  44
  45 /* FIXME none of these flags should be global to all ARM11 cores!
  46  * Most of them shouldn't exist at all, once the code works...
  47  */
  48 static bool arm11_config_memwrite_burst = true;
  49 static bool arm11_config_memwrite_error_fatal = true;
  50 static uint32_t arm11_vcr = 0;
  51 static bool arm11_config_step_irq_enable = false;
  52 static bool arm11_config_hardware_step = false;
  53
  54 static int arm11_step(struct target *target, int current,
  55                 uint32_t address, int handle_breakpoints);
  56
  57
  58 /** Check and if necessary take control of the system
  59  *
  60  * \param arm11         Target state variable.
  61  */
  62 static int arm11_check_init(struct arm11_common *arm11)
  63 {
  64         CHECK_RETVAL(arm11_read_DSCR(arm11));
  65         LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
  66
  67         if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
  68         {
  69                 LOG_DEBUG("Bringing target into debug mode");
  70
  71                 arm11->dscr |= DSCR_HALT_DBG_MODE;
  72                 arm11_write_DSCR(arm11, arm11->dscr);
  73
  74                 /* add further reset initialization here */
  75
  76                 arm11->simulate_reset_on_next_halt = true;
  77
  78                 if (arm11->dscr & DSCR_CORE_HALTED)
  79                 {
  80                         /** \todo TODO: this needs further scrutiny because
  81                           * arm11_debug_entry() never gets called.  (WHY NOT?)
  82                           * As a result we don't read the actual register states from
  83                           * the target.
  84                           */
  85
  86                         arm11->arm.target->state = TARGET_HALTED;
  87                         arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
  88                 }
  89                 else
  90                 {
  91                         arm11->arm.target->state = TARGET_RUNNING;
  92                         arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
  93                 }
  94
  95                 arm11_sc7_clear_vbw(arm11);
  96         }
  97
  98         return ERROR_OK;
  99 }
 100
 101 /**
 102  * Save processor state.  This is called after a HALT instruction
 103  * succeeds, and on other occasions the processor enters debug mode
 104  * (breakpoint, watchpoint, etc).  Caller has updated arm11->dscr.
 105  */
 106 static int arm11_debug_entry(struct arm11_common *arm11)
 107 {
 108         int retval;
 109
 110         arm11->arm.target->state = TARGET_HALTED;
 111         arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
 112
 113         /* REVISIT entire cache should already be invalid !!! */
 114         register_cache_invalidate(arm11->arm.core_cache);
 115
 116         /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
 117
 118         /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
 119         arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
 120         if (arm11->is_wdtr_saved)
 121         {
 122                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 123
 124                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 125
 126                 struct scan_field       chain5_fields[3];
 127
 128                 arm11_setup_field(arm11, 32, NULL,
 129                                 &arm11->saved_wdtr, chain5_fields + 0);
 130                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
 131                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
 132
 133                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 134
 135         }
 136
 137         /* DSCR: set the Execute ARM instruction enable bit.
 138          *
 139          * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
 140          * but not to issue ITRs(?).  The ARMv7 arch spec says it's required
 141          * for executing instructions via ITR.
 142          */
 143         arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
 144
 145
 146         /* From the spec:
 147            Before executing any instruction in debug state you have to drain the write buffer.
 148            This ensures that no imprecise Data Aborts can return at a later point:*/
 149
 150         /** \todo TODO: Test drain write buffer. */
 151
 152 #if 0
 153         while (1)
 154         {
 155                 /* MRC p14,0,R0,c5,c10,0 */
 156                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 157
 158                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 159                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 160
 161                 uint32_t dscr = arm11_read_DSCR(arm11);
 162
 163                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 164
 165                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 166                 {
 167                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 168
 169                         dscr = arm11_read_DSCR(arm11);
 170
 171                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 172
 173                         break;
 174                 }
 175         }
 176 #endif
 177
 178         /* Save registers.
 179          *
 180          * NOTE:  ARM1136 TRM suggests saving just R0 here now, then
 181          * CPSR and PC after the rDTR stuff.  We do it all at once.
 182          */
 183         retval = arm_dpm_read_current_registers(&arm11->dpm);
 184         if (retval != ERROR_OK)
 185                 LOG_ERROR("DPM REG READ -- fail %d", retval);
 186
 187         retval = arm11_run_instr_data_prepare(arm11);
 188         if (retval != ERROR_OK)
 189                 return retval;
 190
 191         /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
 192         arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
 193         if (arm11->is_rdtr_saved)
 194         {
 195                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 196                 retval = arm11_run_instr_data_from_core_via_r0(arm11,
 197                                 0xEE100E15, &arm11->saved_rdtr);
 198                 if (retval != ERROR_OK)
 199                         return retval;
 200         }
 201
 202         /* REVISIT Now that we've saved core state, there's may also
 203          * be MMU and cache state to care about ...
 204          */
 205
 206         if (arm11->simulate_reset_on_next_halt)
 207         {
 208                 arm11->simulate_reset_on_next_halt = false;
 209
 210                 LOG_DEBUG("Reset c1 Control Register");
 211
 212                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 213
 214                 /* MCR p15,0,R0,c1,c0,0 */
 215                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 216                 if (retval != ERROR_OK)
 217                         return retval;
 218
 219         }
 220
 221         if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
 222                 uint32_t wfar;
 223
 224                 /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
 225                 retval = arm11_run_instr_data_from_core_via_r0(arm11,
 226                                 ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
 227                                 &wfar);
 228                 if (retval != ERROR_OK)
 229                         return retval;
 230                 arm_dpm_report_wfar(arm11->arm.dpm, wfar);
 231         }
 232
 233
 234         retval = arm11_run_instr_data_finish(arm11);
 235         if (retval != ERROR_OK)
 236                 return retval;
 237
 238         return ERROR_OK;
 239 }
 240
 241 /**
 242  * Restore processor state.  This is called in preparation for
 243  * the RESTART function.
 244  */
 245 static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 246 {
 247         int retval;
 248
 249         /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
 250
 251         /* NOTE:  the ARM1136 TRM suggests restoring all registers
 252          * except R0/PC/CPSR right now.  Instead, we do them all
 253          * at once, just a bit later on.
 254          */
 255
 256         /* REVISIT once we start caring about MMU and cache state,
 257          * address it here ...
 258          */
 259
 260         /* spec says clear wDTR and rDTR; we assume they are clear as
 261            otherwise our programming would be sloppy */
 262         {
 263                 CHECK_RETVAL(arm11_read_DSCR(arm11));
 264
 265                 if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL))
 266                 {
 267                         /*
 268                         The wDTR/rDTR two registers that are used to send/receive data to/from
 269                         the core in tandem with corresponding instruction codes that are
 270                         written into the core. The RDTR FULL/WDTR FULL flag indicates that the
 271                         registers hold data that was written by one side (CPU or JTAG) and not
 272                         read out by the other side.
 273                         */
 274                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
 275                                         (unsigned) arm11->dscr);
 276                         return ERROR_FAIL;
 277                 }
 278         }
 279
 280         /* maybe restore original wDTR */
 281         if (arm11->is_wdtr_saved)
 282         {
 283                 retval = arm11_run_instr_data_prepare(arm11);
 284                 if (retval != ERROR_OK)
 285                         return retval;
 286
 287                 /* MCR p14,0,R0,c0,c5,0 */
 288                 retval = arm11_run_instr_data_to_core_via_r0(arm11,
 289                                 0xee000e15, arm11->saved_wdtr);
 290                 if (retval != ERROR_OK)
 291                         return retval;
 292
 293                 retval = arm11_run_instr_data_finish(arm11);
 294                 if (retval != ERROR_OK)
 295                         return retval;
 296         }
 297
 298         /* restore CPSR, PC, and R0 ... after flushing any modified
 299          * registers.
 300          */
 301         retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
 302
 303         retval = arm11_bpwp_flush(arm11);
 304
 305         register_cache_invalidate(arm11->arm.core_cache);
 306
 307         /* restore DSCR */
 308         arm11_write_DSCR(arm11, arm11->dscr);
 309
 310         /* maybe restore rDTR */
 311         if (arm11->is_rdtr_saved)
 312         {
 313                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 314
 315                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 316
 317                 struct scan_field       chain5_fields[3];
 318
 319                 uint8_t                 Ready           = 0;    /* ignored */
 320                 uint8_t                 Valid           = 0;    /* ignored */
 321
 322                 arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
 323                                 NULL, chain5_fields + 0);
 324                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 325                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 326
 327                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 328         }
 329
 330         /* now processor is ready to RESTART */
 331
 332         return ERROR_OK;
 333 }
 334
 335 /* poll current target status */
 336 static int arm11_poll(struct target *target)
 337 {
 338         int retval;
 339         struct arm11_common *arm11 = target_to_arm11(target);
 340
 341         CHECK_RETVAL(arm11_check_init(arm11));
 342
 343         if (arm11->dscr & DSCR_CORE_HALTED)
 344         {
 345                 if (target->state != TARGET_HALTED)
 346                 {
 347                         enum target_state old_state = target->state;
 348
 349                         LOG_DEBUG("enter TARGET_HALTED");
 350                         retval = arm11_debug_entry(arm11);
 351                         if (retval != ERROR_OK)
 352                                 return retval;
 353
 354                         target_call_event_callbacks(target,
 355                                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
 356                 }
 357         }
 358         else
 359         {
 360                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 361                 {
 362                         LOG_DEBUG("enter TARGET_RUNNING");
 363                         target->state                   = TARGET_RUNNING;
 364                         target->debug_reason    = DBG_REASON_NOTHALTED;
 365                 }
 366         }
 367
 368         return ERROR_OK;
 369 }
 370 /* architecture specific status reply */
 371 static int arm11_arch_state(struct target *target)
 372 {
 373         struct arm11_common *arm11 = target_to_arm11(target);
 374         int retval;
 375
 376         retval = armv4_5_arch_state(target);
 377
 378         /* REVISIT also display ARM11-specific MMU and cache status ... */
 379
 380         if (target->debug_reason == DBG_REASON_WATCHPOINT)
 381                 LOG_USER("Watchpoint triggered at PC %#08x",
 382                                 (unsigned) arm11->dpm.wp_pc);
 383
 384         return retval;
 385 }
 386
 387 /* target request support */
 388 static int arm11_target_request_data(struct target *target,
 389                 uint32_t size, uint8_t *buffer)
 390 {
 391         LOG_WARNING("Not implemented: %s", __func__);
 392
 393         return ERROR_FAIL;
 394 }
 395
 396 /* target execution control */
 397 static int arm11_halt(struct target *target)
 398 {
 399         struct arm11_common *arm11 = target_to_arm11(target);
 400
 401         LOG_DEBUG("target->state: %s",
 402                 target_state_name(target));
 403
 404         if (target->state == TARGET_UNKNOWN)
 405         {
 406                 arm11->simulate_reset_on_next_halt = true;
 407         }
 408
 409         if (target->state == TARGET_HALTED)
 410         {
 411                 LOG_DEBUG("target was already halted");
 412                 return ERROR_OK;
 413         }
 414
 415         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 416
 417         CHECK_RETVAL(jtag_execute_queue());
 418
 419         int i = 0;
 420
 421         while (1)
 422         {
 423                 CHECK_RETVAL(arm11_read_DSCR(arm11));
 424
 425                 if (arm11->dscr & DSCR_CORE_HALTED)
 426                         break;
 427
 428
 429                 long long then = 0;
 430                 if (i == 1000)
 431                 {
 432                         then = timeval_ms();
 433                 }
 434                 if (i >= 1000)
 435                 {
 436                         if ((timeval_ms()-then) > 1000)
 437                         {
 438                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 439                                 return ERROR_FAIL;
 440                         }
 441                 }
 442                 i++;
 443         }
 444
 445         enum target_state old_state     = target->state;
 446
 447         arm11_debug_entry(arm11);
 448
 449         CHECK_RETVAL(
 450                 target_call_event_callbacks(target,
 451                         old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 452
 453         return ERROR_OK;
 454 }
 455
 456 static uint32_t
 457 arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
 458 {
 459         void *value = arm11->arm.core_cache->reg_list[15].value;
 460
 461         if (!current)
 462                 buf_set_u32(value, 0, 32, address);
 463         else
 464                 address = buf_get_u32(value, 0, 32);
 465
 466         return address;
 467 }
 468
 469 static int arm11_resume(struct target *target, int current,
 470                 uint32_t address, int handle_breakpoints, int debug_execution)
 471 {
 472         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 473         //      current, address, handle_breakpoints, debug_execution);
 474
 475         struct arm11_common *arm11 = target_to_arm11(target);
 476
 477         LOG_DEBUG("target->state: %s",
 478                 target_state_name(target));
 479
 480
 481         if (target->state != TARGET_HALTED)
 482         {
 483                 LOG_ERROR("Target not halted");
 484                 return ERROR_TARGET_NOT_HALTED;
 485         }
 486
 487         address = arm11_nextpc(arm11, current, address);
 488
 489         LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
 490
 491         /* clear breakpoints/watchpoints and VCR*/
 492         arm11_sc7_clear_vbw(arm11);
 493
 494         if (!debug_execution)
 495                 target_free_all_working_areas(target);
 496
 497         /* Set up breakpoints */
 498         if (handle_breakpoints)
 499         {
 500                 /* check if one matches PC and step over it if necessary */
 501
 502                 struct breakpoint *     bp;
 503
 504                 for (bp = target->breakpoints; bp; bp = bp->next)
 505                 {
 506                         if (bp->address == address)
 507                         {
 508                                 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 509                                 arm11_step(target, 1, 0, 0);
 510                                 break;
 511                         }
 512                 }
 513
 514                 /* set all breakpoints */
 515
 516                 unsigned brp_num = 0;
 517
 518                 for (bp = target->breakpoints; bp; bp = bp->next)
 519                 {
 520                         struct arm11_sc7_action brp[2];
 521
 522                         brp[0].write    = 1;
 523                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 524                         brp[0].value    = bp->address;
 525                         brp[1].write    = 1;
 526                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 527                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 528
 529                         arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
 530
 531                         LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
 532                                         bp->address);
 533
 534                         brp_num++;
 535                 }
 536
 537                 if (arm11_vcr)
 538                         arm11_sc7_set_vcr(arm11, arm11_vcr);
 539         }
 540
 541         arm11_leave_debug_state(arm11, handle_breakpoints);
 542
 543         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 544
 545         CHECK_RETVAL(jtag_execute_queue());
 546
 547         int i = 0;
 548         while (1)
 549         {
 550                 CHECK_RETVAL(arm11_read_DSCR(arm11));
 551
 552                 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
 553
 554                 if (arm11->dscr & DSCR_CORE_RESTARTED)
 555                         break;
 556
 557
 558                 long long then = 0;
 559                 if (i == 1000)
 560                 {
 561                         then = timeval_ms();
 562                 }
 563                 if (i >= 1000)
 564                 {
 565                         if ((timeval_ms()-then) > 1000)
 566                         {
 567                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 568                                 return ERROR_FAIL;
 569                         }
 570                 }
 571                 i++;
 572         }
 573
 574         target->debug_reason = DBG_REASON_NOTHALTED;
 575         if (!debug_execution)
 576                 target->state = TARGET_RUNNING;
 577         else
 578                 target->state = TARGET_DEBUG_RUNNING;
 579         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 580
 581         return ERROR_OK;
 582 }
 583
 584 static int arm11_step(struct target *target, int current,
 585                 uint32_t address, int handle_breakpoints)
 586 {
 587         LOG_DEBUG("target->state: %s",
 588                 target_state_name(target));
 589
 590         if (target->state != TARGET_HALTED)
 591         {
 592                 LOG_WARNING("target was not halted");
 593                 return ERROR_TARGET_NOT_HALTED;
 594         }
 595
 596         struct arm11_common *arm11 = target_to_arm11(target);
 597
 598         address = arm11_nextpc(arm11, current, address);
 599
 600         LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
 601
 602
 603         /** \todo TODO: Thumb not supported here */
 604
 605         uint32_t        next_instruction;
 606
 607         CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
 608
 609         /* skip over BKPT */
 610         if ((next_instruction & 0xFFF00070) == 0xe1200070)
 611         {
 612                 address = arm11_nextpc(arm11, 0, address + 4);
 613                 LOG_DEBUG("Skipping BKPT");
 614         }
 615         /* skip over Wait for interrupt / Standby */
 616         /* mcr  15, 0, r?, cr7, cr0, {4} */
 617         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
 618         {
 619                 address = arm11_nextpc(arm11, 0, address + 4);
 620                 LOG_DEBUG("Skipping WFI");
 621         }
 622         /* ignore B to self */
 623         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
 624         {
 625                 LOG_DEBUG("Not stepping jump to self");
 626         }
 627         else
 628         {
 629                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
 630                 * with this. */
 631
 632                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
 633                 * the VCR might be something worth looking into. */
 634
 635
 636                 /* Set up breakpoint for stepping */
 637
 638                 struct arm11_sc7_action brp[2];
 639
 640                 brp[0].write    = 1;
 641                 brp[0].address  = ARM11_SC7_BVR0;
 642                 brp[1].write    = 1;
 643                 brp[1].address  = ARM11_SC7_BCR0;
 644
 645                 if (arm11_config_hardware_step)
 646                 {
 647                         /* Hardware single stepping ("instruction address
 648                          * mismatch") is used if enabled.  It's not quite
 649                          * exactly "run one instruction"; "branch to here"
 650                          * loops won't break, neither will some other cases,
 651                          * but it's probably the best default.
 652                          *
 653                          * Hardware single stepping isn't supported on v6
 654                          * debug modules.  ARM1176 and v7 can support it...
 655                          *
 656                          * FIXME Thumb stepping likely needs to use 0x03
 657                          * or 0xc0 byte masks, not 0x0f.
 658                          */
 659                          brp[0].value   = address;
 660                          brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5)
 661                                         | (0 << 14) | (0 << 16) | (0 << 20)
 662                                         | (2 << 21);
 663                 } else
 664                 {
 665                         /* Sets a breakpoint on the next PC, as calculated
 666                          * by instruction set simulation.
 667                          *
 668                          * REVISIT stepping Thumb on ARM1156 requires Thumb2
 669                          * support from the simulator.
 670                          */
 671                         uint32_t next_pc;
 672                         int retval;
 673
 674                         retval = arm_simulate_step(target, &next_pc);
 675                         if (retval != ERROR_OK)
 676                                 return retval;
 677
 678                         brp[0].value    = next_pc;
 679                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5)
 680                                         | (0 << 14) | (0 << 16) | (0 << 20)
 681                                         | (0 << 21);
 682                 }
 683
 684                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
 685
 686                 /* resume */
 687
 688
 689                 if (arm11_config_step_irq_enable)
 690                         /* this disable should be redundant ... */
 691                         arm11->dscr &= ~DSCR_INT_DIS;
 692                 else
 693                         arm11->dscr |= DSCR_INT_DIS;
 694
 695
 696                 CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
 697
 698                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 699
 700                 CHECK_RETVAL(jtag_execute_queue());
 701
 702                 /* wait for halt */
 703                 int i = 0;
 704
 705                 while (1)
 706                 {
 707                         const uint32_t mask = DSCR_CORE_RESTARTED
 708                                         | DSCR_CORE_HALTED;
 709
 710                         CHECK_RETVAL(arm11_read_DSCR(arm11));
 711                         LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
 712
 713                         if ((arm11->dscr & mask) == mask)
 714                                 break;
 715
 716                         long long then = 0;
 717                         if (i == 1000)
 718                         {
 719                                 then = timeval_ms();
 720                         }
 721                         if (i >= 1000)
 722                         {
 723                                 if ((timeval_ms()-then) > 1000)
 724                                 {
 725                                         LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 726                                         return ERROR_FAIL;
 727                                 }
 728                         }
 729                         i++;
 730                 }
 731
 732                 /* clear breakpoint */
 733                 arm11_sc7_clear_vbw(arm11);
 734
 735                 /* save state */
 736                 CHECK_RETVAL(arm11_debug_entry(arm11));
 737
 738                 /* restore default state */
 739                 arm11->dscr &= ~DSCR_INT_DIS;
 740
 741         }
 742
 743         target->debug_reason = DBG_REASON_SINGLESTEP;
 744
 745         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 746
 747         return ERROR_OK;
 748 }
 749
 750 static int arm11_assert_reset(struct target *target)
 751 {
 752         int retval;
 753         struct arm11_common *arm11 = target_to_arm11(target);
 754
 755         retval = arm11_check_init(arm11);
 756         if (retval != ERROR_OK)
 757                 return retval;
 758
 759         target->state = TARGET_UNKNOWN;
 760
 761         /* we would very much like to reset into the halted, state,
 762          * but resetting and halting is second best... */
 763         if (target->reset_halt)
 764         {
 765                 CHECK_RETVAL(target_halt(target));
 766         }
 767
 768
 769         /* srst is funny. We can not do *anything* else while it's asserted
 770          * and it has unkonwn side effects. Make sure no other code runs
 771          * meanwhile.
 772          *
 773          * Code below assumes srst:
 774          *
 775          * - Causes power-on-reset (but of what parts of the system?). Bug
 776          * in arm11?
 777          *
 778          * - Messes us TAP state without asserting trst.
 779          *
 780          * - There is another bug in the arm11 core. When you generate an access to
 781          * external logic (for example ddr controller via AHB bus) and that block
 782          * is not configured (perhaps it is still held in reset), that transaction
 783          * will never complete. This will hang arm11 core but it will also hang
 784          * JTAG controller. Nothing, short of srst assertion will bring it out of
 785          * this.
 786          *
 787          * Mysteries:
 788          *
 789          * - What should the PC be after an srst reset when starting in the halted
 790          * state?
 791          */
 792
 793         jtag_add_reset(0, 1);
 794         jtag_add_reset(0, 0);
 795
 796         /* How long do we have to wait? */
 797         jtag_add_sleep(5000);
 798
 799         /* un-mess up TAP state */
 800         jtag_add_tlr();
 801
 802         retval = jtag_execute_queue();
 803         if (retval != ERROR_OK)
 804         {
 805                 return retval;
 806         }
 807
 808         return ERROR_OK;
 809 }
 810
 811 static int arm11_deassert_reset(struct target *target)
 812 {
 813         return ERROR_OK;
 814 }
 815
 816 static int arm11_soft_reset_halt(struct target *target)
 817 {
 818         LOG_WARNING("Not implemented: %s", __func__);
 819
 820         return ERROR_FAIL;
 821 }
 822
 823 /* target memory access
 824  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 825  * count: number of items of <size>
 826  *
 827  * arm11_config_memrw_no_increment - in the future we may want to be able
 828  * to read/write a range of data to a "port". a "port" is an action on
 829  * read memory address for some peripheral.
 830  */
 831 static int arm11_read_memory_inner(struct target *target,
 832                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
 833                 bool arm11_config_memrw_no_increment)
 834 {
 835         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
 836         int retval;
 837
 838         if (target->state != TARGET_HALTED)
 839         {
 840                 LOG_WARNING("target was not halted");
 841                 return ERROR_TARGET_NOT_HALTED;
 842         }
 843
 844         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 845
 846         struct arm11_common *arm11 = target_to_arm11(target);
 847
 848         retval = arm11_run_instr_data_prepare(arm11);
 849         if (retval != ERROR_OK)
 850                 return retval;
 851
 852         /* MRC p14,0,r0,c0,c5,0 */
 853         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
 854         if (retval != ERROR_OK)
 855                 return retval;
 856
 857         switch (size)
 858         {
 859         case 1:
 860                 arm11->arm.core_cache->reg_list[1].dirty = true;
 861
 862                 for (size_t i = 0; i < count; i++)
 863                 {
 864                         /* ldrb    r1, [r0], #1 */
 865                         /* ldrb    r1, [r0] */
 866                         arm11_run_instr_no_data1(arm11,
 867                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
 868
 869                         uint32_t res;
 870                         /* MCR p14,0,R1,c0,c5,0 */
 871                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 872
 873                         *buffer++ = res;
 874                 }
 875
 876                 break;
 877
 878         case 2:
 879                 {
 880                         arm11->arm.core_cache->reg_list[1].dirty = true;
 881
 882                         for (size_t i = 0; i < count; i++)
 883                         {
 884                                 /* ldrh    r1, [r0], #2 */
 885                                 arm11_run_instr_no_data1(arm11,
 886                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
 887
 888                                 uint32_t res;
 889
 890                                 /* MCR p14,0,R1,c0,c5,0 */
 891                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 892
 893                                 uint16_t svalue = res;
 894                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
 895                         }
 896
 897                         break;
 898                 }
 899
 900         case 4:
 901                 {
 902                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
 903                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
 904                 uint32_t *words = (uint32_t *)buffer;
 905
 906                 /* LDC p14,c5,[R0],#4 */
 907                 /* LDC p14,c5,[R0] */
 908                 arm11_run_instr_data_from_core(arm11, instr, words, count);
 909                 break;
 910                 }
 911         }
 912
 913         return arm11_run_instr_data_finish(arm11);
 914 }
 915
 916 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 917 {
 918         return arm11_read_memory_inner(target, address, size, count, buffer, false);
 919 }
 920
 921 /*
 922 * no_increment - in the future we may want to be able
 923 * to read/write a range of data to a "port". a "port" is an action on
 924 * read memory address for some peripheral.
 925 */
 926 static int arm11_write_memory_inner(struct target *target,
 927                 uint32_t address, uint32_t size,
 928                 uint32_t count, uint8_t *buffer,
 929                 bool no_increment)
 930 {
 931         int retval;
 932
 933         if (target->state != TARGET_HALTED)
 934         {
 935                 LOG_WARNING("target was not halted");
 936                 return ERROR_TARGET_NOT_HALTED;
 937         }
 938
 939         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 940
 941         struct arm11_common *arm11 = target_to_arm11(target);
 942
 943         retval = arm11_run_instr_data_prepare(arm11);
 944         if (retval != ERROR_OK)
 945                 return retval;
 946
 947         /* MRC p14,0,r0,c0,c5,0 */
 948         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
 949         if (retval != ERROR_OK)
 950                 return retval;
 951
 952         /* burst writes are not used for single words as those may well be
 953          * reset init script writes.
 954          *
 955          * The other advantage is that as burst writes are default, we'll
 956          * now exercise both burst and non-burst code paths with the
 957          * default settings, increasing code coverage.
 958          */
 959         bool burst = arm11_config_memwrite_burst && (count > 1);
 960
 961         switch (size)
 962         {
 963         case 1:
 964                 {
 965                         arm11->arm.core_cache->reg_list[1].dirty = true;
 966
 967                         for (size_t i = 0; i < count; i++)
 968                         {
 969                                 /* MRC p14,0,r1,c0,c5,0 */
 970                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
 971                                 if (retval != ERROR_OK)
 972                                         return retval;
 973
 974                                 /* strb    r1, [r0], #1 */
 975                                 /* strb    r1, [r0] */
 976                                 retval = arm11_run_instr_no_data1(arm11,
 977                                         !no_increment
 978                                                 ? 0xe4c01001
 979                                                 : 0xe5c01000);
 980                                 if (retval != ERROR_OK)
 981                                         return retval;
 982                         }
 983
 984                         break;
 985                 }
 986
 987         case 2:
 988                 {
 989                         arm11->arm.core_cache->reg_list[1].dirty = true;
 990
 991                         for (size_t i = 0; i < count; i++)
 992                         {
 993                                 uint16_t value;
 994                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
 995
 996                                 /* MRC p14,0,r1,c0,c5,0 */
 997                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
 998                                 if (retval != ERROR_OK)
 999                                         return retval;
1000
1001                                 /* strh    r1, [r0], #2 */
1002                                 /* strh    r1, [r0] */
1003                                 retval = arm11_run_instr_no_data1(arm11,
1004                                         !no_increment
1005                                                 ? 0xe0c010b2
1006                                                 : 0xe1c010b0);
1007                                 if (retval != ERROR_OK)
1008                                         return retval;
1009                         }
1010
1011                         break;
1012                 }
1013
1014         case 4: {
1015                 uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
1016
1017                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1018                 uint32_t *words = (uint32_t*)buffer;
1019
1020                 if (!burst)
1021                 {
1022                         /* STC p14,c5,[R0],#4 */
1023                         /* STC p14,c5,[R0]*/
1024                         retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1025                         if (retval != ERROR_OK)
1026                                 return retval;
1027                 }
1028                 else
1029                 {
1030                         /* STC p14,c5,[R0],#4 */
1031                         /* STC p14,c5,[R0]*/
1032                         retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1033                         if (retval != ERROR_OK)
1034                                 return retval;
1035                 }
1036
1037                 break;
1038         }
1039         }
1040
1041         /* r0 verification */
1042         if (!no_increment)
1043         {
1044                 uint32_t r0;
1045
1046                 /* MCR p14,0,R0,c0,c5,0 */
1047                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1048                 if (retval != ERROR_OK)
1049                         return retval;
1050
1051                 if (address + size * count != r0)
1052                 {
1053                         LOG_ERROR("Data transfer failed. Expected end "
1054                                         "address 0x%08x, got 0x%08x",
1055                                         (unsigned) (address + size * count),
1056                                         (unsigned) r0);
1057
1058                         if (burst)
1059                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1060
1061                         if (arm11_config_memwrite_error_fatal)
1062                                 return ERROR_FAIL;
1063                 }
1064         }
1065
1066         return arm11_run_instr_data_finish(arm11);
1067 }
1068
1069 static int arm11_write_memory(struct target *target,
1070                 uint32_t address, uint32_t size,
1071                 uint32_t count, uint8_t *buffer)
1072 {
1073         /* pointer increment matters only for multi-unit writes ...
1074          * not e.g. to a "reset the chip" controller.
1075          */
1076         return arm11_write_memory_inner(target, address, size,
1077                         count, buffer, count == 1);
1078 }
1079
1080 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1081 static int arm11_bulk_write_memory(struct target *target,
1082                 uint32_t address, uint32_t count, uint8_t *buffer)
1083 {
1084         if (target->state != TARGET_HALTED)
1085         {
1086                 LOG_WARNING("target was not halted");
1087                 return ERROR_TARGET_NOT_HALTED;
1088         }
1089
1090         return arm11_write_memory(target, address, 4, count, buffer);
1091 }
1092
1093 /* target break-/watchpoint control
1094 * rw: 0 = write, 1 = read, 2 = access
1095 */
1096 static int arm11_add_breakpoint(struct target *target,
1097                 struct breakpoint *breakpoint)
1098 {
1099         struct arm11_common *arm11 = target_to_arm11(target);
1100
1101 #if 0
1102         if (breakpoint->type == BKPT_SOFT)
1103         {
1104                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1105                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1106         }
1107 #endif
1108
1109         if (!arm11->free_brps)
1110         {
1111                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1112                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1113         }
1114
1115         if (breakpoint->length != 4)
1116         {
1117                 LOG_DEBUG("only breakpoints of four bytes length supported");
1118                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1119         }
1120
1121         arm11->free_brps--;
1122
1123         return ERROR_OK;
1124 }
1125
1126 static int arm11_remove_breakpoint(struct target *target,
1127                 struct breakpoint *breakpoint)
1128 {
1129         struct arm11_common *arm11 = target_to_arm11(target);
1130
1131         arm11->free_brps++;
1132
1133         return ERROR_OK;
1134 }
1135
1136 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1137 {
1138         struct arm11_common *arm11;
1139
1140         if (target->tap == NULL)
1141                 return ERROR_FAIL;
1142
1143         if (target->tap->ir_length != 5)
1144         {
1145                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1146                 return ERROR_COMMAND_SYNTAX_ERROR;
1147         }
1148
1149         arm11 = calloc(1, sizeof *arm11);
1150         if (!arm11)
1151                 return ERROR_FAIL;
1152
1153         armv4_5_init_arch_info(target, &arm11->arm);
1154
1155         arm11->jtag_info.tap = target->tap;
1156         arm11->jtag_info.scann_size = 5;
1157         arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1158         arm11->jtag_info.cur_scan_chain = ~0;   /* invalid/unknown */
1159         arm11->jtag_info.intest_instr = ARM11_INTEST;
1160
1161         return ERROR_OK;
1162 }
1163
1164 static int arm11_init_target(struct command_context *cmd_ctx,
1165                 struct target *target)
1166 {
1167         /* Initialize anything we can set up without talking to the target */
1168         return ERROR_OK;
1169 }
1170
1171 /* talk to the target and set things up */
1172 static int arm11_examine(struct target *target)
1173 {
1174         int retval;
1175         char *type;
1176         struct arm11_common *arm11 = target_to_arm11(target);
1177         uint32_t didr, device_id;
1178         uint8_t implementor;
1179
1180         /* FIXME split into do-first-time and do-every-time logic ... */
1181
1182         /* check IDCODE */
1183
1184         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1185
1186         struct scan_field               idcode_field;
1187
1188         arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1189
1190         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1191
1192         /* check DIDR */
1193
1194         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1195
1196         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1197
1198         struct scan_field               chain0_fields[2];
1199
1200         arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1201         arm11_setup_field(arm11,  8, NULL, &implementor, chain0_fields + 1);
1202
1203         arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1204
1205         CHECK_RETVAL(jtag_execute_queue());
1206
1207         switch (device_id & 0x0FFFF000)
1208         {
1209         case 0x07B36000:
1210                 type = "ARM1136";
1211                 break;
1212         case 0x07B56000:
1213                 type = "ARM1156";
1214                 break;
1215         case 0x07B76000:
1216                 arm11->arm.core_type = ARM_MODE_MON;
1217                 type = "ARM1176";
1218                 break;
1219         default:
1220                 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1221                 return ERROR_FAIL;
1222         }
1223         LOG_INFO("found %s", type);
1224
1225         /* unlikely this could ever fail, but ... */
1226         switch ((didr >> 16) & 0x0F) {
1227         case ARM11_DEBUG_V6:
1228         case ARM11_DEBUG_V61:           /* supports security extensions */
1229                 break;
1230         default:
1231                 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1232                 return ERROR_FAIL;
1233         }
1234
1235         arm11->brp = ((didr >> 24) & 0x0F) + 1;
1236
1237         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1238         arm11->free_brps = arm11->brp;
1239
1240         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1241                         device_id, implementor, didr);
1242
1243         /* as a side-effect this reads DSCR and thus
1244          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1245          * as suggested by the spec.
1246          */
1247
1248         retval = arm11_check_init(arm11);
1249         if (retval != ERROR_OK)
1250                 return retval;
1251
1252         /* Build register cache "late", after target_init(), since we
1253          * want to know if this core supports Secure Monitor mode.
1254          */
1255         if (!target_was_examined(target))
1256                 retval = arm11_dpm_init(arm11, didr);
1257
1258         /* ETM on ARM11 still uses original scanchain 6 access mode */
1259         if (arm11->arm.etm && !target_was_examined(target)) {
1260                 *register_get_last_cache_p(&target->reg_cache) =
1261                         etm_build_reg_cache(target, &arm11->jtag_info,
1262                                         arm11->arm.etm);
1263                 retval = etm_setup(target);
1264         }
1265
1266         target_set_examined(target);
1267
1268         return ERROR_OK;
1269 }
1270
1271
1272 /* FIXME all these BOOL_WRAPPER things should be modifying
1273  * per-instance state, not shared state; ditto the vector
1274  * catch register support.  Scan chains with multiple cores
1275  * should be able to say "work with this core like this,
1276  * that core like that".  Example, ARM11 MPCore ...
1277  */
1278
1279 #define ARM11_BOOL_WRAPPER(name, print_name)    \
1280                 COMMAND_HANDLER(arm11_handle_bool_##name) \
1281                 { \
1282                         return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1283                                         &arm11_config_##name, print_name); \
1284                 }
1285
1286 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1287 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1288 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1289 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1290
1291 COMMAND_HANDLER(arm11_handle_vcr)
1292 {
1293         switch (CMD_ARGC) {
1294         case 0:
1295                 break;
1296         case 1:
1297                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
1298                 break;
1299         default:
1300                 return ERROR_COMMAND_SYNTAX_ERROR;
1301         }
1302
1303         LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1304         return ERROR_OK;
1305 }
1306
1307 static const struct command_registration arm11_mw_command_handlers[] = {
1308         {
1309                 .name = "burst",
1310                 .handler = &arm11_handle_bool_memwrite_burst,
1311                 .mode = COMMAND_ANY,
1312                 .help = "Enable/Disable non-standard but fast burst mode"
1313                         " (default: enabled)",
1314         },
1315         {
1316                 .name = "error_fatal",
1317                 .handler = &arm11_handle_bool_memwrite_error_fatal,
1318                 .mode = COMMAND_ANY,
1319                 .help = "Terminate program if transfer error was found"
1320                         " (default: enabled)",
1321         },
1322         COMMAND_REGISTRATION_DONE
1323 };
1324 static const struct command_registration arm11_any_command_handlers[] = {
1325         {
1326                 /* "hardware_step" is only here to check if the default
1327                  * simulate + breakpoint implementation is broken.
1328                  * TEMPORARY! NOT DOCUMENTED! */
1329                 .name = "hardware_step",
1330                 .handler = &arm11_handle_bool_hardware_step,
1331                 .mode = COMMAND_ANY,
1332                 .help = "DEBUG ONLY - Hardware single stepping"
1333                         " (default: disabled)",
1334                 .usage = "(enable|disable)",
1335         },
1336         {
1337                 .name = "memwrite",
1338                 .mode = COMMAND_ANY,
1339                 .help = "memwrite command group",
1340                 .chain = arm11_mw_command_handlers,
1341         },
1342         {
1343                 .name = "step_irq_enable",
1344                 .handler = &arm11_handle_bool_step_irq_enable,
1345                 .mode = COMMAND_ANY,
1346                 .help = "Enable interrupts while stepping"
1347                         " (default: disabled)",
1348         },
1349         {
1350                 .name = "vcr",
1351                 .handler = &arm11_handle_vcr,
1352                 .mode = COMMAND_ANY,
1353                 .help = "Control (Interrupt) Vector Catch Register",
1354         },
1355         COMMAND_REGISTRATION_DONE
1356 };
1357 static const struct command_registration arm11_command_handlers[] = {
1358         {
1359                 .chain = arm_command_handlers,
1360         },
1361         {
1362                 .chain = etm_command_handlers,
1363         },
1364         {
1365                 .name = "arm11",
1366                 .mode = COMMAND_ANY,
1367                 .help = "ARM11 command group",
1368                 .chain = arm11_any_command_handlers,
1369         },
1370         COMMAND_REGISTRATION_DONE
1371 };
1372
1373 /** Holds methods for ARM11xx targets. */
1374 struct target_type arm11_target = {
1375         .name =                 "arm11",
1376
1377         .poll =                 arm11_poll,
1378         .arch_state =           arm11_arch_state,
1379
1380         .target_request_data =  arm11_target_request_data,
1381
1382         .halt =                 arm11_halt,
1383         .resume =               arm11_resume,
1384         .step =                 arm11_step,
1385
1386         .assert_reset =         arm11_assert_reset,
1387         .deassert_reset =       arm11_deassert_reset,
1388         .soft_reset_halt =      arm11_soft_reset_halt,
1389
1390         .get_gdb_reg_list =     armv4_5_get_gdb_reg_list,
1391
1392         .read_memory =          arm11_read_memory,
1393         .write_memory =         arm11_write_memory,
1394
1395         .bulk_write_memory =    arm11_bulk_write_memory,
1396
1397         .checksum_memory =      arm_checksum_memory,
1398         .blank_check_memory =   arm_blank_check_memory,
1399
1400         .add_breakpoint =       arm11_add_breakpoint,
1401         .remove_breakpoint =    arm11_remove_breakpoint,
1402
1403         .run_algorithm =        armv4_5_run_algorithm,
1404
1405         .commands =             arm11_command_handlers,
1406         .target_create =        arm11_target_create,
1407         .init_target =          arm11_init_target,
1408         .examine =              arm11_examine,
1409 };