1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
31 #include "arm_simulator.h"
32 #include "time_support.h"
33 #include "target_type.h"
37 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #define FNC_INFO LOG_DEBUG("-")
47 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
49 #define FNC_INFO_NOTIMPLEMENTED
52 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
54 bool arm11_config_memwrite_burst = true;
55 bool arm11_config_memwrite_error_fatal = true;
56 uint32_t arm11_vcr = 0;
57 bool arm11_config_memrw_no_increment = false;
58 bool arm11_config_step_irq_enable = false;
59 bool arm11_config_hardware_step = false;
61 #define ARM11_HANDLER(x) \
64 target_type_t arm11_target =
69 ARM11_HANDLER(arch_state),
71 ARM11_HANDLER(target_request_data),
74 ARM11_HANDLER(resume),
77 ARM11_HANDLER(assert_reset),
78 ARM11_HANDLER(deassert_reset),
79 ARM11_HANDLER(soft_reset_halt),
81 ARM11_HANDLER(get_gdb_reg_list),
83 ARM11_HANDLER(read_memory),
84 ARM11_HANDLER(write_memory),
86 ARM11_HANDLER(bulk_write_memory),
88 ARM11_HANDLER(checksum_memory),
90 ARM11_HANDLER(add_breakpoint),
91 ARM11_HANDLER(remove_breakpoint),
92 ARM11_HANDLER(add_watchpoint),
93 ARM11_HANDLER(remove_watchpoint),
95 ARM11_HANDLER(run_algorithm),
97 ARM11_HANDLER(register_commands),
98 ARM11_HANDLER(target_create),
99 ARM11_HANDLER(init_target),
100 ARM11_HANDLER(examine),
104 int arm11_regs_arch_type = -1;
122 ARM11_REGISTER_SPSR_FIQ,
123 ARM11_REGISTER_SPSR_SVC,
124 ARM11_REGISTER_SPSR_ABT,
125 ARM11_REGISTER_SPSR_IRQ,
126 ARM11_REGISTER_SPSR_UND,
127 ARM11_REGISTER_SPSR_MON,
136 typedef struct arm11_reg_defs_s
141 enum arm11_regtype type;
144 /* update arm11_regcache_ids when changing this */
145 static const arm11_reg_defs_t arm11_reg_defs[] =
147 {"r0", 0, 0, ARM11_REGISTER_CORE},
148 {"r1", 1, 1, ARM11_REGISTER_CORE},
149 {"r2", 2, 2, ARM11_REGISTER_CORE},
150 {"r3", 3, 3, ARM11_REGISTER_CORE},
151 {"r4", 4, 4, ARM11_REGISTER_CORE},
152 {"r5", 5, 5, ARM11_REGISTER_CORE},
153 {"r6", 6, 6, ARM11_REGISTER_CORE},
154 {"r7", 7, 7, ARM11_REGISTER_CORE},
155 {"r8", 8, 8, ARM11_REGISTER_CORE},
156 {"r9", 9, 9, ARM11_REGISTER_CORE},
157 {"r10", 10, 10, ARM11_REGISTER_CORE},
158 {"r11", 11, 11, ARM11_REGISTER_CORE},
159 {"r12", 12, 12, ARM11_REGISTER_CORE},
160 {"sp", 13, 13, ARM11_REGISTER_CORE},
161 {"lr", 14, 14, ARM11_REGISTER_CORE},
162 {"pc", 15, 15, ARM11_REGISTER_CORE},
164 #if ARM11_REGCACHE_FREGS
165 {"f0", 0, 16, ARM11_REGISTER_FX},
166 {"f1", 1, 17, ARM11_REGISTER_FX},
167 {"f2", 2, 18, ARM11_REGISTER_FX},
168 {"f3", 3, 19, ARM11_REGISTER_FX},
169 {"f4", 4, 20, ARM11_REGISTER_FX},
170 {"f5", 5, 21, ARM11_REGISTER_FX},
171 {"f6", 6, 22, ARM11_REGISTER_FX},
172 {"f7", 7, 23, ARM11_REGISTER_FX},
173 {"fps", 0, 24, ARM11_REGISTER_FPS},
176 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
178 #if ARM11_REGCACHE_MODEREGS
179 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
180 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
181 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
182 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
183 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
184 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
185 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
186 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
188 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
189 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
190 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
192 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
193 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
194 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
196 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
197 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
198 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
200 {"r13_und", 13, -1, ARM11_REGISTER_UND},
201 {"r14_und", 14, -1, ARM11_REGISTER_UND},
202 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
205 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
206 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
207 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
210 /* Debug Registers */
211 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
212 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
213 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
216 enum arm11_regcache_ids
219 ARM11_RC_RX = ARM11_RC_R0,
234 ARM11_RC_SP = ARM11_RC_R13,
236 ARM11_RC_LR = ARM11_RC_R14,
238 ARM11_RC_PC = ARM11_RC_R15,
240 #if ARM11_REGCACHE_FREGS
242 ARM11_RC_FX = ARM11_RC_F0,
255 #if ARM11_REGCACHE_MODEREGS
293 #define ARM11_GDB_REGISTER_COUNT 26
295 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
297 reg_t arm11_gdb_dummy_fp_reg =
299 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
302 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
304 reg_t arm11_gdb_dummy_fps_reg =
306 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
311 /** Check and if necessary take control of the system
313 * \param arm11 Target state variable.
314 * \param dscr If the current DSCR content is
315 * available a pointer to a word holding the
316 * DSCR can be passed. Otherwise use NULL.
318 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
322 uint32_t dscr_local_tmp_copy;
326 dscr = &dscr_local_tmp_copy;
328 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
331 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
333 LOG_DEBUG("Bringing target into debug mode");
335 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
336 arm11_write_DSCR(arm11, *dscr);
338 /* add further reset initialization here */
340 arm11->simulate_reset_on_next_halt = true;
342 if (*dscr & ARM11_DSCR_CORE_HALTED)
344 /** \todo TODO: this needs further scrutiny because
345 * arm11_on_enter_debug_state() never gets properly called.
346 * As a result we don't read the actual register states from
350 arm11->target->state = TARGET_HALTED;
351 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
355 arm11->target->state = TARGET_RUNNING;
356 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
359 arm11_sc7_clear_vbw(arm11);
368 (arm11->reg_values[ARM11_RC_##x])
370 /** Save processor state.
372 * This is called when the HALT instruction has succeeded
373 * or on other occasions that stop the processor.
376 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
381 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
383 arm11->reg_list[i].valid = 1;
384 arm11->reg_list[i].dirty = 0;
388 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
392 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
394 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
396 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
398 scan_field_t chain5_fields[3];
400 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
401 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
402 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
404 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
408 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
412 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
413 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
414 ARM1136 seems to require this to issue ITR's as well */
416 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
418 /* this executes JTAG queue: */
420 arm11_write_DSCR(arm11, new_dscr);
424 Before executing any instruction in debug state you have to drain the write buffer.
425 This ensures that no imprecise Data Aborts can return at a later point:*/
427 /** \todo TODO: Test drain write buffer. */
432 /* MRC p14,0,R0,c5,c10,0 */
433 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
435 /* mcr 15, 0, r0, cr7, cr10, {4} */
436 arm11_run_instr_no_data1(arm11, 0xee070f9a);
438 uint32_t dscr = arm11_read_DSCR(arm11);
440 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
442 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
444 arm11_run_instr_no_data1(arm11, 0xe320f000);
446 dscr = arm11_read_DSCR(arm11);
448 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
455 arm11_run_instr_data_prepare(arm11);
459 /** \todo TODO: handle other mode registers */
461 for (size_t i = 0; i < 15; i++)
463 /* MCR p14,0,R?,c0,c5,0 */
464 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
465 if (retval != ERROR_OK)
471 /* check rDTRfull in DSCR */
473 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
475 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
476 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
480 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
485 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
486 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
490 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
491 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
492 if (retval != ERROR_OK)
495 /* adjust PC depending on ARM state */
497 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
499 arm11->reg_values[ARM11_RC_PC] -= 0;
501 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
503 arm11->reg_values[ARM11_RC_PC] -= 4;
507 arm11->reg_values[ARM11_RC_PC] -= 8;
510 if (arm11->simulate_reset_on_next_halt)
512 arm11->simulate_reset_on_next_halt = false;
514 LOG_DEBUG("Reset c1 Control Register");
516 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
518 /* MCR p15,0,R0,c1,c0,0 */
519 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
523 arm11_run_instr_data_finish(arm11);
525 arm11_dump_reg_changes(arm11);
530 void arm11_dump_reg_changes(arm11_common_t * arm11)
533 if (!(debug_level >= LOG_LVL_DEBUG))
538 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
540 if (!arm11->reg_list[i].valid)
542 if (arm11->reg_history[i].valid)
543 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
547 if (arm11->reg_history[i].valid)
549 if (arm11->reg_history[i].value != arm11->reg_values[i])
550 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
554 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
560 /** Restore processor state
562 * This is called in preparation for the RESTART function.
565 int arm11_leave_debug_state(arm11_common_t * arm11)
569 arm11_run_instr_data_prepare(arm11);
571 /** \todo TODO: handle other mode registers */
573 /* restore R1 - R14 */
575 for (size_t i = 1; i < 15; i++)
577 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
580 /* MRC p14,0,r?,c0,c5,0 */
581 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
583 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
586 arm11_run_instr_data_finish(arm11);
588 /* spec says clear wDTR and rDTR; we assume they are clear as
589 otherwise our programming would be sloppy */
593 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
595 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
597 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
601 arm11_run_instr_data_prepare(arm11);
603 /* restore original wDTR */
605 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
607 /* MCR p14,0,R0,c0,c5,0 */
608 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
614 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
619 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
623 /* MRC p14,0,r0,c0,c5,0 */
624 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
626 arm11_run_instr_data_finish(arm11);
630 arm11_write_DSCR(arm11, R(DSCR));
634 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
636 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
638 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
640 scan_field_t chain5_fields[3];
642 uint8_t Ready = 0; /* ignored */
643 uint8_t Valid = 0; /* ignored */
645 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
646 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
647 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
649 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
652 arm11_record_register_history(arm11);
657 void arm11_record_register_history(arm11_common_t * arm11)
659 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
661 arm11->reg_history[i].value = arm11->reg_values[i];
662 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
664 arm11->reg_list[i].valid = 0;
665 arm11->reg_list[i].dirty = 0;
670 /* poll current target status */
671 int arm11_poll(struct target_s *target)
676 arm11_common_t * arm11 = target->arch_info;
678 if (arm11->trst_active)
683 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
685 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
687 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
689 if (dscr & ARM11_DSCR_CORE_HALTED)
691 if (target->state != TARGET_HALTED)
693 enum target_state old_state = target->state;
695 LOG_DEBUG("enter TARGET_HALTED");
696 target->state = TARGET_HALTED;
697 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
698 retval = arm11_on_enter_debug_state(arm11);
699 if (retval != ERROR_OK)
702 target_call_event_callbacks(target,
703 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
708 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
710 LOG_DEBUG("enter TARGET_RUNNING");
711 target->state = TARGET_RUNNING;
712 target->debug_reason = DBG_REASON_NOTHALTED;
718 /* architecture specific status reply */
719 int arm11_arch_state(struct target_s *target)
721 arm11_common_t * arm11 = target->arch_info;
723 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
724 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
731 /* target request support */
732 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
734 FNC_INFO_NOTIMPLEMENTED;
739 /* target execution control */
740 int arm11_halt(struct target_s *target)
744 arm11_common_t * arm11 = target->arch_info;
746 LOG_DEBUG("target->state: %s",
747 target_state_name(target));
749 if (target->state == TARGET_UNKNOWN)
751 arm11->simulate_reset_on_next_halt = true;
754 if (target->state == TARGET_HALTED)
756 LOG_DEBUG("target was already halted");
760 if (arm11->trst_active)
762 arm11->halt_requested = true;
766 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
768 CHECK_RETVAL(jtag_execute_queue());
775 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
777 if (dscr & ARM11_DSCR_CORE_HALTED)
788 if ((timeval_ms()-then) > 1000)
790 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
797 arm11_on_enter_debug_state(arm11);
799 enum target_state old_state = target->state;
801 target->state = TARGET_HALTED;
802 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
805 target_call_event_callbacks(target,
806 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
811 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
815 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
816 // current, address, handle_breakpoints, debug_execution);
818 arm11_common_t * arm11 = target->arch_info;
820 LOG_DEBUG("target->state: %s",
821 target_state_name(target));
824 if (target->state != TARGET_HALTED)
826 LOG_ERROR("Target not halted");
827 return ERROR_TARGET_NOT_HALTED;
833 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
835 /* clear breakpoints/watchpoints and VCR*/
836 arm11_sc7_clear_vbw(arm11);
838 /* Set up breakpoints */
839 if (!debug_execution)
841 /* check if one matches PC and step over it if necessary */
845 for (bp = target->breakpoints; bp; bp = bp->next)
847 if (bp->address == R(PC))
849 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
850 arm11_step(target, 1, 0, 0);
855 /* set all breakpoints */
859 for (bp = target->breakpoints; bp; bp = bp->next)
861 arm11_sc7_action_t brp[2];
864 brp[0].address = ARM11_SC7_BVR0 + brp_num;
865 brp[0].value = bp->address;
867 brp[1].address = ARM11_SC7_BCR0 + brp_num;
868 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
870 arm11_sc7_run(arm11, brp, asizeof(brp));
872 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
877 arm11_sc7_set_vcr(arm11, arm11_vcr);
880 arm11_leave_debug_state(arm11);
882 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
884 CHECK_RETVAL(jtag_execute_queue());
891 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
893 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
895 if (dscr & ARM11_DSCR_CORE_RESTARTED)
906 if ((timeval_ms()-then) > 1000)
908 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
915 if (!debug_execution)
917 target->state = TARGET_RUNNING;
918 target->debug_reason = DBG_REASON_NOTHALTED;
920 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
924 target->state = TARGET_DEBUG_RUNNING;
925 target->debug_reason = DBG_REASON_NOTHALTED;
927 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
934 static int armv4_5_to_arm11(int reg)
941 return ARM11_RC_CPSR;
943 /* FIX!!! handle thumb better! */
944 return ARM11_RC_CPSR;
946 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
952 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
954 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
956 reg=armv4_5_to_arm11(reg);
958 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
961 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
963 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
965 reg=armv4_5_to_arm11(reg);
967 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
970 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
972 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
974 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
977 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
979 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
981 /* FIX!!!! we should implement thumb for arm11 */
982 return ARMV4_5_STATE_ARM;
985 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
987 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
989 /* FIX!!!! we should implement thumb for arm11 */
990 LOG_ERROR("Not implemetned!");
994 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
996 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
998 /* FIX!!!! we should implement something that returns the current mode here!!! */
999 return ARMV4_5_MODE_USR;
1002 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
1004 struct arm_sim_interface sim;
1006 sim.user_data=target->arch_info;
1007 sim.get_reg=&arm11_sim_get_reg;
1008 sim.set_reg=&arm11_sim_set_reg;
1009 sim.get_reg_mode=&arm11_sim_get_reg;
1010 sim.set_reg_mode=&arm11_sim_set_reg;
1011 sim.get_cpsr=&arm11_sim_get_cpsr;
1012 sim.get_mode=&arm11_sim_get_mode;
1013 sim.get_state=&arm11_sim_get_state;
1014 sim.set_state=&arm11_sim_set_state;
1016 return arm_simulate_step_core(target, dry_run_pc, &sim);
1020 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
1024 LOG_DEBUG("target->state: %s",
1025 target_state_name(target));
1027 if (target->state != TARGET_HALTED)
1029 LOG_WARNING("target was not halted");
1030 return ERROR_TARGET_NOT_HALTED;
1033 arm11_common_t * arm11 = target->arch_info;
1038 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1041 /** \todo TODO: Thumb not supported here */
1043 uint32_t next_instruction;
1045 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1047 /* skip over BKPT */
1048 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1051 arm11->reg_list[ARM11_RC_PC].valid = 1;
1052 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1053 LOG_DEBUG("Skipping BKPT");
1055 /* skip over Wait for interrupt / Standby */
1056 /* mcr 15, 0, r?, cr7, cr0, {4} */
1057 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1060 arm11->reg_list[ARM11_RC_PC].valid = 1;
1061 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1062 LOG_DEBUG("Skipping WFI");
1064 /* ignore B to self */
1065 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1067 LOG_DEBUG("Not stepping jump to self");
1071 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1074 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1075 * the VCR might be something worth looking into. */
1078 /* Set up breakpoint for stepping */
1080 arm11_sc7_action_t brp[2];
1083 brp[0].address = ARM11_SC7_BVR0;
1085 brp[1].address = ARM11_SC7_BCR0;
1087 if (arm11_config_hardware_step)
1089 /* hardware single stepping be used if possible or is it better to
1090 * always use the same code path? Hardware single stepping is not supported
1093 brp[0].value = R(PC);
1094 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1097 /* sets a breakpoint on the next PC(calculated by simulation),
1101 retval = arm11_simulate_step(target, &next_pc);
1102 if (retval != ERROR_OK)
1105 brp[0].value = next_pc;
1106 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1109 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1114 if (arm11_config_step_irq_enable)
1115 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1117 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1120 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1122 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1124 CHECK_RETVAL(jtag_execute_queue());
1132 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1134 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1136 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1137 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1143 then = timeval_ms();
1147 if ((timeval_ms()-then) > 1000)
1149 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1156 /* clear breakpoint */
1157 arm11_sc7_clear_vbw(arm11);
1160 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1162 /* restore default state */
1163 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1167 // target->state = TARGET_HALTED;
1168 target->debug_reason = DBG_REASON_SINGLESTEP;
1170 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1175 /* target reset control */
1176 int arm11_assert_reset(struct target_s *target)
1181 /* assert reset lines */
1182 /* resets only the DBGTAP, not the ARM */
1184 jtag_add_reset(1, 0);
1185 jtag_add_sleep(5000);
1187 arm11_common_t * arm11 = target->arch_info;
1188 arm11->trst_active = true;
1191 if (target->reset_halt)
1193 CHECK_RETVAL(target_halt(target));
1199 int arm11_deassert_reset(struct target_s *target)
1204 LOG_DEBUG("target->state: %s",
1205 target_state_name(target));
1208 /* deassert reset lines */
1209 jtag_add_reset(0, 0);
1211 arm11_common_t * arm11 = target->arch_info;
1212 arm11->trst_active = false;
1214 if (arm11->halt_requested)
1215 return arm11_halt(target);
1221 int arm11_soft_reset_halt(struct target_s *target)
1223 FNC_INFO_NOTIMPLEMENTED;
1228 /* target register access for gdb */
1229 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1233 arm11_common_t * arm11 = target->arch_info;
1235 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1236 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1238 for (size_t i = 16; i < 24; i++)
1240 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1243 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1245 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1247 if (arm11_reg_defs[i].gdb_num == -1)
1250 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1256 /* target memory access
1257 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1258 * count: number of items of <size>
1260 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1262 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1266 if (target->state != TARGET_HALTED)
1268 LOG_WARNING("target was not halted");
1269 return ERROR_TARGET_NOT_HALTED;
1272 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1274 arm11_common_t * arm11 = target->arch_info;
1276 arm11_run_instr_data_prepare(arm11);
1278 /* MRC p14,0,r0,c0,c5,0 */
1279 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1284 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1285 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1287 for (size_t i = 0; i < count; i++)
1289 /* ldrb r1, [r0], #1 */
1291 arm11_run_instr_no_data1(arm11,
1292 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1295 /* MCR p14,0,R1,c0,c5,0 */
1296 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1305 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1307 for (size_t i = 0; i < count; i++)
1309 /* ldrh r1, [r0], #2 */
1310 arm11_run_instr_no_data1(arm11,
1311 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1315 /* MCR p14,0,R1,c0,c5,0 */
1316 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1318 uint16_t svalue = res;
1319 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1327 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1328 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1329 uint32_t *words = (uint32_t *)buffer;
1331 /* LDC p14,c5,[R0],#4 */
1332 /* LDC p14,c5,[R0] */
1333 arm11_run_instr_data_from_core(arm11, instr, words, count);
1338 arm11_run_instr_data_finish(arm11);
1343 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1347 if (target->state != TARGET_HALTED)
1349 LOG_WARNING("target was not halted");
1350 return ERROR_TARGET_NOT_HALTED;
1353 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1355 arm11_common_t * arm11 = target->arch_info;
1357 arm11_run_instr_data_prepare(arm11);
1359 /* MRC p14,0,r0,c0,c5,0 */
1360 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1366 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1368 for (size_t i = 0; i < count; i++)
1370 /* MRC p14,0,r1,c0,c5,0 */
1371 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1373 /* strb r1, [r0], #1 */
1375 arm11_run_instr_no_data1(arm11,
1376 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1384 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1386 for (size_t i = 0; i < count; i++)
1389 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1391 /* MRC p14,0,r1,c0,c5,0 */
1392 arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1394 /* strh r1, [r0], #2 */
1396 arm11_run_instr_no_data1(arm11,
1397 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1404 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1406 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1407 uint32_t *words = (uint32_t*)buffer;
1409 if (!arm11_config_memwrite_burst)
1411 /* STC p14,c5,[R0],#4 */
1412 /* STC p14,c5,[R0]*/
1413 arm11_run_instr_data_to_core(arm11, instr, words, count);
1417 /* STC p14,c5,[R0],#4 */
1418 /* STC p14,c5,[R0]*/
1419 arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1427 /* r0 verification */
1428 if (!arm11_config_memrw_no_increment)
1432 /* MCR p14,0,R0,c0,c5,0 */
1433 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1435 if (address + size * count != r0)
1437 LOG_ERROR("Data transfer failed. Expected end address 0x%08x, got 0x%08x",
1438 address + size * count, r0);
1440 if (arm11_config_memwrite_burst)
1441 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1443 if (arm11_config_memwrite_error_fatal)
1449 arm11_run_instr_data_finish(arm11);
1455 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1456 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1460 if (target->state != TARGET_HALTED)
1462 LOG_WARNING("target was not halted");
1463 return ERROR_TARGET_NOT_HALTED;
1466 return arm11_write_memory(target, address, 4, count, buffer);
1469 /* here we have nothing target specific to contribute, so we fail and then the
1470 * fallback code will read data from the target and calculate the CRC on the
1473 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1478 /* target break-/watchpoint control
1479 * rw: 0 = write, 1 = read, 2 = access
1481 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1485 arm11_common_t * arm11 = target->arch_info;
1488 if (breakpoint->type == BKPT_SOFT)
1490 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1491 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1495 if (!arm11->free_brps)
1497 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1498 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1501 if (breakpoint->length != 4)
1503 LOG_DEBUG("only breakpoints of four bytes length supported");
1504 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1512 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1516 arm11_common_t * arm11 = target->arch_info;
1523 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1525 FNC_INFO_NOTIMPLEMENTED;
1530 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1532 FNC_INFO_NOTIMPLEMENTED;
1537 // HACKHACKHACK - FIXME mode/state
1538 /* target algorithm support */
1539 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1540 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1541 int timeout_ms, void *arch_info)
1543 arm11_common_t *arm11 = target->arch_info;
1544 // enum armv4_5_state core_state = arm11->core_state;
1545 // enum armv4_5_mode core_mode = arm11->core_mode;
1546 uint32_t context[16];
1548 int exit_breakpoint_size = 0;
1549 int retval = ERROR_OK;
1550 LOG_DEBUG("Running algorithm");
1553 if (target->state != TARGET_HALTED)
1555 LOG_WARNING("target not halted");
1556 return ERROR_TARGET_NOT_HALTED;
1560 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1561 // return ERROR_FAIL;
1564 for (size_t i = 0; i < 16; i++)
1566 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1567 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1570 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1571 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1573 for (int i = 0; i < num_mem_params; i++)
1575 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1578 // Set register parameters
1579 for (int i = 0; i < num_reg_params; i++)
1581 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1584 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1588 if (reg->size != reg_params[i].size)
1590 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1593 arm11_set_reg(reg,reg_params[i].value);
1594 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1597 exit_breakpoint_size = 4;
1599 /* arm11->core_state = arm11_algorithm_info->core_state;
1600 if (arm11->core_state == ARMV4_5_STATE_ARM)
1601 exit_breakpoint_size = 4;
1602 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1603 exit_breakpoint_size = 2;
1606 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1612 /* arm11 at this point only supports ARM not THUMB mode
1613 however if this test needs to be reactivated the current state can be read back
1616 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1618 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1619 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1620 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1621 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1625 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1627 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1628 retval = ERROR_TARGET_FAILURE;
1632 // no debug, otherwise breakpoint is not set
1633 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1635 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1637 if (target->state != TARGET_HALTED)
1639 CHECK_RETVAL(target_halt(target));
1641 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1643 retval = ERROR_TARGET_TIMEOUT;
1645 goto del_breakpoint;
1648 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1650 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1651 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1652 retval = ERROR_TARGET_TIMEOUT;
1653 goto del_breakpoint;
1656 for (int i = 0; i < num_mem_params; i++)
1658 if (mem_params[i].direction != PARAM_OUT)
1659 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1662 for (int i = 0; i < num_reg_params; i++)
1664 if (reg_params[i].direction != PARAM_OUT)
1666 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1669 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1673 if (reg->size != reg_params[i].size)
1675 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1679 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1684 breakpoint_remove(target, exit_point);
1688 for (size_t i = 0; i < 16; i++)
1690 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1691 arm11->reg_list[i].name, context[i]);
1692 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1694 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1695 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1697 // arm11->core_state = core_state;
1698 // arm11->core_mode = core_mode;
1703 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1707 NEW(arm11_common_t, arm11, 1);
1709 arm11->target = target;
1711 if (target->tap == NULL)
1714 if (target->tap->ir_length != 5)
1716 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1717 return ERROR_COMMAND_SYNTAX_ERROR;
1720 target->arch_info = arm11;
1725 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1727 /* Initialize anything we can set up without talking to the target */
1728 return arm11_build_reg_cache(target);
1731 /* talk to the target and set things up */
1732 int arm11_examine(struct target_s *target)
1736 arm11_common_t * arm11 = target->arch_info;
1740 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1742 scan_field_t idcode_field;
1744 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1746 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1750 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1752 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1754 scan_field_t chain0_fields[2];
1756 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1757 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1759 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1761 CHECK_RETVAL(jtag_execute_queue());
1763 switch (arm11->device_id & 0x0FFFF000)
1765 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1766 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1767 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1770 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1775 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1777 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1778 arm11->debug_version != ARM11_DEBUG_V61)
1780 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1784 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1785 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1787 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1788 arm11->free_brps = arm11->brp;
1789 arm11->free_wrps = arm11->wrp;
1791 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1793 (int)(arm11->implementor),
1796 /* as a side-effect this reads DSCR and thus
1797 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1798 * as suggested by the spec.
1801 arm11_check_init(arm11, NULL);
1803 target_set_examined(target);
1808 int arm11_quit(void)
1810 FNC_INFO_NOTIMPLEMENTED;
1815 /** Load a register that is marked !valid in the register cache */
1816 int arm11_get_reg(reg_t *reg)
1820 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1822 if (target->state != TARGET_HALTED)
1824 LOG_WARNING("target was not halted");
1825 return ERROR_TARGET_NOT_HALTED;
1828 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1831 arm11_common_t *arm11 = target->arch_info;
1832 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1838 /** Change a value in the register cache */
1839 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1843 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1844 arm11_common_t *arm11 = target->arch_info;
1845 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1847 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1854 int arm11_build_reg_cache(target_t *target)
1856 arm11_common_t *arm11 = target->arch_info;
1858 NEW(reg_cache_t, cache, 1);
1859 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1860 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1862 if (arm11_regs_arch_type == -1)
1863 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1865 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1866 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1868 arm11->reg_list = reg_list;
1870 /* Build the process context cache */
1871 cache->name = "arm11 registers";
1873 cache->reg_list = reg_list;
1874 cache->num_regs = ARM11_REGCACHE_COUNT;
1876 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1879 arm11->core_cache = cache;
1880 // armv7m->process_context = cache;
1884 /* Not very elegant assertion */
1885 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1886 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1887 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1889 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1893 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1895 reg_t * r = reg_list + i;
1896 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1897 arm11_reg_state_t * rs = arm11_reg_states + i;
1901 r->value = (uint8_t *)(arm11->reg_values + i);
1904 r->bitfield_desc = NULL;
1905 r->num_bitfields = 0;
1906 r->arch_type = arm11_regs_arch_type;
1910 rs->target = target;
1916 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1920 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1925 return ERROR_COMMAND_SYNTAX_ERROR;
1930 case 'f': /* false */
1932 case 'd': /* disable */
1938 case 't': /* true */
1940 case 'e': /* enable */
1946 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1951 #define BOOL_WRAPPER(name, print_name) \
1952 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1954 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1957 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1958 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1959 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
1960 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1961 BOOL_WRAPPER(hardware_step, "hardware single step")
1963 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1967 arm11_vcr = strtoul(args[0], NULL, 0);
1971 return ERROR_COMMAND_SYNTAX_ERROR;
1974 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1978 const uint32_t arm11_coproc_instruction_limits[] =
1980 15, /* coprocessor */
1985 0xFFFFFFFF, /* value */
1988 arm11_common_t * arm11_find_target(const char * arg)
1993 tap = jtag_tap_by_string(arg);
1998 for (t = all_targets; t; t = t->next)
2003 /* if (t->type == arm11_target) */
2004 if (0 == strcmp(target_get_name(t), "arm11"))
2005 return t->arch_info;
2011 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
2013 if (argc != (read ? 6 : 7))
2015 LOG_ERROR("Invalid number of arguments.");
2016 return ERROR_COMMAND_SYNTAX_ERROR;
2019 arm11_common_t * arm11 = arm11_find_target(args[0]);
2023 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
2024 return ERROR_COMMAND_SYNTAX_ERROR;
2027 if (arm11->target->state != TARGET_HALTED)
2029 LOG_WARNING("target was not halted");
2030 return ERROR_TARGET_NOT_HALTED;
2035 for (size_t i = 0; i < (read ? 5 : 6); i++)
2037 values[i] = strtoul(args[i + 1], NULL, 0);
2039 if (values[i] > arm11_coproc_instruction_limits[i])
2041 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
2043 arm11_coproc_instruction_limits[i]);
2044 return ERROR_COMMAND_SYNTAX_ERROR;
2048 uint32_t instr = 0xEE000010 |
2056 instr |= 0x00100000;
2058 arm11_run_instr_data_prepare(arm11);
2063 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2065 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2070 (int)(values[4]), result, result);
2074 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2076 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2077 (int)(values[0]), (int)(values[1]),
2079 (int)(values[2]), (int)(values[3]), (int)(values[4]));
2082 arm11_run_instr_data_finish(arm11);
2088 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2090 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2093 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2095 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2098 int arm11_register_commands(struct command_context_s *cmd_ctx)
2102 command_t *top_cmd, *mw_cmd;
2104 top_cmd = register_command(cmd_ctx, NULL, "arm11",
2105 NULL, COMMAND_ANY, NULL);
2107 /* "hardware_step" is only here to check if the default
2108 * simulate + breakpoint implementation is broken.
2109 * TEMPORARY! NOT DOCUMENTED!
2111 register_command(cmd_ctx, top_cmd, "hardware_step",
2112 arm11_handle_bool_hardware_step, COMMAND_ANY,
2113 "DEBUG ONLY - Hardware single stepping"
2114 " (default: disabled)");
2116 register_command(cmd_ctx, top_cmd, "mcr",
2117 arm11_handle_mcr, COMMAND_ANY,
2118 "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
2120 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2121 NULL, COMMAND_ANY, NULL);
2122 register_command(cmd_ctx, mw_cmd, "burst",
2123 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2124 "Enable/Disable non-standard but fast burst mode"
2125 " (default: enabled)");
2126 register_command(cmd_ctx, mw_cmd, "error_fatal",
2127 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2128 "Terminate program if transfer error was found"
2129 " (default: enabled)");
2131 register_command(cmd_ctx, top_cmd, "mrc",
2132 arm11_handle_mrc, COMMAND_ANY,
2133 "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
2134 register_command(cmd_ctx, top_cmd, "no_increment",
2135 arm11_handle_bool_memrw_no_increment, COMMAND_ANY,
2136 "Don't increment address on multi-read/-write"
2137 " (default: disabled)");
2138 register_command(cmd_ctx, top_cmd, "step_irq_enable",
2139 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2140 "Enable interrupts while stepping"
2141 " (default: disabled)");
2142 register_command(cmd_ctx, top_cmd, "vcr",
2143 arm11_handle_vcr, COMMAND_ANY,
2144 "Control (Interrupt) Vector Catch Register");