git.gag.com Git - fw/openocd/blob - src/target/arm11.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "etm.h"
  30 #include "breakpoints.h"
  31 #include "arm11_dbgtap.h"
  32 #include "arm_simulator.h"
  33 #include "time_support.h"
  34 #include "target_type.h"
  35 #include "algorithm.h"
  36 #include "register.h"
  37
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 static bool arm11_config_memwrite_burst = true;
  44 static bool arm11_config_memwrite_error_fatal = true;
  45 static uint32_t arm11_vcr = 0;
  46 static bool arm11_config_step_irq_enable = false;
  47 static bool arm11_config_hardware_step = false;
  48
  49 enum arm11_regtype
  50 {
  51         /* debug regs */
  52         ARM11_REGISTER_DSCR,
  53         ARM11_REGISTER_WDTR,
  54 };
  55
  56
  57 struct arm11_reg_defs
  58 {
  59         char *                                  name;
  60         uint32_t                                                num;
  61         int                                             gdb_num;
  62         enum arm11_regtype              type;
  63 };
  64
  65 /* update arm11_regcache_ids when changing this */
  66 static const struct arm11_reg_defs arm11_reg_defs[] =
  67 {
  68         /* Debug Registers */
  69         {"dscr",        0,      -1,     ARM11_REGISTER_DSCR},
  70         {"wdtr",        0,      -1,     ARM11_REGISTER_WDTR},
  71 };
  72
  73 enum arm11_regcache_ids
  74 {
  75         ARM11_RC_DSCR,
  76         ARM11_RC_WDTR,
  77
  78         ARM11_RC_MAX,
  79 };
  80
  81 static int arm11_step(struct target *target, int current,
  82                 uint32_t address, int handle_breakpoints);
  83 /* helpers */
  84 static int arm11_build_reg_cache(struct target *target);
  85 static int arm11_set_reg(struct reg *reg, uint8_t *buf);
  86 static int arm11_get_reg(struct reg *reg);
  87
  88
  89 /** Check and if necessary take control of the system
  90  *
  91  * \param arm11         Target state variable.
  92  * \param dscr          If the current DSCR content is
  93  *                                      available a pointer to a word holding the
  94  *                                      DSCR can be passed. Otherwise use NULL.
  95  */
  96 static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
  97 {
  98         uint32_t                        dscr_local_tmp_copy;
  99
 100         if (!dscr)
 101         {
 102                 dscr = &dscr_local_tmp_copy;
 103
 104                 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
 105         }
 106
 107         if (!(*dscr & ARM11_DSCR_MODE_SELECT))
 108         {
 109                 LOG_DEBUG("Bringing target into debug mode");
 110
 111                 *dscr |= ARM11_DSCR_MODE_SELECT;                /* Halt debug-mode */
 112                 arm11_write_DSCR(arm11, *dscr);
 113
 114                 /* add further reset initialization here */
 115
 116                 arm11->simulate_reset_on_next_halt = true;
 117
 118                 if (*dscr & ARM11_DSCR_CORE_HALTED)
 119                 {
 120                         /** \todo TODO: this needs further scrutiny because
 121                           * arm11_debug_entry() never gets called.  (WHY NOT?)
 122                           * As a result we don't read the actual register states from
 123                           * the target.
 124                           */
 125
 126                         arm11->arm.target->state = TARGET_HALTED;
 127                         arm11->arm.target->debug_reason =
 128                                         arm11_get_DSCR_debug_reason(*dscr);
 129                 }
 130                 else
 131                 {
 132                         arm11->arm.target->state = TARGET_RUNNING;
 133                         arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
 134                 }
 135
 136                 arm11_sc7_clear_vbw(arm11);
 137         }
 138
 139         return ERROR_OK;
 140 }
 141
 142
 143
 144 #define R(x) \
 145         (arm11->reg_values[ARM11_RC_##x])
 146
 147 /**
 148  * Save processor state.  This is called after a HALT instruction
 149  * succeeds, and on other occasions the processor enters debug mode
 150  * (breakpoint, watchpoint, etc).
 151  */
 152 static int arm11_debug_entry(struct arm11_common *arm11, uint32_t dscr)
 153 {
 154         int retval;
 155
 156         arm11->arm.target->state = TARGET_HALTED;
 157         arm11->arm.target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
 158
 159         /* REVISIT entire cache should already be invalid !!! */
 160         register_cache_invalidate(arm11->arm.core_cache);
 161
 162         for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
 163         {
 164                 arm11->reg_list[i].valid        = 1;
 165                 arm11->reg_list[i].dirty        = 0;
 166         }
 167
 168         /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
 169
 170         /* Save DSCR */
 171         R(DSCR) = dscr;
 172
 173         /* Save wDTR */
 174
 175         if (dscr & ARM11_DSCR_WDTR_FULL)
 176         {
 177                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 178
 179                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 180
 181                 struct scan_field       chain5_fields[3];
 182
 183                 arm11_setup_field(arm11, 32, NULL, &R(WDTR),    chain5_fields + 0);
 184                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
 185                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
 186
 187                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 188         }
 189         else
 190         {
 191                 arm11->reg_list[ARM11_RC_WDTR].valid    = 0;
 192         }
 193
 194
 195         /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
 196          *
 197          * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
 198          * but not to issue ITRs. ARM1136 seems to require this to issue
 199          * ITR's as well...
 200          */
 201         uint32_t new_dscr = dscr | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
 202
 203         /* this executes JTAG queue: */
 204
 205         arm11_write_DSCR(arm11, new_dscr);
 206
 207
 208         /* From the spec:
 209            Before executing any instruction in debug state you have to drain the write buffer.
 210            This ensures that no imprecise Data Aborts can return at a later point:*/
 211
 212         /** \todo TODO: Test drain write buffer. */
 213
 214 #if 0
 215         while (1)
 216         {
 217                 /* MRC p14,0,R0,c5,c10,0 */
 218                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 219
 220                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 221                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 222
 223                 uint32_t dscr = arm11_read_DSCR(arm11);
 224
 225                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 226
 227                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 228                 {
 229                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 230
 231                         dscr = arm11_read_DSCR(arm11);
 232
 233                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 234
 235                         break;
 236                 }
 237         }
 238 #endif
 239
 240         /* Save registers.
 241          *
 242          * NOTE:  ARM1136 TRM suggests saving just R0 here now, then
 243          * CPSR and PC after the rDTR stuff.  We do it all at once.
 244          */
 245         retval = arm_dpm_read_current_registers(&arm11->dpm);
 246         if (retval != ERROR_OK)
 247                 LOG_ERROR("DPM REG READ -- fail %d", retval);
 248
 249         retval = arm11_run_instr_data_prepare(arm11);
 250         if (retval != ERROR_OK)
 251                 return retval;
 252
 253         /* maybe save rDTR */
 254         arm11->is_rdtr_saved = !!(dscr & ARM11_DSCR_RDTR_FULL);
 255         if (arm11->is_rdtr_saved)
 256         {
 257                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 258                 retval = arm11_run_instr_data_from_core_via_r0(arm11,
 259                                 0xEE100E15, &arm11->saved_rdtr);
 260                 if (retval != ERROR_OK)
 261                         return retval;
 262         }
 263
 264         /* REVISIT Now that we've saved core state, there's may also
 265          * be MMU and cache state to care about ...
 266          */
 267
 268         if (arm11->simulate_reset_on_next_halt)
 269         {
 270                 arm11->simulate_reset_on_next_halt = false;
 271
 272                 LOG_DEBUG("Reset c1 Control Register");
 273
 274                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 275
 276                 /* MCR p15,0,R0,c1,c0,0 */
 277                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 278                 if (retval != ERROR_OK)
 279                         return retval;
 280
 281         }
 282
 283         retval = arm11_run_instr_data_finish(arm11);
 284         if (retval != ERROR_OK)
 285                 return retval;
 286
 287         return ERROR_OK;
 288 }
 289
 290 /**
 291  * Restore processor state.  This is called in preparation for
 292  * the RESTART function.
 293  */
 294 static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 295 {
 296         int retval;
 297
 298         /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
 299
 300         /* NOTE:  the ARM1136 TRM suggests restoring all registers
 301          * except R0/PC/CPSR right now.  Instead, we do them all
 302          * at once, just a bit later on.
 303          */
 304
 305         /* REVISIT once we start caring about MMU and cache state,
 306          * address it here ...
 307          */
 308
 309         /* spec says clear wDTR and rDTR; we assume they are clear as
 310            otherwise our programming would be sloppy */
 311         {
 312                 uint32_t DSCR;
 313
 314                 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
 315
 316                 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 317                 {
 318                         /*
 319                         The wDTR/rDTR two registers that are used to send/receive data to/from
 320                         the core in tandem with corresponding instruction codes that are
 321                         written into the core. The RDTR FULL/WDTR FULL flag indicates that the
 322                         registers hold data that was written by one side (CPU or JTAG) and not
 323                         read out by the other side.
 324                         */
 325                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 326                         return ERROR_FAIL;
 327                 }
 328         }
 329
 330         /* maybe restore original wDTR */
 331         if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
 332         {
 333                 retval = arm11_run_instr_data_prepare(arm11);
 334                 if (retval != ERROR_OK)
 335                         return retval;
 336
 337                 /* MCR p14,0,R0,c0,c5,0 */
 338                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
 339                 if (retval != ERROR_OK)
 340                         return retval;
 341
 342                 retval = arm11_run_instr_data_finish(arm11);
 343                 if (retval != ERROR_OK)
 344                         return retval;
 345         }
 346
 347         /* restore CPSR, PC, and R0 ... after flushing any modified
 348          * registers.
 349          */
 350         retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
 351
 352         register_cache_invalidate(arm11->arm.core_cache);
 353
 354         /* restore DSCR */
 355
 356         arm11_write_DSCR(arm11, R(DSCR));
 357
 358         /* maybe restore rDTR */
 359
 360         if (arm11->is_rdtr_saved)
 361         {
 362                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 363
 364                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 365
 366                 struct scan_field       chain5_fields[3];
 367
 368                 uint8_t                 Ready           = 0;    /* ignored */
 369                 uint8_t                 Valid           = 0;    /* ignored */
 370
 371                 arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
 372                                 NULL, chain5_fields + 0);
 373                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 374                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 375
 376                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 377         }
 378
 379         /* now processor is ready to RESTART */
 380
 381         return ERROR_OK;
 382 }
 383
 384 /* poll current target status */
 385 static int arm11_poll(struct target *target)
 386 {
 387         int retval;
 388         struct arm11_common *arm11 = target_to_arm11(target);
 389         uint32_t        dscr;
 390
 391         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 392
 393         LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 394
 395         CHECK_RETVAL(arm11_check_init(arm11, &dscr));
 396
 397         if (dscr & ARM11_DSCR_CORE_HALTED)
 398         {
 399                 if (target->state != TARGET_HALTED)
 400                 {
 401                         enum target_state old_state = target->state;
 402
 403                         LOG_DEBUG("enter TARGET_HALTED");
 404                         retval = arm11_debug_entry(arm11, dscr);
 405                         if (retval != ERROR_OK)
 406                                 return retval;
 407
 408                         target_call_event_callbacks(target,
 409                                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
 410                 }
 411         }
 412         else
 413         {
 414                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 415                 {
 416                         LOG_DEBUG("enter TARGET_RUNNING");
 417                         target->state                   = TARGET_RUNNING;
 418                         target->debug_reason    = DBG_REASON_NOTHALTED;
 419                 }
 420         }
 421
 422         return ERROR_OK;
 423 }
 424 /* architecture specific status reply */
 425 static int arm11_arch_state(struct target *target)
 426 {
 427         int retval;
 428
 429         retval = armv4_5_arch_state(target);
 430
 431         /* REVISIT also display ARM11-specific MMU and cache status ... */
 432
 433         return retval;
 434 }
 435
 436 /* target request support */
 437 static int arm11_target_request_data(struct target *target,
 438                 uint32_t size, uint8_t *buffer)
 439 {
 440         LOG_WARNING("Not implemented: %s", __func__);
 441
 442         return ERROR_FAIL;
 443 }
 444
 445 /* target execution control */
 446 static int arm11_halt(struct target *target)
 447 {
 448         struct arm11_common *arm11 = target_to_arm11(target);
 449
 450         LOG_DEBUG("target->state: %s",
 451                 target_state_name(target));
 452
 453         if (target->state == TARGET_UNKNOWN)
 454         {
 455                 arm11->simulate_reset_on_next_halt = true;
 456         }
 457
 458         if (target->state == TARGET_HALTED)
 459         {
 460                 LOG_DEBUG("target was already halted");
 461                 return ERROR_OK;
 462         }
 463
 464         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 465
 466         CHECK_RETVAL(jtag_execute_queue());
 467
 468         uint32_t dscr;
 469         int i = 0;
 470
 471         while (1)
 472         {
 473                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 474
 475                 if (dscr & ARM11_DSCR_CORE_HALTED)
 476                         break;
 477
 478
 479                 long long then = 0;
 480                 if (i == 1000)
 481                 {
 482                         then = timeval_ms();
 483                 }
 484                 if (i >= 1000)
 485                 {
 486                         if ((timeval_ms()-then) > 1000)
 487                         {
 488                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 489                                 return ERROR_FAIL;
 490                         }
 491                 }
 492                 i++;
 493         }
 494
 495         enum target_state old_state     = target->state;
 496
 497         arm11_debug_entry(arm11, dscr);
 498
 499         CHECK_RETVAL(
 500                 target_call_event_callbacks(target,
 501                         old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 502
 503         return ERROR_OK;
 504 }
 505
 506 static uint32_t
 507 arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
 508 {
 509         void *value = arm11->arm.core_cache->reg_list[15].value;
 510
 511         if (!current)
 512                 buf_set_u32(value, 0, 32, address);
 513         else
 514                 address = buf_get_u32(value, 0, 32);
 515
 516         return address;
 517 }
 518
 519 static int arm11_resume(struct target *target, int current,
 520                 uint32_t address, int handle_breakpoints, int debug_execution)
 521 {
 522         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 523         //      current, address, handle_breakpoints, debug_execution);
 524
 525         struct arm11_common *arm11 = target_to_arm11(target);
 526
 527         LOG_DEBUG("target->state: %s",
 528                 target_state_name(target));
 529
 530
 531         if (target->state != TARGET_HALTED)
 532         {
 533                 LOG_ERROR("Target not halted");
 534                 return ERROR_TARGET_NOT_HALTED;
 535         }
 536
 537         address = arm11_nextpc(arm11, current, address);
 538
 539         LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
 540
 541         /* clear breakpoints/watchpoints and VCR*/
 542         arm11_sc7_clear_vbw(arm11);
 543
 544         if (!debug_execution)
 545                 target_free_all_working_areas(target);
 546
 547         /* Set up breakpoints */
 548         if (handle_breakpoints)
 549         {
 550                 /* check if one matches PC and step over it if necessary */
 551
 552                 struct breakpoint *     bp;
 553
 554                 for (bp = target->breakpoints; bp; bp = bp->next)
 555                 {
 556                         if (bp->address == address)
 557                         {
 558                                 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 559                                 arm11_step(target, 1, 0, 0);
 560                                 break;
 561                         }
 562                 }
 563
 564                 /* set all breakpoints */
 565
 566                 unsigned brp_num = 0;
 567
 568                 for (bp = target->breakpoints; bp; bp = bp->next)
 569                 {
 570                         struct arm11_sc7_action brp[2];
 571
 572                         brp[0].write    = 1;
 573                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 574                         brp[0].value    = bp->address;
 575                         brp[1].write    = 1;
 576                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 577                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 578
 579                         arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
 580
 581                         LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
 582                                         bp->address);
 583
 584                         brp_num++;
 585                 }
 586
 587                 arm11_sc7_set_vcr(arm11, arm11_vcr);
 588         }
 589
 590         arm11_leave_debug_state(arm11, handle_breakpoints);
 591
 592         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 593
 594         CHECK_RETVAL(jtag_execute_queue());
 595
 596         int i = 0;
 597         while (1)
 598         {
 599                 uint32_t dscr;
 600
 601                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 602
 603                 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 604
 605                 if (dscr & ARM11_DSCR_CORE_RESTARTED)
 606                         break;
 607
 608
 609                 long long then = 0;
 610                 if (i == 1000)
 611                 {
 612                         then = timeval_ms();
 613                 }
 614                 if (i >= 1000)
 615                 {
 616                         if ((timeval_ms()-then) > 1000)
 617                         {
 618                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 619                                 return ERROR_FAIL;
 620                         }
 621                 }
 622                 i++;
 623         }
 624
 625         if (!debug_execution)
 626         {
 627                 target->state                   = TARGET_RUNNING;
 628                 target->debug_reason    = DBG_REASON_NOTHALTED;
 629
 630                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 631         }
 632         else
 633         {
 634                 target->state                   = TARGET_DEBUG_RUNNING;
 635                 target->debug_reason    = DBG_REASON_NOTHALTED;
 636
 637                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 638         }
 639
 640         return ERROR_OK;
 641 }
 642
 643 static int arm11_step(struct target *target, int current,
 644                 uint32_t address, int handle_breakpoints)
 645 {
 646         LOG_DEBUG("target->state: %s",
 647                 target_state_name(target));
 648
 649         if (target->state != TARGET_HALTED)
 650         {
 651                 LOG_WARNING("target was not halted");
 652                 return ERROR_TARGET_NOT_HALTED;
 653         }
 654
 655         struct arm11_common *arm11 = target_to_arm11(target);
 656
 657         address = arm11_nextpc(arm11, current, address);
 658
 659         LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
 660
 661
 662         /** \todo TODO: Thumb not supported here */
 663
 664         uint32_t        next_instruction;
 665
 666         CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
 667
 668         /* skip over BKPT */
 669         if ((next_instruction & 0xFFF00070) == 0xe1200070)
 670         {
 671                 address = arm11_nextpc(arm11, 0, address + 4);
 672                 LOG_DEBUG("Skipping BKPT");
 673         }
 674         /* skip over Wait for interrupt / Standby */
 675         /* mcr  15, 0, r?, cr7, cr0, {4} */
 676         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
 677         {
 678                 address = arm11_nextpc(arm11, 0, address + 4);
 679                 LOG_DEBUG("Skipping WFI");
 680         }
 681         /* ignore B to self */
 682         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
 683         {
 684                 LOG_DEBUG("Not stepping jump to self");
 685         }
 686         else
 687         {
 688                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
 689                 * with this. */
 690
 691                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
 692                 * the VCR might be something worth looking into. */
 693
 694
 695                 /* Set up breakpoint for stepping */
 696
 697                 struct arm11_sc7_action brp[2];
 698
 699                 brp[0].write    = 1;
 700                 brp[0].address  = ARM11_SC7_BVR0;
 701                 brp[1].write    = 1;
 702                 brp[1].address  = ARM11_SC7_BCR0;
 703
 704                 if (arm11_config_hardware_step)
 705                 {
 706                         /* Hardware single stepping ("instruction address
 707                          * mismatch") is used if enabled.  It's not quite
 708                          * exactly "run one instruction"; "branch to here"
 709                          * loops won't break, neither will some other cases,
 710                          * but it's probably the best default.
 711                          *
 712                          * Hardware single stepping isn't supported on v6
 713                          * debug modules.  ARM1176 and v7 can support it...
 714                          *
 715                          * FIXME Thumb stepping likely needs to use 0x03
 716                          * or 0xc0 byte masks, not 0x0f.
 717                          */
 718                          brp[0].value   = address;
 719                          brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5)
 720                                         | (0 << 14) | (0 << 16) | (0 << 20)
 721                                         | (2 << 21);
 722                 } else
 723                 {
 724                         /* Sets a breakpoint on the next PC, as calculated
 725                          * by instruction set simulation.
 726                          *
 727                          * REVISIT stepping Thumb on ARM1156 requires Thumb2
 728                          * support from the simulator.
 729                          */
 730                         uint32_t next_pc;
 731                         int retval;
 732
 733                         retval = arm_simulate_step(target, &next_pc);
 734                         if (retval != ERROR_OK)
 735                                 return retval;
 736
 737                         brp[0].value    = next_pc;
 738                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5)
 739                                         | (0 << 14) | (0 << 16) | (0 << 20)
 740                                         | (0 << 21);
 741                 }
 742
 743                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
 744
 745                 /* resume */
 746
 747
 748                 if (arm11_config_step_irq_enable)
 749                         R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;              /* should be redundant */
 750                 else
 751                         R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
 752
 753
 754                 CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
 755
 756                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 757
 758                 CHECK_RETVAL(jtag_execute_queue());
 759
 760                 /* wait for halt */
 761                 int i = 0;
 762                 uint32_t dscr;
 763
 764                 while (1)
 765                 {
 766                         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 767
 768                         LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
 769
 770                         if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
 771                                 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
 772                                 break;
 773
 774                         long long then = 0;
 775                         if (i == 1000)
 776                         {
 777                                 then = timeval_ms();
 778                         }
 779                         if (i >= 1000)
 780                         {
 781                                 if ((timeval_ms()-then) > 1000)
 782                                 {
 783                                         LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 784                                         return ERROR_FAIL;
 785                                 }
 786                         }
 787                         i++;
 788                 }
 789
 790                 /* clear breakpoint */
 791                 arm11_sc7_clear_vbw(arm11);
 792
 793                 /* save state */
 794                 CHECK_RETVAL(arm11_debug_entry(arm11, dscr));
 795
 796             /* restore default state */
 797                 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
 798
 799         }
 800
 801         target->debug_reason    = DBG_REASON_SINGLESTEP;
 802
 803         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 804
 805         return ERROR_OK;
 806 }
 807
 808 static int arm11_assert_reset(struct target *target)
 809 {
 810         int retval;
 811         struct arm11_common *arm11 = target_to_arm11(target);
 812
 813         retval = arm11_check_init(arm11, NULL);
 814         if (retval != ERROR_OK)
 815                 return retval;
 816
 817         target->state = TARGET_UNKNOWN;
 818
 819         /* we would very much like to reset into the halted, state,
 820          * but resetting and halting is second best... */
 821         if (target->reset_halt)
 822         {
 823                 CHECK_RETVAL(target_halt(target));
 824         }
 825
 826
 827         /* srst is funny. We can not do *anything* else while it's asserted
 828          * and it has unkonwn side effects. Make sure no other code runs
 829          * meanwhile.
 830          *
 831          * Code below assumes srst:
 832          *
 833          * - Causes power-on-reset (but of what parts of the system?). Bug
 834          * in arm11?
 835          *
 836          * - Messes us TAP state without asserting trst.
 837          *
 838          * - There is another bug in the arm11 core. When you generate an access to
 839          * external logic (for example ddr controller via AHB bus) and that block
 840          * is not configured (perhaps it is still held in reset), that transaction
 841          * will never complete. This will hang arm11 core but it will also hang
 842          * JTAG controller. Nothing, short of srst assertion will bring it out of
 843          * this.
 844          *
 845          * Mysteries:
 846          *
 847          * - What should the PC be after an srst reset when starting in the halted
 848          * state?
 849          */
 850
 851         jtag_add_reset(0, 1);
 852         jtag_add_reset(0, 0);
 853
 854         /* How long do we have to wait? */
 855         jtag_add_sleep(5000);
 856
 857         /* un-mess up TAP state */
 858         jtag_add_tlr();
 859
 860         retval = jtag_execute_queue();
 861         if (retval != ERROR_OK)
 862         {
 863                 return retval;
 864         }
 865
 866         return ERROR_OK;
 867 }
 868
 869 static int arm11_deassert_reset(struct target *target)
 870 {
 871         return ERROR_OK;
 872 }
 873
 874 static int arm11_soft_reset_halt(struct target *target)
 875 {
 876         LOG_WARNING("Not implemented: %s", __func__);
 877
 878         return ERROR_FAIL;
 879 }
 880
 881 /* target memory access
 882  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 883  * count: number of items of <size>
 884  *
 885  * arm11_config_memrw_no_increment - in the future we may want to be able
 886  * to read/write a range of data to a "port". a "port" is an action on
 887  * read memory address for some peripheral.
 888  */
 889 static int arm11_read_memory_inner(struct target *target,
 890                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
 891                 bool arm11_config_memrw_no_increment)
 892 {
 893         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
 894         int retval;
 895
 896         if (target->state != TARGET_HALTED)
 897         {
 898                 LOG_WARNING("target was not halted");
 899                 return ERROR_TARGET_NOT_HALTED;
 900         }
 901
 902         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 903
 904         struct arm11_common *arm11 = target_to_arm11(target);
 905
 906         retval = arm11_run_instr_data_prepare(arm11);
 907         if (retval != ERROR_OK)
 908                 return retval;
 909
 910         /* MRC p14,0,r0,c0,c5,0 */
 911         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
 912         if (retval != ERROR_OK)
 913                 return retval;
 914
 915         switch (size)
 916         {
 917         case 1:
 918                 arm11->arm.core_cache->reg_list[1].dirty = true;
 919
 920                 for (size_t i = 0; i < count; i++)
 921                 {
 922                         /* ldrb    r1, [r0], #1 */
 923                         /* ldrb    r1, [r0] */
 924                         arm11_run_instr_no_data1(arm11,
 925                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
 926
 927                         uint32_t res;
 928                         /* MCR p14,0,R1,c0,c5,0 */
 929                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 930
 931                         *buffer++ = res;
 932                 }
 933
 934                 break;
 935
 936         case 2:
 937                 {
 938                         arm11->arm.core_cache->reg_list[1].dirty = true;
 939
 940                         for (size_t i = 0; i < count; i++)
 941                         {
 942                                 /* ldrh    r1, [r0], #2 */
 943                                 arm11_run_instr_no_data1(arm11,
 944                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
 945
 946                                 uint32_t res;
 947
 948                                 /* MCR p14,0,R1,c0,c5,0 */
 949                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 950
 951                                 uint16_t svalue = res;
 952                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
 953                         }
 954
 955                         break;
 956                 }
 957
 958         case 4:
 959                 {
 960                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
 961                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
 962                 uint32_t *words = (uint32_t *)buffer;
 963
 964                 /* LDC p14,c5,[R0],#4 */
 965                 /* LDC p14,c5,[R0] */
 966                 arm11_run_instr_data_from_core(arm11, instr, words, count);
 967                 break;
 968                 }
 969         }
 970
 971         return arm11_run_instr_data_finish(arm11);
 972 }
 973
 974 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 975 {
 976         return arm11_read_memory_inner(target, address, size, count, buffer, false);
 977 }
 978
 979 /*
 980 * no_increment - in the future we may want to be able
 981 * to read/write a range of data to a "port". a "port" is an action on
 982 * read memory address for some peripheral.
 983 */
 984 static int arm11_write_memory_inner(struct target *target,
 985                 uint32_t address, uint32_t size,
 986                 uint32_t count, uint8_t *buffer,
 987                 bool no_increment)
 988 {
 989         int retval;
 990
 991         if (target->state != TARGET_HALTED)
 992         {
 993                 LOG_WARNING("target was not halted");
 994                 return ERROR_TARGET_NOT_HALTED;
 995         }
 996
 997         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 998
 999         struct arm11_common *arm11 = target_to_arm11(target);
1000
1001         retval = arm11_run_instr_data_prepare(arm11);
1002         if (retval != ERROR_OK)
1003                 return retval;
1004
1005         /* MRC p14,0,r0,c0,c5,0 */
1006         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1007         if (retval != ERROR_OK)
1008                 return retval;
1009
1010         /* burst writes are not used for single words as those may well be
1011          * reset init script writes.
1012          *
1013          * The other advantage is that as burst writes are default, we'll
1014          * now exercise both burst and non-burst code paths with the
1015          * default settings, increasing code coverage.
1016          */
1017         bool burst = arm11_config_memwrite_burst && (count > 1);
1018
1019         switch (size)
1020         {
1021         case 1:
1022                 {
1023                         arm11->arm.core_cache->reg_list[1].dirty = true;
1024
1025                         for (size_t i = 0; i < count; i++)
1026                         {
1027                                 /* MRC p14,0,r1,c0,c5,0 */
1028                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1029                                 if (retval != ERROR_OK)
1030                                         return retval;
1031
1032                                 /* strb    r1, [r0], #1 */
1033                                 /* strb    r1, [r0] */
1034                                 retval = arm11_run_instr_no_data1(arm11,
1035                                         !no_increment
1036                                                 ? 0xe4c01001
1037                                                 : 0xe5c01000);
1038                                 if (retval != ERROR_OK)
1039                                         return retval;
1040                         }
1041
1042                         break;
1043                 }
1044
1045         case 2:
1046                 {
1047                         arm11->arm.core_cache->reg_list[1].dirty = true;
1048
1049                         for (size_t i = 0; i < count; i++)
1050                         {
1051                                 uint16_t value;
1052                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1053
1054                                 /* MRC p14,0,r1,c0,c5,0 */
1055                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1056                                 if (retval != ERROR_OK)
1057                                         return retval;
1058
1059                                 /* strh    r1, [r0], #2 */
1060                                 /* strh    r1, [r0] */
1061                                 retval = arm11_run_instr_no_data1(arm11,
1062                                         !no_increment
1063                                                 ? 0xe0c010b2
1064                                                 : 0xe1c010b0);
1065                                 if (retval != ERROR_OK)
1066                                         return retval;
1067                         }
1068
1069                         break;
1070                 }
1071
1072         case 4: {
1073                 uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
1074
1075                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1076                 uint32_t *words = (uint32_t*)buffer;
1077
1078                 if (!burst)
1079                 {
1080                         /* STC p14,c5,[R0],#4 */
1081                         /* STC p14,c5,[R0]*/
1082                         retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1083                         if (retval != ERROR_OK)
1084                                 return retval;
1085                 }
1086                 else
1087                 {
1088                         /* STC p14,c5,[R0],#4 */
1089                         /* STC p14,c5,[R0]*/
1090                         retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1091                         if (retval != ERROR_OK)
1092                                 return retval;
1093                 }
1094
1095                 break;
1096         }
1097         }
1098
1099         /* r0 verification */
1100         if (!no_increment)
1101         {
1102                 uint32_t r0;
1103
1104                 /* MCR p14,0,R0,c0,c5,0 */
1105                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1106                 if (retval != ERROR_OK)
1107                         return retval;
1108
1109                 if (address + size * count != r0)
1110                 {
1111                         LOG_ERROR("Data transfer failed. Expected end "
1112                                         "address 0x%08x, got 0x%08x",
1113                                         (unsigned) (address + size * count),
1114                                         (unsigned) r0);
1115
1116                         if (burst)
1117                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1118
1119                         if (arm11_config_memwrite_error_fatal)
1120                                 return ERROR_FAIL;
1121                 }
1122         }
1123
1124         return arm11_run_instr_data_finish(arm11);
1125 }
1126
1127 static int arm11_write_memory(struct target *target,
1128                 uint32_t address, uint32_t size,
1129                 uint32_t count, uint8_t *buffer)
1130 {
1131         /* pointer increment matters only for multi-unit writes ...
1132          * not e.g. to a "reset the chip" controller.
1133          */
1134         return arm11_write_memory_inner(target, address, size,
1135                         count, buffer, count == 1);
1136 }
1137
1138 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1139 static int arm11_bulk_write_memory(struct target *target,
1140                 uint32_t address, uint32_t count, uint8_t *buffer)
1141 {
1142         if (target->state != TARGET_HALTED)
1143         {
1144                 LOG_WARNING("target was not halted");
1145                 return ERROR_TARGET_NOT_HALTED;
1146         }
1147
1148         return arm11_write_memory(target, address, 4, count, buffer);
1149 }
1150
1151 /* target break-/watchpoint control
1152 * rw: 0 = write, 1 = read, 2 = access
1153 */
1154 static int arm11_add_breakpoint(struct target *target,
1155                 struct breakpoint *breakpoint)
1156 {
1157         struct arm11_common *arm11 = target_to_arm11(target);
1158
1159 #if 0
1160         if (breakpoint->type == BKPT_SOFT)
1161         {
1162                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1163                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1164         }
1165 #endif
1166
1167         if (!arm11->free_brps)
1168         {
1169                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1170                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1171         }
1172
1173         if (breakpoint->length != 4)
1174         {
1175                 LOG_DEBUG("only breakpoints of four bytes length supported");
1176                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1177         }
1178
1179         arm11->free_brps--;
1180
1181         return ERROR_OK;
1182 }
1183
1184 static int arm11_remove_breakpoint(struct target *target,
1185                 struct breakpoint *breakpoint)
1186 {
1187         struct arm11_common *arm11 = target_to_arm11(target);
1188
1189         arm11->free_brps++;
1190
1191         return ERROR_OK;
1192 }
1193
1194 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1195 {
1196         struct arm11_common *arm11;
1197
1198         if (target->tap == NULL)
1199                 return ERROR_FAIL;
1200
1201         if (target->tap->ir_length != 5)
1202         {
1203                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1204                 return ERROR_COMMAND_SYNTAX_ERROR;
1205         }
1206
1207         arm11 = calloc(1, sizeof *arm11);
1208         if (!arm11)
1209                 return ERROR_FAIL;
1210
1211         armv4_5_init_arch_info(target, &arm11->arm);
1212
1213         arm11->jtag_info.tap = target->tap;
1214         arm11->jtag_info.scann_size = 5;
1215         arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1216         /* cur_scan_chain == 0 */
1217         arm11->jtag_info.intest_instr = ARM11_INTEST;
1218
1219         return ERROR_OK;
1220 }
1221
1222 static int arm11_init_target(struct command_context *cmd_ctx,
1223                 struct target *target)
1224 {
1225         /* Initialize anything we can set up without talking to the target */
1226
1227         /* REVISIT do we really want such a debug-registers-only cache?
1228          * If we do, it should probably be handled purely by the DPM code,
1229          * so it works identically on the v7a/v7r cores.
1230          */
1231         return arm11_build_reg_cache(target);
1232 }
1233
1234 /* talk to the target and set things up */
1235 static int arm11_examine(struct target *target)
1236 {
1237         int retval;
1238         char *type;
1239         struct arm11_common *arm11 = target_to_arm11(target);
1240         uint32_t didr, device_id;
1241         uint8_t implementor;
1242
1243         /* FIXME split into do-first-time and do-every-time logic ... */
1244
1245         /* check IDCODE */
1246
1247         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1248
1249         struct scan_field               idcode_field;
1250
1251         arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1252
1253         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1254
1255         /* check DIDR */
1256
1257         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1258
1259         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1260
1261         struct scan_field               chain0_fields[2];
1262
1263         arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1264         arm11_setup_field(arm11,  8, NULL, &implementor, chain0_fields + 1);
1265
1266         arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1267
1268         CHECK_RETVAL(jtag_execute_queue());
1269
1270         switch (device_id & 0x0FFFF000)
1271         {
1272         case 0x07B36000:
1273                 type = "ARM1136";
1274                 break;
1275         case 0x07B56000:
1276                 type = "ARM1156";
1277                 break;
1278         case 0x07B76000:
1279                 arm11->arm.core_type = ARM_MODE_MON;
1280                 type = "ARM1176";
1281                 break;
1282         default:
1283                 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1284                 return ERROR_FAIL;
1285         }
1286         LOG_INFO("found %s", type);
1287
1288         /* unlikely this could ever fail, but ... */
1289         switch ((didr >> 16) & 0x0F) {
1290         case ARM11_DEBUG_V6:
1291         case ARM11_DEBUG_V61:           /* supports security extensions */
1292                 break;
1293         default:
1294                 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1295                 return ERROR_FAIL;
1296         }
1297
1298         arm11->brp = ((didr >> 24) & 0x0F) + 1;
1299         arm11->wrp = ((didr >> 28) & 0x0F) + 1;
1300
1301         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1302         arm11->free_brps = arm11->brp;
1303
1304         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1305                         device_id, implementor, didr);
1306
1307         /* as a side-effect this reads DSCR and thus
1308          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1309          * as suggested by the spec.
1310          */
1311
1312         retval = arm11_check_init(arm11, NULL);
1313         if (retval != ERROR_OK)
1314                 return retval;
1315
1316         /* Build register cache "late", after target_init(), since we
1317          * want to know if this core supports Secure Monitor mode.
1318          */
1319         if (!target_was_examined(target))
1320                 retval = arm11_dpm_init(arm11, didr);
1321
1322         /* ETM on ARM11 still uses original scanchain 6 access mode */
1323         if (arm11->arm.etm && !target_was_examined(target)) {
1324                 *register_get_last_cache_p(&target->reg_cache) =
1325                         etm_build_reg_cache(target, &arm11->jtag_info,
1326                                         arm11->arm.etm);
1327                 retval = etm_setup(target);
1328         }
1329
1330         target_set_examined(target);
1331
1332         return ERROR_OK;
1333 }
1334
1335
1336 /** Load a register that is marked !valid in the register cache */
1337 static int arm11_get_reg(struct reg *reg)
1338 {
1339         struct arm11_reg_state *r = reg->arch_info;
1340         struct target *target = r->target;
1341
1342         if (target->state != TARGET_HALTED)
1343         {
1344                 LOG_WARNING("target was not halted");
1345                 return ERROR_TARGET_NOT_HALTED;
1346         }
1347
1348         /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1349
1350 #if 0
1351         struct arm11_common *arm11 = target_to_arm11(target);
1352         const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1353 #endif
1354
1355         return ERROR_OK;
1356 }
1357
1358 /** Change a value in the register cache */
1359 static int arm11_set_reg(struct reg *reg, uint8_t *buf)
1360 {
1361         struct arm11_reg_state *r = reg->arch_info;
1362         struct target *target = r->target;
1363         struct arm11_common *arm11 = target_to_arm11(target);
1364 //      const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1365
1366         arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1367         reg->valid      = 1;
1368         reg->dirty      = 1;
1369
1370         return ERROR_OK;
1371 }
1372
1373 static const struct reg_arch_type arm11_reg_type = {
1374         .get = arm11_get_reg,
1375         .set = arm11_set_reg,
1376 };
1377
1378 static int arm11_build_reg_cache(struct target *target)
1379 {
1380         struct arm11_common *arm11 = target_to_arm11(target);
1381         struct reg_cache *cache;
1382         struct reg *reg_list;
1383         struct arm11_reg_state *arm11_reg_states;
1384
1385         cache = calloc(1, sizeof *cache);
1386         reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list);
1387         arm11_reg_states = calloc(ARM11_REGCACHE_COUNT,
1388                         sizeof *arm11_reg_states);
1389         if (!cache || !reg_list || !arm11_reg_states) {
1390                 free(cache);
1391                 free(reg_list);
1392                 free(arm11_reg_states);
1393                 return ERROR_FAIL;
1394         }
1395
1396         arm11->reg_list = reg_list;
1397
1398         /* build cache for some of the debug registers */
1399         cache->name = "arm11 debug registers";
1400         cache->reg_list = reg_list;
1401         cache->num_regs = ARM11_REGCACHE_COUNT;
1402
1403         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1404         (*cache_p) = cache;
1405
1406         arm11->core_cache = cache;
1407
1408         size_t i;
1409
1410         /* Not very elegant assertion */
1411         if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
1412                 ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
1413                 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1414         {
1415                 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)",
1416                                 ARM11_REGCACHE_COUNT,
1417                                 (unsigned) ARRAY_SIZE(arm11->reg_values),
1418                                 (unsigned) ARRAY_SIZE(arm11_reg_defs),
1419                                 ARM11_RC_MAX);
1420                 /* FIXME minimally, use a build_bug_on(X) mechanism;
1421                  * runtime exit() here is bad!
1422                  */
1423                 exit(-1);
1424         }
1425
1426         for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1427         {
1428                 struct reg *                                            r       = reg_list                      + i;
1429                 const struct arm11_reg_defs *   rd      = arm11_reg_defs        + i;
1430                 struct arm11_reg_state *                        rs      = arm11_reg_states      + i;
1431
1432                 r->name                         = rd->name;
1433                 r->size                         = 32;
1434                 r->value                        = (uint8_t *)(arm11->reg_values + i);
1435                 r->dirty                        = 0;
1436                 r->valid                        = 0;
1437                 r->type = &arm11_reg_type;
1438                 r->arch_info            = rs;
1439
1440                 rs->def_index           = i;
1441                 rs->target                      = target;
1442         }
1443
1444         return ERROR_OK;
1445 }
1446
1447 /* FIXME all these BOOL_WRAPPER things should be modifying
1448  * per-instance state, not shared state; ditto the vector
1449  * catch register support.  Scan chains with multiple cores
1450  * should be able to say "work with this core like this,
1451  * that core like that".  Example, ARM11 MPCore ...
1452  */
1453
1454 #define ARM11_BOOL_WRAPPER(name, print_name)    \
1455                 COMMAND_HANDLER(arm11_handle_bool_##name) \
1456                 { \
1457                         return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1458                                         &arm11_config_##name, print_name); \
1459                 }
1460
1461 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1462 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1463 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1464 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1465
1466 COMMAND_HANDLER(arm11_handle_vcr)
1467 {
1468         switch (CMD_ARGC) {
1469         case 0:
1470                 break;
1471         case 1:
1472                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
1473                 break;
1474         default:
1475                 return ERROR_COMMAND_SYNTAX_ERROR;
1476         }
1477
1478         LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1479         return ERROR_OK;
1480 }
1481
1482 static const struct command_registration arm11_mw_command_handlers[] = {
1483         {
1484                 .name = "burst",
1485                 .handler = &arm11_handle_bool_memwrite_burst,
1486                 .mode = COMMAND_ANY,
1487                 .help = "Enable/Disable non-standard but fast burst mode"
1488                         " (default: enabled)",
1489         },
1490         {
1491                 .name = "error_fatal",
1492                 .handler = &arm11_handle_bool_memwrite_error_fatal,
1493                 .mode = COMMAND_ANY,
1494                 .help = "Terminate program if transfer error was found"
1495                         " (default: enabled)",
1496         },
1497         COMMAND_REGISTRATION_DONE
1498 };
1499 static const struct command_registration arm11_any_command_handlers[] = {
1500         {
1501                 /* "hardware_step" is only here to check if the default
1502                  * simulate + breakpoint implementation is broken.
1503                  * TEMPORARY! NOT DOCUMENTED! */
1504                 .name = "hardware_step",
1505                 .handler = &arm11_handle_bool_hardware_step,
1506                 .mode = COMMAND_ANY,
1507                 .help = "DEBUG ONLY - Hardware single stepping"
1508                         " (default: disabled)",
1509                 .usage = "(enable|disable)",
1510         },
1511         {
1512                 .name = "memwrite",
1513                 .mode = COMMAND_ANY,
1514                 .help = "memwrite command group",
1515                 .chain = arm11_mw_command_handlers,
1516         },
1517         {
1518                 .name = "step_irq_enable",
1519                 .handler = &arm11_handle_bool_step_irq_enable,
1520                 .mode = COMMAND_ANY,
1521                 .help = "Enable interrupts while stepping"
1522                         " (default: disabled)",
1523         },
1524         {
1525                 .name = "vcr",
1526                 .handler = &arm11_handle_vcr,
1527                 .mode = COMMAND_ANY,
1528                 .help = "Control (Interrupt) Vector Catch Register",
1529         },
1530         COMMAND_REGISTRATION_DONE
1531 };
1532 static const struct command_registration arm11_command_handlers[] = {
1533         {
1534                 .chain = arm_command_handlers,
1535         },
1536         {
1537                 .chain = etm_command_handlers,
1538         },
1539         {
1540                 .name = "arm11",
1541                 .mode = COMMAND_ANY,
1542                 .help = "ARM11 command group",
1543                 .chain = arm11_any_command_handlers,
1544         },
1545         COMMAND_REGISTRATION_DONE
1546 };
1547
1548 /** Holds methods for ARM11xx targets. */
1549 struct target_type arm11_target = {
1550         .name =                 "arm11",
1551
1552         .poll =                 arm11_poll,
1553         .arch_state =           arm11_arch_state,
1554
1555         .target_request_data =  arm11_target_request_data,
1556
1557         .halt =                 arm11_halt,
1558         .resume =               arm11_resume,
1559         .step =                 arm11_step,
1560
1561         .assert_reset =         arm11_assert_reset,
1562         .deassert_reset =       arm11_deassert_reset,
1563         .soft_reset_halt =      arm11_soft_reset_halt,
1564
1565         .get_gdb_reg_list =     armv4_5_get_gdb_reg_list,
1566
1567         .read_memory =          arm11_read_memory,
1568         .write_memory =         arm11_write_memory,
1569
1570         .bulk_write_memory =    arm11_bulk_write_memory,
1571
1572         .checksum_memory =      arm_checksum_memory,
1573         .blank_check_memory =   arm_blank_check_memory,
1574
1575         .add_breakpoint =       arm11_add_breakpoint,
1576         .remove_breakpoint =    arm11_remove_breakpoint,
1577
1578         .run_algorithm =        armv4_5_run_algorithm,
1579
1580         .commands =             arm11_command_handlers,
1581         .target_create =        arm11_target_create,
1582         .init_target =          arm11_init_target,
1583         .examine =              arm11_examine,
1584 };