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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "etm.h"
  30 #include "breakpoints.h"
  31 #include "arm11_dbgtap.h"
  32 #include "arm_simulator.h"
  33 #include "time_support.h"
  34 #include "target_type.h"
  35 #include "algorithm.h"
  36 #include "register.h"
  37
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 static bool arm11_config_memwrite_burst = true;
  44 static bool arm11_config_memwrite_error_fatal = true;
  45 static uint32_t arm11_vcr = 0;
  46 static bool arm11_config_step_irq_enable = false;
  47 static bool arm11_config_hardware_step = false;
  48
  49 enum arm11_regtype
  50 {
  51         /* debug regs */
  52         ARM11_REGISTER_DSCR,
  53         ARM11_REGISTER_WDTR,
  54         ARM11_REGISTER_RDTR,
  55 };
  56
  57
  58 struct arm11_reg_defs
  59 {
  60         char *                                  name;
  61         uint32_t                                                num;
  62         int                                             gdb_num;
  63         enum arm11_regtype              type;
  64 };
  65
  66 /* update arm11_regcache_ids when changing this */
  67 static const struct arm11_reg_defs arm11_reg_defs[] =
  68 {
  69         /* Debug Registers */
  70         {"dscr",        0,      -1,     ARM11_REGISTER_DSCR},
  71         {"wdtr",        0,      -1,     ARM11_REGISTER_WDTR},
  72         {"rdtr",        0,      -1,     ARM11_REGISTER_RDTR},
  73 };
  74
  75 enum arm11_regcache_ids
  76 {
  77         ARM11_RC_DSCR,
  78         ARM11_RC_WDTR,
  79         ARM11_RC_RDTR,
  80
  81         ARM11_RC_MAX,
  82 };
  83
  84 static int arm11_step(struct target *target, int current,
  85                 uint32_t address, int handle_breakpoints);
  86 /* helpers */
  87 static int arm11_build_reg_cache(struct target *target);
  88 static int arm11_set_reg(struct reg *reg, uint8_t *buf);
  89 static int arm11_get_reg(struct reg *reg);
  90
  91
  92 /** Check and if necessary take control of the system
  93  *
  94  * \param arm11         Target state variable.
  95  * \param dscr          If the current DSCR content is
  96  *                                      available a pointer to a word holding the
  97  *                                      DSCR can be passed. Otherwise use NULL.
  98  */
  99 static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
 100 {
 101         uint32_t                        dscr_local_tmp_copy;
 102
 103         if (!dscr)
 104         {
 105                 dscr = &dscr_local_tmp_copy;
 106
 107                 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
 108         }
 109
 110         if (!(*dscr & ARM11_DSCR_MODE_SELECT))
 111         {
 112                 LOG_DEBUG("Bringing target into debug mode");
 113
 114                 *dscr |= ARM11_DSCR_MODE_SELECT;                /* Halt debug-mode */
 115                 arm11_write_DSCR(arm11, *dscr);
 116
 117                 /* add further reset initialization here */
 118
 119                 arm11->simulate_reset_on_next_halt = true;
 120
 121                 if (*dscr & ARM11_DSCR_CORE_HALTED)
 122                 {
 123                         /** \todo TODO: this needs further scrutiny because
 124                           * arm11_debug_entry() never gets called.  (WHY NOT?)
 125                           * As a result we don't read the actual register states from
 126                           * the target.
 127                           */
 128
 129                         arm11->arm.target->state = TARGET_HALTED;
 130                         arm11->arm.target->debug_reason =
 131                                         arm11_get_DSCR_debug_reason(*dscr);
 132                 }
 133                 else
 134                 {
 135                         arm11->arm.target->state = TARGET_RUNNING;
 136                         arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
 137                 }
 138
 139                 arm11_sc7_clear_vbw(arm11);
 140         }
 141
 142         return ERROR_OK;
 143 }
 144
 145
 146
 147 #define R(x) \
 148         (arm11->reg_values[ARM11_RC_##x])
 149
 150 /**
 151  * Save processor state.  This is called after a HALT instruction
 152  * succeeds, and on other occasions the processor enters debug mode
 153  * (breakpoint, watchpoint, etc).
 154  */
 155 static int arm11_debug_entry(struct arm11_common *arm11, uint32_t dscr)
 156 {
 157         int retval;
 158
 159         arm11->arm.target->state = TARGET_HALTED;
 160         arm11->arm.target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
 161
 162         /* REVISIT entire cache should already be invalid !!! */
 163         register_cache_invalidate(arm11->arm.core_cache);
 164
 165         for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
 166         {
 167                 arm11->reg_list[i].valid        = 1;
 168                 arm11->reg_list[i].dirty        = 0;
 169         }
 170
 171         /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
 172
 173         /* Save DSCR */
 174         R(DSCR) = dscr;
 175
 176         /* Save wDTR */
 177
 178         if (dscr & ARM11_DSCR_WDTR_FULL)
 179         {
 180                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 181
 182                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 183
 184                 struct scan_field       chain5_fields[3];
 185
 186                 arm11_setup_field(arm11, 32, NULL, &R(WDTR),    chain5_fields + 0);
 187                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
 188                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
 189
 190                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 191         }
 192         else
 193         {
 194                 arm11->reg_list[ARM11_RC_WDTR].valid    = 0;
 195         }
 196
 197
 198         /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
 199          *
 200          * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
 201          * but not to issue ITRs. ARM1136 seems to require this to issue
 202          * ITR's as well...
 203          */
 204         uint32_t new_dscr = dscr | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
 205
 206         /* this executes JTAG queue: */
 207
 208         arm11_write_DSCR(arm11, new_dscr);
 209
 210
 211         /* From the spec:
 212            Before executing any instruction in debug state you have to drain the write buffer.
 213            This ensures that no imprecise Data Aborts can return at a later point:*/
 214
 215         /** \todo TODO: Test drain write buffer. */
 216
 217 #if 0
 218         while (1)
 219         {
 220                 /* MRC p14,0,R0,c5,c10,0 */
 221                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 222
 223                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 224                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 225
 226                 uint32_t dscr = arm11_read_DSCR(arm11);
 227
 228                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 229
 230                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 231                 {
 232                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 233
 234                         dscr = arm11_read_DSCR(arm11);
 235
 236                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 237
 238                         break;
 239                 }
 240         }
 241 #endif
 242
 243         /* Save registers.
 244          *
 245          * NOTE:  ARM1136 TRM suggests saving just R0 here now, then
 246          * CPSR and PC after the rDTR stuff.  We do it all at once.
 247          */
 248         retval = arm_dpm_read_current_registers(&arm11->dpm);
 249         if (retval != ERROR_OK)
 250                 LOG_ERROR("DPM REG READ -- fail %d", retval);
 251
 252         retval = arm11_run_instr_data_prepare(arm11);
 253         if (retval != ERROR_OK)
 254                 return retval;
 255
 256         /* maybe save rDTR */
 257
 258         /* check rDTRfull in DSCR */
 259
 260         if (dscr & ARM11_DSCR_RDTR_FULL)
 261         {
 262                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 263                 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
 264                 if (retval != ERROR_OK)
 265                         return retval;
 266         }
 267         else
 268         {
 269                 arm11->reg_list[ARM11_RC_RDTR].valid    = 0;
 270         }
 271
 272         /* REVISIT Now that we've saved core state, there's may also
 273          * be MMU and cache state to care about ...
 274          */
 275
 276         if (arm11->simulate_reset_on_next_halt)
 277         {
 278                 arm11->simulate_reset_on_next_halt = false;
 279
 280                 LOG_DEBUG("Reset c1 Control Register");
 281
 282                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 283
 284                 /* MCR p15,0,R0,c1,c0,0 */
 285                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 286                 if (retval != ERROR_OK)
 287                         return retval;
 288
 289         }
 290
 291         retval = arm11_run_instr_data_finish(arm11);
 292         if (retval != ERROR_OK)
 293                 return retval;
 294
 295         return ERROR_OK;
 296 }
 297
 298 /**
 299  * Restore processor state.  This is called in preparation for
 300  * the RESTART function.
 301  */
 302 static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 303 {
 304         int retval;
 305
 306         /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
 307
 308         /* NOTE:  the ARM1136 TRM suggests restoring all registers
 309          * except R0/PC/CPSR right now.  Instead, we do them all
 310          * at once, just a bit later on.
 311          */
 312
 313         /* REVISIT once we start caring about MMU and cache state,
 314          * address it here ...
 315          */
 316
 317         /* spec says clear wDTR and rDTR; we assume they are clear as
 318            otherwise our programming would be sloppy */
 319         {
 320                 uint32_t DSCR;
 321
 322                 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
 323
 324                 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 325                 {
 326                         /*
 327                         The wDTR/rDTR two registers that are used to send/receive data to/from
 328                         the core in tandem with corresponding instruction codes that are
 329                         written into the core. The RDTR FULL/WDTR FULL flag indicates that the
 330                         registers hold data that was written by one side (CPU or JTAG) and not
 331                         read out by the other side.
 332                         */
 333                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 334                         return ERROR_FAIL;
 335                 }
 336         }
 337
 338         /* maybe restore original wDTR */
 339         if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
 340         {
 341                 retval = arm11_run_instr_data_prepare(arm11);
 342                 if (retval != ERROR_OK)
 343                         return retval;
 344
 345                 /* MCR p14,0,R0,c0,c5,0 */
 346                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
 347                 if (retval != ERROR_OK)
 348                         return retval;
 349
 350                 retval = arm11_run_instr_data_finish(arm11);
 351                 if (retval != ERROR_OK)
 352                         return retval;
 353         }
 354
 355         /* restore CPSR, PC, and R0 ... after flushing any modified
 356          * registers.
 357          */
 358         retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
 359
 360         register_cache_invalidate(arm11->arm.core_cache);
 361
 362         /* restore DSCR */
 363
 364         arm11_write_DSCR(arm11, R(DSCR));
 365
 366         /* maybe restore rDTR */
 367
 368         if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
 369         {
 370                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 371
 372                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 373
 374                 struct scan_field       chain5_fields[3];
 375
 376                 uint8_t                 Ready           = 0;    /* ignored */
 377                 uint8_t                 Valid           = 0;    /* ignored */
 378
 379                 arm11_setup_field(arm11, 32, &R(RDTR),  NULL, chain5_fields + 0);
 380                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 381                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 382
 383                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 384         }
 385
 386         /* now processor is ready to RESTART */
 387
 388         return ERROR_OK;
 389 }
 390
 391 /* poll current target status */
 392 static int arm11_poll(struct target *target)
 393 {
 394         int retval;
 395         struct arm11_common *arm11 = target_to_arm11(target);
 396         uint32_t        dscr;
 397
 398         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 399
 400         LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 401
 402         CHECK_RETVAL(arm11_check_init(arm11, &dscr));
 403
 404         if (dscr & ARM11_DSCR_CORE_HALTED)
 405         {
 406                 if (target->state != TARGET_HALTED)
 407                 {
 408                         enum target_state old_state = target->state;
 409
 410                         LOG_DEBUG("enter TARGET_HALTED");
 411                         retval = arm11_debug_entry(arm11, dscr);
 412                         if (retval != ERROR_OK)
 413                                 return retval;
 414
 415                         target_call_event_callbacks(target,
 416                                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
 417                 }
 418         }
 419         else
 420         {
 421                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 422                 {
 423                         LOG_DEBUG("enter TARGET_RUNNING");
 424                         target->state                   = TARGET_RUNNING;
 425                         target->debug_reason    = DBG_REASON_NOTHALTED;
 426                 }
 427         }
 428
 429         return ERROR_OK;
 430 }
 431 /* architecture specific status reply */
 432 static int arm11_arch_state(struct target *target)
 433 {
 434         int retval;
 435
 436         retval = armv4_5_arch_state(target);
 437
 438         /* REVISIT also display ARM11-specific MMU and cache status ... */
 439
 440         return retval;
 441 }
 442
 443 /* target request support */
 444 static int arm11_target_request_data(struct target *target,
 445                 uint32_t size, uint8_t *buffer)
 446 {
 447         LOG_WARNING("Not implemented: %s", __func__);
 448
 449         return ERROR_FAIL;
 450 }
 451
 452 /* target execution control */
 453 static int arm11_halt(struct target *target)
 454 {
 455         struct arm11_common *arm11 = target_to_arm11(target);
 456
 457         LOG_DEBUG("target->state: %s",
 458                 target_state_name(target));
 459
 460         if (target->state == TARGET_UNKNOWN)
 461         {
 462                 arm11->simulate_reset_on_next_halt = true;
 463         }
 464
 465         if (target->state == TARGET_HALTED)
 466         {
 467                 LOG_DEBUG("target was already halted");
 468                 return ERROR_OK;
 469         }
 470
 471         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 472
 473         CHECK_RETVAL(jtag_execute_queue());
 474
 475         uint32_t dscr;
 476         int i = 0;
 477
 478         while (1)
 479         {
 480                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 481
 482                 if (dscr & ARM11_DSCR_CORE_HALTED)
 483                         break;
 484
 485
 486                 long long then = 0;
 487                 if (i == 1000)
 488                 {
 489                         then = timeval_ms();
 490                 }
 491                 if (i >= 1000)
 492                 {
 493                         if ((timeval_ms()-then) > 1000)
 494                         {
 495                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 496                                 return ERROR_FAIL;
 497                         }
 498                 }
 499                 i++;
 500         }
 501
 502         enum target_state old_state     = target->state;
 503
 504         arm11_debug_entry(arm11, dscr);
 505
 506         CHECK_RETVAL(
 507                 target_call_event_callbacks(target,
 508                         old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 509
 510         return ERROR_OK;
 511 }
 512
 513 static uint32_t
 514 arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
 515 {
 516         void *value = arm11->arm.core_cache->reg_list[15].value;
 517
 518         if (!current)
 519                 buf_set_u32(value, 0, 32, address);
 520         else
 521                 address = buf_get_u32(value, 0, 32);
 522
 523         return address;
 524 }
 525
 526 static int arm11_resume(struct target *target, int current,
 527                 uint32_t address, int handle_breakpoints, int debug_execution)
 528 {
 529         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 530         //      current, address, handle_breakpoints, debug_execution);
 531
 532         struct arm11_common *arm11 = target_to_arm11(target);
 533
 534         LOG_DEBUG("target->state: %s",
 535                 target_state_name(target));
 536
 537
 538         if (target->state != TARGET_HALTED)
 539         {
 540                 LOG_ERROR("Target not halted");
 541                 return ERROR_TARGET_NOT_HALTED;
 542         }
 543
 544         address = arm11_nextpc(arm11, current, address);
 545
 546         LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
 547
 548         /* clear breakpoints/watchpoints and VCR*/
 549         arm11_sc7_clear_vbw(arm11);
 550
 551         if (!debug_execution)
 552                 target_free_all_working_areas(target);
 553
 554         /* Set up breakpoints */
 555         if (handle_breakpoints)
 556         {
 557                 /* check if one matches PC and step over it if necessary */
 558
 559                 struct breakpoint *     bp;
 560
 561                 for (bp = target->breakpoints; bp; bp = bp->next)
 562                 {
 563                         if (bp->address == address)
 564                         {
 565                                 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 566                                 arm11_step(target, 1, 0, 0);
 567                                 break;
 568                         }
 569                 }
 570
 571                 /* set all breakpoints */
 572
 573                 unsigned brp_num = 0;
 574
 575                 for (bp = target->breakpoints; bp; bp = bp->next)
 576                 {
 577                         struct arm11_sc7_action brp[2];
 578
 579                         brp[0].write    = 1;
 580                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 581                         brp[0].value    = bp->address;
 582                         brp[1].write    = 1;
 583                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 584                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 585
 586                         arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
 587
 588                         LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
 589                                         bp->address);
 590
 591                         brp_num++;
 592                 }
 593
 594                 arm11_sc7_set_vcr(arm11, arm11_vcr);
 595         }
 596
 597         arm11_leave_debug_state(arm11, handle_breakpoints);
 598
 599         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 600
 601         CHECK_RETVAL(jtag_execute_queue());
 602
 603         int i = 0;
 604         while (1)
 605         {
 606                 uint32_t dscr;
 607
 608                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 609
 610                 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 611
 612                 if (dscr & ARM11_DSCR_CORE_RESTARTED)
 613                         break;
 614
 615
 616                 long long then = 0;
 617                 if (i == 1000)
 618                 {
 619                         then = timeval_ms();
 620                 }
 621                 if (i >= 1000)
 622                 {
 623                         if ((timeval_ms()-then) > 1000)
 624                         {
 625                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 626                                 return ERROR_FAIL;
 627                         }
 628                 }
 629                 i++;
 630         }
 631
 632         if (!debug_execution)
 633         {
 634                 target->state                   = TARGET_RUNNING;
 635                 target->debug_reason    = DBG_REASON_NOTHALTED;
 636
 637                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 638         }
 639         else
 640         {
 641                 target->state                   = TARGET_DEBUG_RUNNING;
 642                 target->debug_reason    = DBG_REASON_NOTHALTED;
 643
 644                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 645         }
 646
 647         return ERROR_OK;
 648 }
 649
 650 static int arm11_step(struct target *target, int current,
 651                 uint32_t address, int handle_breakpoints)
 652 {
 653         LOG_DEBUG("target->state: %s",
 654                 target_state_name(target));
 655
 656         if (target->state != TARGET_HALTED)
 657         {
 658                 LOG_WARNING("target was not halted");
 659                 return ERROR_TARGET_NOT_HALTED;
 660         }
 661
 662         struct arm11_common *arm11 = target_to_arm11(target);
 663
 664         address = arm11_nextpc(arm11, current, address);
 665
 666         LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
 667
 668
 669         /** \todo TODO: Thumb not supported here */
 670
 671         uint32_t        next_instruction;
 672
 673         CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
 674
 675         /* skip over BKPT */
 676         if ((next_instruction & 0xFFF00070) == 0xe1200070)
 677         {
 678                 address = arm11_nextpc(arm11, 0, address + 4);
 679                 LOG_DEBUG("Skipping BKPT");
 680         }
 681         /* skip over Wait for interrupt / Standby */
 682         /* mcr  15, 0, r?, cr7, cr0, {4} */
 683         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
 684         {
 685                 address = arm11_nextpc(arm11, 0, address + 4);
 686                 LOG_DEBUG("Skipping WFI");
 687         }
 688         /* ignore B to self */
 689         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
 690         {
 691                 LOG_DEBUG("Not stepping jump to self");
 692         }
 693         else
 694         {
 695                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
 696                 * with this. */
 697
 698                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
 699                 * the VCR might be something worth looking into. */
 700
 701
 702                 /* Set up breakpoint for stepping */
 703
 704                 struct arm11_sc7_action brp[2];
 705
 706                 brp[0].write    = 1;
 707                 brp[0].address  = ARM11_SC7_BVR0;
 708                 brp[1].write    = 1;
 709                 brp[1].address  = ARM11_SC7_BCR0;
 710
 711                 if (arm11_config_hardware_step)
 712                 {
 713                         /* Hardware single stepping ("instruction address
 714                          * mismatch") is used if enabled.  It's not quite
 715                          * exactly "run one instruction"; "branch to here"
 716                          * loops won't break, neither will some other cases,
 717                          * but it's probably the best default.
 718                          *
 719                          * Hardware single stepping isn't supported on v6
 720                          * debug modules.  ARM1176 and v7 can support it...
 721                          *
 722                          * FIXME Thumb stepping likely needs to use 0x03
 723                          * or 0xc0 byte masks, not 0x0f.
 724                          */
 725                          brp[0].value   = address;
 726                          brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5)
 727                                         | (0 << 14) | (0 << 16) | (0 << 20)
 728                                         | (2 << 21);
 729                 } else
 730                 {
 731                         /* Sets a breakpoint on the next PC, as calculated
 732                          * by instruction set simulation.
 733                          *
 734                          * REVISIT stepping Thumb on ARM1156 requires Thumb2
 735                          * support from the simulator.
 736                          */
 737                         uint32_t next_pc;
 738                         int retval;
 739
 740                         retval = arm_simulate_step(target, &next_pc);
 741                         if (retval != ERROR_OK)
 742                                 return retval;
 743
 744                         brp[0].value    = next_pc;
 745                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5)
 746                                         | (0 << 14) | (0 << 16) | (0 << 20)
 747                                         | (0 << 21);
 748                 }
 749
 750                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
 751
 752                 /* resume */
 753
 754
 755                 if (arm11_config_step_irq_enable)
 756                         R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;              /* should be redundant */
 757                 else
 758                         R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
 759
 760
 761                 CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
 762
 763                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 764
 765                 CHECK_RETVAL(jtag_execute_queue());
 766
 767                 /* wait for halt */
 768                 int i = 0;
 769                 uint32_t dscr;
 770
 771                 while (1)
 772                 {
 773                         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 774
 775                         LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
 776
 777                         if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
 778                                 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
 779                                 break;
 780
 781                         long long then = 0;
 782                         if (i == 1000)
 783                         {
 784                                 then = timeval_ms();
 785                         }
 786                         if (i >= 1000)
 787                         {
 788                                 if ((timeval_ms()-then) > 1000)
 789                                 {
 790                                         LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 791                                         return ERROR_FAIL;
 792                                 }
 793                         }
 794                         i++;
 795                 }
 796
 797                 /* clear breakpoint */
 798                 arm11_sc7_clear_vbw(arm11);
 799
 800                 /* save state */
 801                 CHECK_RETVAL(arm11_debug_entry(arm11, dscr));
 802
 803             /* restore default state */
 804                 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
 805
 806         }
 807
 808         target->debug_reason    = DBG_REASON_SINGLESTEP;
 809
 810         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 811
 812         return ERROR_OK;
 813 }
 814
 815 static int arm11_assert_reset(struct target *target)
 816 {
 817         int retval;
 818         struct arm11_common *arm11 = target_to_arm11(target);
 819
 820         retval = arm11_check_init(arm11, NULL);
 821         if (retval != ERROR_OK)
 822                 return retval;
 823
 824         target->state = TARGET_UNKNOWN;
 825
 826         /* we would very much like to reset into the halted, state,
 827          * but resetting and halting is second best... */
 828         if (target->reset_halt)
 829         {
 830                 CHECK_RETVAL(target_halt(target));
 831         }
 832
 833
 834         /* srst is funny. We can not do *anything* else while it's asserted
 835          * and it has unkonwn side effects. Make sure no other code runs
 836          * meanwhile.
 837          *
 838          * Code below assumes srst:
 839          *
 840          * - Causes power-on-reset (but of what parts of the system?). Bug
 841          * in arm11?
 842          *
 843          * - Messes us TAP state without asserting trst.
 844          *
 845          * - There is another bug in the arm11 core. When you generate an access to
 846          * external logic (for example ddr controller via AHB bus) and that block
 847          * is not configured (perhaps it is still held in reset), that transaction
 848          * will never complete. This will hang arm11 core but it will also hang
 849          * JTAG controller. Nothing, short of srst assertion will bring it out of
 850          * this.
 851          *
 852          * Mysteries:
 853          *
 854          * - What should the PC be after an srst reset when starting in the halted
 855          * state?
 856          */
 857
 858         jtag_add_reset(0, 1);
 859         jtag_add_reset(0, 0);
 860
 861         /* How long do we have to wait? */
 862         jtag_add_sleep(5000);
 863
 864         /* un-mess up TAP state */
 865         jtag_add_tlr();
 866
 867         retval = jtag_execute_queue();
 868         if (retval != ERROR_OK)
 869         {
 870                 return retval;
 871         }
 872
 873         return ERROR_OK;
 874 }
 875
 876 static int arm11_deassert_reset(struct target *target)
 877 {
 878         return ERROR_OK;
 879 }
 880
 881 static int arm11_soft_reset_halt(struct target *target)
 882 {
 883         LOG_WARNING("Not implemented: %s", __func__);
 884
 885         return ERROR_FAIL;
 886 }
 887
 888 /* target memory access
 889  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 890  * count: number of items of <size>
 891  *
 892  * arm11_config_memrw_no_increment - in the future we may want to be able
 893  * to read/write a range of data to a "port". a "port" is an action on
 894  * read memory address for some peripheral.
 895  */
 896 static int arm11_read_memory_inner(struct target *target,
 897                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
 898                 bool arm11_config_memrw_no_increment)
 899 {
 900         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
 901         int retval;
 902
 903         if (target->state != TARGET_HALTED)
 904         {
 905                 LOG_WARNING("target was not halted");
 906                 return ERROR_TARGET_NOT_HALTED;
 907         }
 908
 909         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 910
 911         struct arm11_common *arm11 = target_to_arm11(target);
 912
 913         retval = arm11_run_instr_data_prepare(arm11);
 914         if (retval != ERROR_OK)
 915                 return retval;
 916
 917         /* MRC p14,0,r0,c0,c5,0 */
 918         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
 919         if (retval != ERROR_OK)
 920                 return retval;
 921
 922         switch (size)
 923         {
 924         case 1:
 925                 arm11->arm.core_cache->reg_list[1].dirty = true;
 926
 927                 for (size_t i = 0; i < count; i++)
 928                 {
 929                         /* ldrb    r1, [r0], #1 */
 930                         /* ldrb    r1, [r0] */
 931                         arm11_run_instr_no_data1(arm11,
 932                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
 933
 934                         uint32_t res;
 935                         /* MCR p14,0,R1,c0,c5,0 */
 936                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 937
 938                         *buffer++ = res;
 939                 }
 940
 941                 break;
 942
 943         case 2:
 944                 {
 945                         arm11->arm.core_cache->reg_list[1].dirty = true;
 946
 947                         for (size_t i = 0; i < count; i++)
 948                         {
 949                                 /* ldrh    r1, [r0], #2 */
 950                                 arm11_run_instr_no_data1(arm11,
 951                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
 952
 953                                 uint32_t res;
 954
 955                                 /* MCR p14,0,R1,c0,c5,0 */
 956                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 957
 958                                 uint16_t svalue = res;
 959                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
 960                         }
 961
 962                         break;
 963                 }
 964
 965         case 4:
 966                 {
 967                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
 968                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
 969                 uint32_t *words = (uint32_t *)buffer;
 970
 971                 /* LDC p14,c5,[R0],#4 */
 972                 /* LDC p14,c5,[R0] */
 973                 arm11_run_instr_data_from_core(arm11, instr, words, count);
 974                 break;
 975                 }
 976         }
 977
 978         return arm11_run_instr_data_finish(arm11);
 979 }
 980
 981 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 982 {
 983         return arm11_read_memory_inner(target, address, size, count, buffer, false);
 984 }
 985
 986 /*
 987 * no_increment - in the future we may want to be able
 988 * to read/write a range of data to a "port". a "port" is an action on
 989 * read memory address for some peripheral.
 990 */
 991 static int arm11_write_memory_inner(struct target *target,
 992                 uint32_t address, uint32_t size,
 993                 uint32_t count, uint8_t *buffer,
 994                 bool no_increment)
 995 {
 996         int retval;
 997
 998         if (target->state != TARGET_HALTED)
 999         {
1000                 LOG_WARNING("target was not halted");
1001                 return ERROR_TARGET_NOT_HALTED;
1002         }
1003
1004         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1005
1006         struct arm11_common *arm11 = target_to_arm11(target);
1007
1008         retval = arm11_run_instr_data_prepare(arm11);
1009         if (retval != ERROR_OK)
1010                 return retval;
1011
1012         /* MRC p14,0,r0,c0,c5,0 */
1013         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1014         if (retval != ERROR_OK)
1015                 return retval;
1016
1017         /* burst writes are not used for single words as those may well be
1018          * reset init script writes.
1019          *
1020          * The other advantage is that as burst writes are default, we'll
1021          * now exercise both burst and non-burst code paths with the
1022          * default settings, increasing code coverage.
1023          */
1024         bool burst = arm11_config_memwrite_burst && (count > 1);
1025
1026         switch (size)
1027         {
1028         case 1:
1029                 {
1030                         arm11->arm.core_cache->reg_list[1].dirty = true;
1031
1032                         for (size_t i = 0; i < count; i++)
1033                         {
1034                                 /* MRC p14,0,r1,c0,c5,0 */
1035                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1036                                 if (retval != ERROR_OK)
1037                                         return retval;
1038
1039                                 /* strb    r1, [r0], #1 */
1040                                 /* strb    r1, [r0] */
1041                                 retval = arm11_run_instr_no_data1(arm11,
1042                                         !no_increment
1043                                                 ? 0xe4c01001
1044                                                 : 0xe5c01000);
1045                                 if (retval != ERROR_OK)
1046                                         return retval;
1047                         }
1048
1049                         break;
1050                 }
1051
1052         case 2:
1053                 {
1054                         arm11->arm.core_cache->reg_list[1].dirty = true;
1055
1056                         for (size_t i = 0; i < count; i++)
1057                         {
1058                                 uint16_t value;
1059                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1060
1061                                 /* MRC p14,0,r1,c0,c5,0 */
1062                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1063                                 if (retval != ERROR_OK)
1064                                         return retval;
1065
1066                                 /* strh    r1, [r0], #2 */
1067                                 /* strh    r1, [r0] */
1068                                 retval = arm11_run_instr_no_data1(arm11,
1069                                         !no_increment
1070                                                 ? 0xe0c010b2
1071                                                 : 0xe1c010b0);
1072                                 if (retval != ERROR_OK)
1073                                         return retval;
1074                         }
1075
1076                         break;
1077                 }
1078
1079         case 4: {
1080                 uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
1081
1082                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1083                 uint32_t *words = (uint32_t*)buffer;
1084
1085                 if (!burst)
1086                 {
1087                         /* STC p14,c5,[R0],#4 */
1088                         /* STC p14,c5,[R0]*/
1089                         retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1090                         if (retval != ERROR_OK)
1091                                 return retval;
1092                 }
1093                 else
1094                 {
1095                         /* STC p14,c5,[R0],#4 */
1096                         /* STC p14,c5,[R0]*/
1097                         retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1098                         if (retval != ERROR_OK)
1099                                 return retval;
1100                 }
1101
1102                 break;
1103         }
1104         }
1105
1106         /* r0 verification */
1107         if (!no_increment)
1108         {
1109                 uint32_t r0;
1110
1111                 /* MCR p14,0,R0,c0,c5,0 */
1112                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1113                 if (retval != ERROR_OK)
1114                         return retval;
1115
1116                 if (address + size * count != r0)
1117                 {
1118                         LOG_ERROR("Data transfer failed. Expected end "
1119                                         "address 0x%08x, got 0x%08x",
1120                                         (unsigned) (address + size * count),
1121                                         (unsigned) r0);
1122
1123                         if (burst)
1124                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1125
1126                         if (arm11_config_memwrite_error_fatal)
1127                                 return ERROR_FAIL;
1128                 }
1129         }
1130
1131         return arm11_run_instr_data_finish(arm11);
1132 }
1133
1134 static int arm11_write_memory(struct target *target,
1135                 uint32_t address, uint32_t size,
1136                 uint32_t count, uint8_t *buffer)
1137 {
1138         /* pointer increment matters only for multi-unit writes ...
1139          * not e.g. to a "reset the chip" controller.
1140          */
1141         return arm11_write_memory_inner(target, address, size,
1142                         count, buffer, count == 1);
1143 }
1144
1145 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1146 static int arm11_bulk_write_memory(struct target *target,
1147                 uint32_t address, uint32_t count, uint8_t *buffer)
1148 {
1149         if (target->state != TARGET_HALTED)
1150         {
1151                 LOG_WARNING("target was not halted");
1152                 return ERROR_TARGET_NOT_HALTED;
1153         }
1154
1155         return arm11_write_memory(target, address, 4, count, buffer);
1156 }
1157
1158 /* target break-/watchpoint control
1159 * rw: 0 = write, 1 = read, 2 = access
1160 */
1161 static int arm11_add_breakpoint(struct target *target,
1162                 struct breakpoint *breakpoint)
1163 {
1164         struct arm11_common *arm11 = target_to_arm11(target);
1165
1166 #if 0
1167         if (breakpoint->type == BKPT_SOFT)
1168         {
1169                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1170                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1171         }
1172 #endif
1173
1174         if (!arm11->free_brps)
1175         {
1176                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1177                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1178         }
1179
1180         if (breakpoint->length != 4)
1181         {
1182                 LOG_DEBUG("only breakpoints of four bytes length supported");
1183                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1184         }
1185
1186         arm11->free_brps--;
1187
1188         return ERROR_OK;
1189 }
1190
1191 static int arm11_remove_breakpoint(struct target *target,
1192                 struct breakpoint *breakpoint)
1193 {
1194         struct arm11_common *arm11 = target_to_arm11(target);
1195
1196         arm11->free_brps++;
1197
1198         return ERROR_OK;
1199 }
1200
1201 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1202 {
1203         struct arm11_common *arm11;
1204
1205         if (target->tap == NULL)
1206                 return ERROR_FAIL;
1207
1208         if (target->tap->ir_length != 5)
1209         {
1210                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1211                 return ERROR_COMMAND_SYNTAX_ERROR;
1212         }
1213
1214         arm11 = calloc(1, sizeof *arm11);
1215         if (!arm11)
1216                 return ERROR_FAIL;
1217
1218         armv4_5_init_arch_info(target, &arm11->arm);
1219
1220         arm11->jtag_info.tap = target->tap;
1221         arm11->jtag_info.scann_size = 5;
1222         arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1223         /* cur_scan_chain == 0 */
1224         arm11->jtag_info.intest_instr = ARM11_INTEST;
1225
1226         return ERROR_OK;
1227 }
1228
1229 static int arm11_init_target(struct command_context *cmd_ctx,
1230                 struct target *target)
1231 {
1232         /* Initialize anything we can set up without talking to the target */
1233
1234         /* REVISIT do we really want such a debug-registers-only cache?
1235          * If we do, it should probably be handled purely by the DPM code,
1236          * so it works identically on the v7a/v7r cores.
1237          */
1238         return arm11_build_reg_cache(target);
1239 }
1240
1241 /* talk to the target and set things up */
1242 static int arm11_examine(struct target *target)
1243 {
1244         int retval;
1245         char *type;
1246         struct arm11_common *arm11 = target_to_arm11(target);
1247         uint32_t didr, device_id;
1248         uint8_t implementor;
1249
1250         /* FIXME split into do-first-time and do-every-time logic ... */
1251
1252         /* check IDCODE */
1253
1254         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1255
1256         struct scan_field               idcode_field;
1257
1258         arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1259
1260         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1261
1262         /* check DIDR */
1263
1264         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1265
1266         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1267
1268         struct scan_field               chain0_fields[2];
1269
1270         arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1271         arm11_setup_field(arm11,  8, NULL, &implementor, chain0_fields + 1);
1272
1273         arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1274
1275         CHECK_RETVAL(jtag_execute_queue());
1276
1277         switch (device_id & 0x0FFFF000)
1278         {
1279         case 0x07B36000:
1280                 type = "ARM1136";
1281                 break;
1282         case 0x07B56000:
1283                 type = "ARM1156";
1284                 break;
1285         case 0x07B76000:
1286                 arm11->arm.core_type = ARM_MODE_MON;
1287                 type = "ARM1176";
1288                 break;
1289         default:
1290                 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1291                 return ERROR_FAIL;
1292         }
1293         LOG_INFO("found %s", type);
1294
1295         /* unlikely this could ever fail, but ... */
1296         switch ((didr >> 16) & 0x0F) {
1297         case ARM11_DEBUG_V6:
1298         case ARM11_DEBUG_V61:           /* supports security extensions */
1299                 break;
1300         default:
1301                 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1302                 return ERROR_FAIL;
1303         }
1304
1305         arm11->brp = ((didr >> 24) & 0x0F) + 1;
1306         arm11->wrp = ((didr >> 28) & 0x0F) + 1;
1307
1308         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1309         arm11->free_brps = arm11->brp;
1310
1311         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1312                         device_id, implementor, didr);
1313
1314         /* as a side-effect this reads DSCR and thus
1315          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1316          * as suggested by the spec.
1317          */
1318
1319         retval = arm11_check_init(arm11, NULL);
1320         if (retval != ERROR_OK)
1321                 return retval;
1322
1323         /* Build register cache "late", after target_init(), since we
1324          * want to know if this core supports Secure Monitor mode.
1325          */
1326         if (!target_was_examined(target))
1327                 retval = arm11_dpm_init(arm11, didr);
1328
1329         /* ETM on ARM11 still uses original scanchain 6 access mode */
1330         if (arm11->arm.etm && !target_was_examined(target)) {
1331                 *register_get_last_cache_p(&target->reg_cache) =
1332                         etm_build_reg_cache(target, &arm11->jtag_info,
1333                                         arm11->arm.etm);
1334                 retval = etm_setup(target);
1335         }
1336
1337         target_set_examined(target);
1338
1339         return ERROR_OK;
1340 }
1341
1342
1343 /** Load a register that is marked !valid in the register cache */
1344 static int arm11_get_reg(struct reg *reg)
1345 {
1346         struct arm11_reg_state *r = reg->arch_info;
1347         struct target *target = r->target;
1348
1349         if (target->state != TARGET_HALTED)
1350         {
1351                 LOG_WARNING("target was not halted");
1352                 return ERROR_TARGET_NOT_HALTED;
1353         }
1354
1355         /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1356
1357 #if 0
1358         struct arm11_common *arm11 = target_to_arm11(target);
1359         const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1360 #endif
1361
1362         return ERROR_OK;
1363 }
1364
1365 /** Change a value in the register cache */
1366 static int arm11_set_reg(struct reg *reg, uint8_t *buf)
1367 {
1368         struct arm11_reg_state *r = reg->arch_info;
1369         struct target *target = r->target;
1370         struct arm11_common *arm11 = target_to_arm11(target);
1371 //      const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1372
1373         arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1374         reg->valid      = 1;
1375         reg->dirty      = 1;
1376
1377         return ERROR_OK;
1378 }
1379
1380 static const struct reg_arch_type arm11_reg_type = {
1381         .get = arm11_get_reg,
1382         .set = arm11_set_reg,
1383 };
1384
1385 static int arm11_build_reg_cache(struct target *target)
1386 {
1387         struct arm11_common *arm11 = target_to_arm11(target);
1388         struct reg_cache *cache;
1389         struct reg *reg_list;
1390         struct arm11_reg_state *arm11_reg_states;
1391
1392         cache = calloc(1, sizeof *cache);
1393         reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list);
1394         arm11_reg_states = calloc(ARM11_REGCACHE_COUNT,
1395                         sizeof *arm11_reg_states);
1396         if (!cache || !reg_list || !arm11_reg_states) {
1397                 free(cache);
1398                 free(reg_list);
1399                 free(arm11_reg_states);
1400                 return ERROR_FAIL;
1401         }
1402
1403         arm11->reg_list = reg_list;
1404
1405         /* build cache for some of the debug registers */
1406         cache->name = "arm11 debug registers";
1407         cache->reg_list = reg_list;
1408         cache->num_regs = ARM11_REGCACHE_COUNT;
1409
1410         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1411         (*cache_p) = cache;
1412
1413         arm11->core_cache = cache;
1414
1415         size_t i;
1416
1417         /* Not very elegant assertion */
1418         if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
1419                 ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
1420                 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1421         {
1422                 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)",
1423                                 ARM11_REGCACHE_COUNT,
1424                                 (unsigned) ARRAY_SIZE(arm11->reg_values),
1425                                 (unsigned) ARRAY_SIZE(arm11_reg_defs),
1426                                 ARM11_RC_MAX);
1427                 /* FIXME minimally, use a build_bug_on(X) mechanism;
1428                  * runtime exit() here is bad!
1429                  */
1430                 exit(-1);
1431         }
1432
1433         for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1434         {
1435                 struct reg *                                            r       = reg_list                      + i;
1436                 const struct arm11_reg_defs *   rd      = arm11_reg_defs        + i;
1437                 struct arm11_reg_state *                        rs      = arm11_reg_states      + i;
1438
1439                 r->name                         = rd->name;
1440                 r->size                         = 32;
1441                 r->value                        = (uint8_t *)(arm11->reg_values + i);
1442                 r->dirty                        = 0;
1443                 r->valid                        = 0;
1444                 r->type = &arm11_reg_type;
1445                 r->arch_info            = rs;
1446
1447                 rs->def_index           = i;
1448                 rs->target                      = target;
1449         }
1450
1451         return ERROR_OK;
1452 }
1453
1454 /* FIXME all these BOOL_WRAPPER things should be modifying
1455  * per-instance state, not shared state; ditto the vector
1456  * catch register support.  Scan chains with multiple cores
1457  * should be able to say "work with this core like this,
1458  * that core like that".  Example, ARM11 MPCore ...
1459  */
1460
1461 #define ARM11_BOOL_WRAPPER(name, print_name)    \
1462                 COMMAND_HANDLER(arm11_handle_bool_##name) \
1463                 { \
1464                         return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1465                                         &arm11_config_##name, print_name); \
1466                 }
1467
1468 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1469 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1470 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1471 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1472
1473 COMMAND_HANDLER(arm11_handle_vcr)
1474 {
1475         switch (CMD_ARGC) {
1476         case 0:
1477                 break;
1478         case 1:
1479                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
1480                 break;
1481         default:
1482                 return ERROR_COMMAND_SYNTAX_ERROR;
1483         }
1484
1485         LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1486         return ERROR_OK;
1487 }
1488
1489 static const struct command_registration arm11_mw_command_handlers[] = {
1490         {
1491                 .name = "burst",
1492                 .handler = &arm11_handle_bool_memwrite_burst,
1493                 .mode = COMMAND_ANY,
1494                 .help = "Enable/Disable non-standard but fast burst mode"
1495                         " (default: enabled)",
1496         },
1497         {
1498                 .name = "error_fatal",
1499                 .handler = &arm11_handle_bool_memwrite_error_fatal,
1500                 .mode = COMMAND_ANY,
1501                 .help = "Terminate program if transfer error was found"
1502                         " (default: enabled)",
1503         },
1504         COMMAND_REGISTRATION_DONE
1505 };
1506 static const struct command_registration arm11_any_command_handlers[] = {
1507         {
1508                 /* "hardware_step" is only here to check if the default
1509                  * simulate + breakpoint implementation is broken.
1510                  * TEMPORARY! NOT DOCUMENTED! */
1511                 .name = "hardware_step",
1512                 .handler = &arm11_handle_bool_hardware_step,
1513                 .mode = COMMAND_ANY,
1514                 .help = "DEBUG ONLY - Hardware single stepping"
1515                         " (default: disabled)",
1516                 .usage = "(enable|disable)",
1517         },
1518         {
1519                 .name = "memwrite",
1520                 .mode = COMMAND_ANY,
1521                 .help = "memwrite command group",
1522                 .chain = arm11_mw_command_handlers,
1523         },
1524         {
1525                 .name = "step_irq_enable",
1526                 .handler = &arm11_handle_bool_step_irq_enable,
1527                 .mode = COMMAND_ANY,
1528                 .help = "Enable interrupts while stepping"
1529                         " (default: disabled)",
1530         },
1531         {
1532                 .name = "vcr",
1533                 .handler = &arm11_handle_vcr,
1534                 .mode = COMMAND_ANY,
1535                 .help = "Control (Interrupt) Vector Catch Register",
1536         },
1537         COMMAND_REGISTRATION_DONE
1538 };
1539 static const struct command_registration arm11_command_handlers[] = {
1540         {
1541                 .chain = arm_command_handlers,
1542         },
1543         {
1544                 .chain = etm_command_handlers,
1545         },
1546         {
1547                 .name = "arm11",
1548                 .mode = COMMAND_ANY,
1549                 .help = "ARM11 command group",
1550                 .chain = arm11_any_command_handlers,
1551         },
1552         COMMAND_REGISTRATION_DONE
1553 };
1554
1555 /** Holds methods for ARM11xx targets. */
1556 struct target_type arm11_target = {
1557         .name =                 "arm11",
1558
1559         .poll =                 arm11_poll,
1560         .arch_state =           arm11_arch_state,
1561
1562         .target_request_data =  arm11_target_request_data,
1563
1564         .halt =                 arm11_halt,
1565         .resume =               arm11_resume,
1566         .step =                 arm11_step,
1567
1568         .assert_reset =         arm11_assert_reset,
1569         .deassert_reset =       arm11_deassert_reset,
1570         .soft_reset_halt =      arm11_soft_reset_halt,
1571
1572         .get_gdb_reg_list =     armv4_5_get_gdb_reg_list,
1573
1574         .read_memory =          arm11_read_memory,
1575         .write_memory =         arm11_write_memory,
1576
1577         .bulk_write_memory =    arm11_bulk_write_memory,
1578
1579         .checksum_memory =      arm_checksum_memory,
1580         .blank_check_memory =   arm_blank_check_memory,
1581
1582         .add_breakpoint =       arm11_add_breakpoint,
1583         .remove_breakpoint =    arm11_remove_breakpoint,
1584
1585         .run_algorithm =        armv4_5_run_algorithm,
1586
1587         .commands =             arm11_command_handlers,
1588         .target_create =        arm11_target_create,
1589         .init_target =          arm11_init_target,
1590         .examine =              arm11_examine,
1591 };