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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *                                                                         *
   4  *   Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com              *
   5  *                                                                         *
   6  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "arm11.h"
  29 #include "jtag.h"
  30 #include "log.h"
  31
  32 #include <stdlib.h>
  33 #include <string.h>
  34
  35 #if 0
  36 #define _DEBUG_INSTRUCTION_EXECUTION_
  37 #endif
  38
  39 #if 0
  40 #define FNC_INFO        LOG_DEBUG("-")
  41 #else
  42 #define FNC_INFO
  43 #endif
  44
  45 #if 1
  46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
  47 #else
  48 #define FNC_INFO_NOTIMPLEMENTED
  49 #endif
  50
  51 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
  52
  53 bool    arm11_config_memwrite_burst                             = true;
  54 bool    arm11_config_memwrite_error_fatal               = true;
  55 u32             arm11_vcr                                                               = 0;
  56 bool    arm11_config_memrw_no_increment                 = false;
  57 bool    arm11_config_step_irq_enable                    = false;
  58
  59 #define ARM11_HANDLER(x)        \
  60         .x                              = arm11_##x
  61
  62 target_type_t arm11_target =
  63 {
  64         .name                   = "arm11",
  65
  66         ARM11_HANDLER(poll),
  67         ARM11_HANDLER(arch_state),
  68
  69         ARM11_HANDLER(target_request_data),
  70
  71         ARM11_HANDLER(halt),
  72         ARM11_HANDLER(resume),
  73         ARM11_HANDLER(step),
  74
  75         ARM11_HANDLER(assert_reset),
  76         ARM11_HANDLER(deassert_reset),
  77         ARM11_HANDLER(soft_reset_halt),
  78
  79         ARM11_HANDLER(get_gdb_reg_list),
  80
  81         ARM11_HANDLER(read_memory),
  82         ARM11_HANDLER(write_memory),
  83
  84         ARM11_HANDLER(bulk_write_memory),
  85
  86         ARM11_HANDLER(checksum_memory),
  87
  88         ARM11_HANDLER(add_breakpoint),
  89         ARM11_HANDLER(remove_breakpoint),
  90         ARM11_HANDLER(add_watchpoint),
  91         ARM11_HANDLER(remove_watchpoint),
  92
  93         ARM11_HANDLER(run_algorithm),
  94
  95         ARM11_HANDLER(register_commands),
  96         ARM11_HANDLER(target_create),
  97         ARM11_HANDLER(init_target),
  98         ARM11_HANDLER(examine),
  99         ARM11_HANDLER(quit),
 100 };
 101
 102 int arm11_regs_arch_type = -1;
 103
 104
 105 enum arm11_regtype
 106 {
 107         ARM11_REGISTER_CORE,
 108         ARM11_REGISTER_CPSR,
 109
 110         ARM11_REGISTER_FX,
 111         ARM11_REGISTER_FPS,
 112
 113         ARM11_REGISTER_FIQ,
 114         ARM11_REGISTER_SVC,
 115         ARM11_REGISTER_ABT,
 116         ARM11_REGISTER_IRQ,
 117         ARM11_REGISTER_UND,
 118         ARM11_REGISTER_MON,
 119
 120         ARM11_REGISTER_SPSR_FIQ,
 121         ARM11_REGISTER_SPSR_SVC,
 122         ARM11_REGISTER_SPSR_ABT,
 123         ARM11_REGISTER_SPSR_IRQ,
 124         ARM11_REGISTER_SPSR_UND,
 125         ARM11_REGISTER_SPSR_MON,
 126
 127         /* debug regs */
 128         ARM11_REGISTER_DSCR,
 129         ARM11_REGISTER_WDTR,
 130         ARM11_REGISTER_RDTR,
 131 };
 132
 133
 134 typedef struct arm11_reg_defs_s
 135 {
 136         char *                                  name;
 137         u32                                             num;
 138         int                                             gdb_num;
 139         enum arm11_regtype              type;
 140 } arm11_reg_defs_t;
 141
 142 /* update arm11_regcache_ids when changing this */
 143 static const arm11_reg_defs_t arm11_reg_defs[] =
 144 {
 145         {"r0",  0,      0,      ARM11_REGISTER_CORE},
 146         {"r1",  1,      1,      ARM11_REGISTER_CORE},
 147         {"r2",  2,      2,      ARM11_REGISTER_CORE},
 148         {"r3",  3,      3,      ARM11_REGISTER_CORE},
 149         {"r4",  4,      4,      ARM11_REGISTER_CORE},
 150         {"r5",  5,      5,      ARM11_REGISTER_CORE},
 151         {"r6",  6,      6,      ARM11_REGISTER_CORE},
 152         {"r7",  7,      7,      ARM11_REGISTER_CORE},
 153         {"r8",  8,      8,      ARM11_REGISTER_CORE},
 154         {"r9",  9,      9,      ARM11_REGISTER_CORE},
 155         {"r10", 10,     10,     ARM11_REGISTER_CORE},
 156         {"r11", 11,     11,     ARM11_REGISTER_CORE},
 157         {"r12", 12,     12,     ARM11_REGISTER_CORE},
 158         {"sp",  13,     13,     ARM11_REGISTER_CORE},
 159         {"lr",  14,     14,     ARM11_REGISTER_CORE},
 160         {"pc",  15,     15,     ARM11_REGISTER_CORE},
 161
 162 #if ARM11_REGCACHE_FREGS
 163         {"f0",  0,      16,     ARM11_REGISTER_FX},
 164         {"f1",  1,      17,     ARM11_REGISTER_FX},
 165         {"f2",  2,      18,     ARM11_REGISTER_FX},
 166         {"f3",  3,      19,     ARM11_REGISTER_FX},
 167         {"f4",  4,      20,     ARM11_REGISTER_FX},
 168         {"f5",  5,      21,     ARM11_REGISTER_FX},
 169         {"f6",  6,      22,     ARM11_REGISTER_FX},
 170         {"f7",  7,      23,     ARM11_REGISTER_FX},
 171         {"fps", 0,      24,     ARM11_REGISTER_FPS},
 172 #endif
 173
 174         {"cpsr",        0,      25,     ARM11_REGISTER_CPSR},
 175
 176 #if ARM11_REGCACHE_MODEREGS
 177         {"r8_fiq",      8,      -1,     ARM11_REGISTER_FIQ},
 178         {"r9_fiq",      9,      -1,     ARM11_REGISTER_FIQ},
 179         {"r10_fiq",     10,     -1,     ARM11_REGISTER_FIQ},
 180         {"r11_fiq",     11,     -1,     ARM11_REGISTER_FIQ},
 181         {"r12_fiq",     12,     -1,     ARM11_REGISTER_FIQ},
 182         {"r13_fiq",     13,     -1,     ARM11_REGISTER_FIQ},
 183         {"r14_fiq",     14,     -1,     ARM11_REGISTER_FIQ},
 184         {"spsr_fiq", 0, -1,     ARM11_REGISTER_SPSR_FIQ},
 185
 186         {"r13_svc",     13,     -1,     ARM11_REGISTER_SVC},
 187         {"r14_svc",     14,     -1,     ARM11_REGISTER_SVC},
 188         {"spsr_svc", 0, -1,     ARM11_REGISTER_SPSR_SVC},
 189
 190         {"r13_abt",     13,     -1,     ARM11_REGISTER_ABT},
 191         {"r14_abt",     14,     -1,     ARM11_REGISTER_ABT},
 192         {"spsr_abt", 0, -1,     ARM11_REGISTER_SPSR_ABT},
 193
 194         {"r13_irq",     13,     -1,     ARM11_REGISTER_IRQ},
 195         {"r14_irq",     14,     -1,     ARM11_REGISTER_IRQ},
 196         {"spsr_irq", 0, -1,     ARM11_REGISTER_SPSR_IRQ},
 197
 198         {"r13_und",     13,     -1,     ARM11_REGISTER_UND},
 199         {"r14_und",     14,     -1,     ARM11_REGISTER_UND},
 200         {"spsr_und", 0, -1,     ARM11_REGISTER_SPSR_UND},
 201
 202         /* ARM1176 only */
 203         {"r13_mon",     13,     -1,     ARM11_REGISTER_MON},
 204         {"r14_mon",     14,     -1,     ARM11_REGISTER_MON},
 205         {"spsr_mon", 0, -1,     ARM11_REGISTER_SPSR_MON},
 206 #endif
 207
 208         /* Debug Registers */
 209         {"dscr",        0,      -1,     ARM11_REGISTER_DSCR},
 210         {"wdtr",        0,      -1,     ARM11_REGISTER_WDTR},
 211         {"rdtr",        0,      -1,     ARM11_REGISTER_RDTR},
 212 };
 213
 214 enum arm11_regcache_ids
 215 {
 216         ARM11_RC_R0,
 217         ARM11_RC_RX                     = ARM11_RC_R0,
 218
 219         ARM11_RC_R1,
 220         ARM11_RC_R2,
 221         ARM11_RC_R3,
 222         ARM11_RC_R4,
 223         ARM11_RC_R5,
 224         ARM11_RC_R6,
 225         ARM11_RC_R7,
 226         ARM11_RC_R8,
 227         ARM11_RC_R9,
 228         ARM11_RC_R10,
 229         ARM11_RC_R11,
 230         ARM11_RC_R12,
 231         ARM11_RC_R13,
 232         ARM11_RC_SP                     = ARM11_RC_R13,
 233         ARM11_RC_R14,
 234         ARM11_RC_LR                     = ARM11_RC_R14,
 235         ARM11_RC_R15,
 236         ARM11_RC_PC                     = ARM11_RC_R15,
 237
 238 #if ARM11_REGCACHE_FREGS
 239         ARM11_RC_F0,
 240         ARM11_RC_FX                     = ARM11_RC_F0,
 241         ARM11_RC_F1,
 242         ARM11_RC_F2,
 243         ARM11_RC_F3,
 244         ARM11_RC_F4,
 245         ARM11_RC_F5,
 246         ARM11_RC_F6,
 247         ARM11_RC_F7,
 248         ARM11_RC_FPS,
 249 #endif
 250
 251         ARM11_RC_CPSR,
 252
 253 #if ARM11_REGCACHE_MODEREGS
 254         ARM11_RC_R8_FIQ,
 255         ARM11_RC_R9_FIQ,
 256         ARM11_RC_R10_FIQ,
 257         ARM11_RC_R11_FIQ,
 258         ARM11_RC_R12_FIQ,
 259         ARM11_RC_R13_FIQ,
 260         ARM11_RC_R14_FIQ,
 261         ARM11_RC_SPSR_FIQ,
 262
 263         ARM11_RC_R13_SVC,
 264         ARM11_RC_R14_SVC,
 265         ARM11_RC_SPSR_SVC,
 266
 267         ARM11_RC_R13_ABT,
 268         ARM11_RC_R14_ABT,
 269         ARM11_RC_SPSR_ABT,
 270
 271         ARM11_RC_R13_IRQ,
 272         ARM11_RC_R14_IRQ,
 273         ARM11_RC_SPSR_IRQ,
 274
 275         ARM11_RC_R13_UND,
 276         ARM11_RC_R14_UND,
 277         ARM11_RC_SPSR_UND,
 278
 279         ARM11_RC_R13_MON,
 280         ARM11_RC_R14_MON,
 281         ARM11_RC_SPSR_MON,
 282 #endif
 283
 284         ARM11_RC_DSCR,
 285         ARM11_RC_WDTR,
 286         ARM11_RC_RDTR,
 287
 288         ARM11_RC_MAX,
 289 };
 290
 291 #define ARM11_GDB_REGISTER_COUNT        26
 292
 293 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 294
 295 reg_t arm11_gdb_dummy_fp_reg =
 296 {
 297         "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 298 };
 299
 300 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 301
 302 reg_t arm11_gdb_dummy_fps_reg =
 303 {
 304         "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 305 };
 306
 307
 308
 309 /** Check and if necessary take control of the system
 310  *
 311  * \param arm11         Target state variable.
 312  * \param dscr          If the current DSCR content is
 313  *                                      available a pointer to a word holding the
 314  *                                      DSCR can be passed. Otherwise use NULL.
 315  */
 316 int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
 317 {
 318         FNC_INFO;
 319         int retval;
 320
 321         u32                     dscr_local_tmp_copy;
 322
 323         if (!dscr)
 324         {
 325                 dscr = &dscr_local_tmp_copy;
 326                 if ((retval=arm11_read_DSCR(arm11, dscr))!=ERROR_OK)
 327                         return retval;
 328         }
 329
 330         if (!(*dscr & ARM11_DSCR_MODE_SELECT))
 331         {
 332                 LOG_DEBUG("Bringing target into debug mode");
 333
 334                 *dscr |= ARM11_DSCR_MODE_SELECT;                /* Halt debug-mode */
 335                 arm11_write_DSCR(arm11, *dscr);
 336
 337                 /* add further reset initialization here */
 338
 339                 arm11->simulate_reset_on_next_halt = true;
 340
 341                 if (*dscr & ARM11_DSCR_CORE_HALTED)
 342                 {
 343                         /** \todo TODO: this needs further scrutiny because
 344                           * arm11_on_enter_debug_state() never gets properly called
 345                           */
 346
 347                         arm11->target->state    = TARGET_HALTED;
 348                         arm11->target->debug_reason     = arm11_get_DSCR_debug_reason(*dscr);
 349                 }
 350                 else
 351                 {
 352                         arm11->target->state    = TARGET_RUNNING;
 353                         arm11->target->debug_reason     = DBG_REASON_NOTHALTED;
 354                 }
 355
 356                 arm11_sc7_clear_vbw(arm11);
 357         }
 358
 359         return ERROR_OK;
 360 }
 361
 362
 363
 364 #define R(x) \
 365         (arm11->reg_values[ARM11_RC_##x])
 366
 367 /** Save processor state.
 368   *
 369   * This is called when the HALT instruction has succeeded
 370   * or on other occasions that stop the processor.
 371   *
 372   */
 373 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 374 {
 375         FNC_INFO;
 376
 377         {size_t i;
 378         for(i = 0; i < asizeof(arm11->reg_values); i++)
 379         {
 380                 arm11->reg_list[i].valid        = 1;
 381                 arm11->reg_list[i].dirty        = 0;
 382         }}
 383
 384         /* Save DSCR */
 385         int retval;
 386         if ((retval=arm11_read_DSCR(arm11, &R(DSCR)))!=ERROR_OK)
 387                 return retval;
 388
 389         /* Save wDTR */
 390
 391         if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
 392         {
 393                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 394
 395                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 396
 397                 scan_field_t    chain5_fields[3];
 398
 399                 arm11_setup_field(arm11, 32, NULL, &R(WDTR),    chain5_fields + 0);
 400                 arm11_setup_field(arm11,  1, NULL, NULL,        chain5_fields + 1);
 401                 arm11_setup_field(arm11,  1, NULL, NULL,        chain5_fields + 2);
 402
 403                 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 404         }
 405         else
 406         {
 407                 arm11->reg_list[ARM11_RC_WDTR].valid    = 0;
 408         }
 409
 410
 411         /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
 412         /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
 413            ARM1136 seems to require this to issue ITR's as well */
 414
 415         u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
 416
 417         /* this executes JTAG queue: */
 418
 419         arm11_write_DSCR(arm11, new_dscr);
 420
 421
 422         /* From the spec:
 423            Before executing any instruction in debug state you have to drain the write buffer.
 424            This ensures that no imprecise Data Aborts can return at a later point:*/
 425
 426         /** \todo TODO: Test drain write buffer. */
 427
 428 #if 0
 429         while (1)
 430         {
 431                 /* MRC p14,0,R0,c5,c10,0 */
 432                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 433
 434                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 435                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 436
 437                 u32 dscr = arm11_read_DSCR(arm11);
 438
 439                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 440
 441                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 442                 {
 443                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 444
 445                         dscr = arm11_read_DSCR(arm11);
 446
 447                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 448
 449                         break;
 450                 }
 451         }
 452 #endif
 453
 454         arm11_run_instr_data_prepare(arm11);
 455
 456         /* save r0 - r14 */
 457
 458         /** \todo TODO: handle other mode registers */
 459
 460         {size_t i;
 461         for (i = 0; i < 15; i++)
 462         {
 463                 /* MCR p14,0,R?,c0,c5,0 */
 464                 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
 465         }}
 466
 467         /* save rDTR */
 468
 469         /* check rDTRfull in DSCR */
 470
 471         if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
 472         {
 473                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 474                 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
 475         }
 476         else
 477         {
 478                 arm11->reg_list[ARM11_RC_RDTR].valid    = 0;
 479         }
 480
 481         /* save CPSR */
 482
 483         /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
 484         arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
 485
 486         /* save PC */
 487
 488         /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
 489         arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
 490
 491         /* adjust PC depending on ARM state */
 492
 493         if (R(CPSR) & ARM11_CPSR_J)     /* Java state */
 494         {
 495                 arm11->reg_values[ARM11_RC_PC] -= 0;
 496         }
 497         else if (R(CPSR) & ARM11_CPSR_T)        /* Thumb state */
 498         {
 499                 arm11->reg_values[ARM11_RC_PC] -= 4;
 500         }
 501         else                                    /* ARM state */
 502         {
 503                 arm11->reg_values[ARM11_RC_PC] -= 8;
 504         }
 505
 506         if (arm11->simulate_reset_on_next_halt)
 507         {
 508                 arm11->simulate_reset_on_next_halt = false;
 509
 510                 LOG_DEBUG("Reset c1 Control Register");
 511
 512                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 513
 514                 /* MCR p15,0,R0,c1,c0,0 */
 515                 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 516
 517         }
 518
 519         arm11_run_instr_data_finish(arm11);
 520
 521         arm11_dump_reg_changes(arm11);
 522
 523         return ERROR_OK;
 524 }
 525
 526 void arm11_dump_reg_changes(arm11_common_t * arm11)
 527 {
 528         {size_t i;
 529         for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
 530         {
 531                 if (!arm11->reg_list[i].valid)
 532                 {
 533                         if (arm11->reg_history[i].valid)
 534                                 LOG_INFO("%8s INVALID    (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
 535                 }
 536                 else
 537                 {
 538                         if (arm11->reg_history[i].valid)
 539                         {
 540                                 if (arm11->reg_history[i].value != arm11->reg_values[i])
 541                                         LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
 542                         }
 543                         else
 544                         {
 545                                 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
 546                         }
 547                 }
 548         }}
 549 }
 550
 551 /** Restore processor state
 552   *
 553   * This is called in preparation for the RESTART function.
 554   *
 555   */
 556 int arm11_leave_debug_state(arm11_common_t * arm11)
 557 {
 558         FNC_INFO;
 559
 560         arm11_run_instr_data_prepare(arm11);
 561
 562         /** \todo TODO: handle other mode registers */
 563
 564         /* restore R1 - R14 */
 565         {size_t i;
 566         for (i = 1; i < 15; i++)
 567         {
 568                 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
 569                         continue;
 570
 571                 /* MRC p14,0,r?,c0,c5,0 */
 572                 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
 573
 574                 //      LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
 575         }}
 576
 577         arm11_run_instr_data_finish(arm11);
 578
 579         /* spec says clear wDTR and rDTR; we assume they are clear as
 580            otherwise our programming would be sloppy */
 581         {
 582                 u32 DSCR;
 583                 int retval;
 584                 if ((retval=arm11_read_DSCR(arm11, &DSCR))!=ERROR_OK)
 585                 {
 586                         return retval;
 587                 }
 588
 589                 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 590                 {
 591                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
 592                 }
 593         }
 594
 595         arm11_run_instr_data_prepare(arm11);
 596
 597         /* restore original wDTR */
 598
 599         if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
 600         {
 601                 /* MCR p14,0,R0,c0,c5,0 */
 602                 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
 603         }
 604
 605         /* restore CPSR */
 606
 607         /* MSR CPSR,R0*/
 608         arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
 609
 610         /* restore PC */
 611
 612         /* MOV PC,R0 */
 613         arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
 614
 615         /* restore R0 */
 616
 617         /* MRC p14,0,r0,c0,c5,0 */
 618         arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
 619
 620         arm11_run_instr_data_finish(arm11);
 621
 622         /* restore DSCR */
 623
 624         arm11_write_DSCR(arm11, R(DSCR));
 625
 626         /* restore rDTR */
 627
 628         if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
 629         {
 630                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 631
 632                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 633
 634                 scan_field_t    chain5_fields[3];
 635
 636                 u8                      Ready           = 0;    /* ignored */
 637                 u8                      Valid           = 0;    /* ignored */
 638
 639                 arm11_setup_field(arm11, 32, &R(RDTR),  NULL, chain5_fields + 0);
 640                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 641                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 642
 643                 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 644         }
 645
 646         arm11_record_register_history(arm11);
 647
 648         return ERROR_OK;
 649 }
 650
 651 void arm11_record_register_history(arm11_common_t * arm11)
 652 {
 653         {size_t i;
 654         for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
 655         {
 656                 arm11->reg_history[i].value     = arm11->reg_values[i];
 657                 arm11->reg_history[i].valid     = arm11->reg_list[i].valid;
 658
 659                 arm11->reg_list[i].valid        = 0;
 660                 arm11->reg_list[i].dirty        = 0;
 661         }}
 662 }
 663
 664
 665 /* poll current target status */
 666 int arm11_poll(struct target_s *target)
 667 {
 668         FNC_INFO;
 669
 670         arm11_common_t * arm11 = target->arch_info;
 671
 672         if (arm11->trst_active)
 673                 return ERROR_OK;
 674
 675         u32     dscr;
 676         int retval;
 677         if ((retval=arm11_read_DSCR(arm11, &dscr))!=ERROR_OK)
 678                 return retval;
 679
 680         LOG_DEBUG("DSCR %08x", dscr);
 681
 682         if ((retval=arm11_check_init(arm11, &dscr))!=ERROR_OK)
 683                 return retval;
 684
 685         if (dscr & ARM11_DSCR_CORE_HALTED)
 686         {
 687                 if (target->state != TARGET_HALTED)
 688                 {
 689                         enum target_state old_state = target->state;
 690
 691                         LOG_DEBUG("enter TARGET_HALTED");
 692                         target->state           = TARGET_HALTED;
 693                         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 694                         arm11_on_enter_debug_state(arm11);
 695
 696                         target_call_event_callbacks(target,
 697                                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
 698                 }
 699         }
 700         else
 701         {
 702                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 703                 {
 704                         LOG_DEBUG("enter TARGET_RUNNING");
 705                         target->state           = TARGET_RUNNING;
 706                         target->debug_reason    = DBG_REASON_NOTHALTED;
 707                 }
 708         }
 709
 710         return ERROR_OK;
 711 }
 712 /* architecture specific status reply */
 713 int arm11_arch_state(struct target_s *target)
 714 {
 715         FNC_INFO_NOTIMPLEMENTED;
 716
 717         return ERROR_OK;
 718 }
 719
 720 /* target request support */
 721 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
 722 {
 723         FNC_INFO_NOTIMPLEMENTED;
 724
 725         return ERROR_OK;
 726 }
 727
 728 /* target execution control */
 729 int arm11_halt(struct target_s *target)
 730 {
 731         int retval = ERROR_OK;
 732
 733         FNC_INFO;
 734
 735         arm11_common_t * arm11 = target->arch_info;
 736
 737         LOG_DEBUG("target->state: %s",
 738                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
 739
 740         if (target->state == TARGET_UNKNOWN)
 741         {
 742                 arm11->simulate_reset_on_next_halt = true;
 743         }
 744
 745         if (target->state == TARGET_HALTED)
 746         {
 747                 LOG_DEBUG("target was already halted");
 748                 return ERROR_OK;
 749         }
 750
 751         if (arm11->trst_active)
 752         {
 753                 arm11->halt_requested = true;
 754                 return ERROR_OK;
 755         }
 756
 757         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 758
 759         if((retval = jtag_execute_queue()) != ERROR_OK)
 760         {
 761                 return retval;
 762         }
 763
 764         u32 dscr;
 765
 766         while (1)
 767         {
 768                 int retval;
 769                 retval = arm11_read_DSCR(arm11, &dscr);
 770                 if (retval!=ERROR_OK)
 771                         return retval;
 772
 773                 if (dscr & ARM11_DSCR_CORE_HALTED)
 774                         break;
 775         }
 776
 777         arm11_on_enter_debug_state(arm11);
 778
 779         enum target_state old_state     = target->state;
 780
 781         target->state           = TARGET_HALTED;
 782         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 783
 784         if((retval = target_call_event_callbacks(target,
 785                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
 786         {
 787                 return retval;
 788         }
 789
 790         return ERROR_OK;
 791 }
 792
 793 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
 794 {
 795         int retval = ERROR_OK;
 796
 797         FNC_INFO;
 798
 799         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 800         //      current, address, handle_breakpoints, debug_execution);
 801
 802         arm11_common_t * arm11 = target->arch_info;
 803
 804         LOG_DEBUG("target->state: %s",
 805                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
 806
 807
 808         if (target->state != TARGET_HALTED)
 809         {
 810                 LOG_ERROR("Target not halted");
 811                 return ERROR_TARGET_NOT_HALTED;
 812         }
 813
 814         if (!current)
 815                 R(PC) = address;
 816
 817         LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
 818
 819         /* clear breakpoints/watchpoints and VCR*/
 820         arm11_sc7_clear_vbw(arm11);
 821
 822         /* Set up breakpoints */
 823         if (!debug_execution)
 824         {
 825                 /* check if one matches PC and step over it if necessary */
 826
 827                 breakpoint_t *  bp;
 828
 829                 for (bp = target->breakpoints; bp; bp = bp->next)
 830                 {
 831                         if (bp->address == R(PC))
 832                         {
 833                                 LOG_DEBUG("must step over %08x", bp->address);
 834                                 arm11_step(target, 1, 0, 0);
 835                                 break;
 836                         }
 837                 }
 838
 839                 /* set all breakpoints */
 840
 841                 size_t          brp_num = 0;
 842
 843                 for (bp = target->breakpoints; bp; bp = bp->next)
 844                 {
 845                         arm11_sc7_action_t      brp[2];
 846
 847                         brp[0].write    = 1;
 848                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 849                         brp[0].value    = bp->address;
 850                         brp[1].write    = 1;
 851                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 852                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 853
 854                         arm11_sc7_run(arm11, brp, asizeof(brp));
 855
 856                         LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
 857
 858                         brp_num++;
 859                 }
 860
 861                 arm11_sc7_set_vcr(arm11, arm11_vcr);
 862         }
 863
 864         arm11_leave_debug_state(arm11);
 865
 866         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 867
 868         if((retval = jtag_execute_queue()) != ERROR_OK)
 869         {
 870                 return retval;
 871         }
 872
 873         while (1)
 874         {
 875                 u32 dscr;
 876                 retval = arm11_read_DSCR(arm11, &dscr);
 877                 if (retval!=ERROR_OK)
 878                         return retval;
 879
 880                 LOG_DEBUG("DSCR %08x", dscr);
 881
 882                 if (dscr & ARM11_DSCR_CORE_RESTARTED)
 883                         break;
 884         }
 885
 886         if (!debug_execution)
 887         {
 888                 target->state                   = TARGET_RUNNING;
 889                 target->debug_reason    = DBG_REASON_NOTHALTED;
 890
 891                 if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
 892                 {
 893                         return retval;
 894                 }
 895         }
 896         else
 897         {
 898                 target->state                   = TARGET_DEBUG_RUNNING;
 899                 target->debug_reason    = DBG_REASON_NOTHALTED;
 900                 if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
 901                 {
 902                         return retval;
 903                 }
 904         }
 905
 906         return ERROR_OK;
 907 }
 908
 909 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
 910 {
 911         int retval = ERROR_OK;
 912
 913         FNC_INFO;
 914
 915         LOG_DEBUG("target->state: %s",
 916                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
 917
 918         if (target->state != TARGET_HALTED)
 919         {
 920                 LOG_WARNING("target was not halted");
 921                 return ERROR_TARGET_NOT_HALTED;
 922         }
 923
 924         arm11_common_t * arm11 = target->arch_info;
 925
 926         if (!current)
 927                 R(PC) = address;
 928
 929         LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
 930
 931         /** \todo TODO: Thumb not supported here */
 932
 933         u32     next_instruction;
 934
 935         arm11_read_memory_word(arm11, R(PC), &next_instruction);
 936
 937         /* skip over BKPT */
 938         if ((next_instruction & 0xFFF00070) == 0xe1200070)
 939         {
 940                 R(PC) += 4;
 941                 arm11->reg_list[ARM11_RC_PC].valid = 1;
 942                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
 943                 LOG_INFO("Skipping BKPT");
 944         }
 945         /* skip over Wait for interrupt / Standby */
 946         /* mcr  15, 0, r?, cr7, cr0, {4} */
 947         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
 948         {
 949                 R(PC) += 4;
 950                 arm11->reg_list[ARM11_RC_PC].valid = 1;
 951                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
 952                 LOG_INFO("Skipping WFI");
 953         }
 954         /* ignore B to self */
 955         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
 956         {
 957                 LOG_INFO("Not stepping jump to self");
 958         }
 959         else
 960         {
 961                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
 962                 * with this. */
 963
 964                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
 965                 * the VCR might be something worth looking into. */
 966
 967
 968                 /* Set up breakpoint for stepping */
 969
 970                 arm11_sc7_action_t      brp[2];
 971
 972                 brp[0].write    = 1;
 973                 brp[0].address  = ARM11_SC7_BVR0;
 974                 brp[0].value    = R(PC);
 975                 brp[1].write    = 1;
 976                 brp[1].address  = ARM11_SC7_BCR0;
 977                 brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
 978
 979                 arm11_sc7_run(arm11, brp, asizeof(brp));
 980
 981                 /* resume */
 982
 983
 984                 if (arm11_config_step_irq_enable)
 985                         R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;              /* should be redundant */
 986                 else
 987                         R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
 988
 989
 990                 arm11_leave_debug_state(arm11);
 991
 992                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 993
 994                 if((retval = jtag_execute_queue()) != ERROR_OK)
 995                 {
 996                         return retval;
 997                 }
 998
 999                 /** \todo TODO: add a timeout */
1000
1001                 /* wait for halt */
1002
1003                 while (1)
1004                 {
1005                         u32 dscr;
1006                         retval = arm11_read_DSCR(arm11, &dscr);
1007                         if (retval!=ERROR_OK)
1008                                 return retval;
1009
1010                         LOG_DEBUG("DSCR %08x", dscr);
1011
1012                         if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1013                                 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1014                                 break;
1015                 }
1016
1017                 /* clear breakpoint */
1018                 arm11_sc7_clear_vbw(arm11);
1019
1020                 /* save state */
1021                 arm11_on_enter_debug_state(arm11);
1022
1023             /* restore default state */
1024                 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1025
1026         }
1027
1028         //        target->state         = TARGET_HALTED;
1029         target->debug_reason    = DBG_REASON_SINGLESTEP;
1030
1031         if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1032         {
1033                 return retval;
1034         }
1035
1036         return ERROR_OK;
1037 }
1038
1039 /* target reset control */
1040 int arm11_assert_reset(struct target_s *target)
1041 {
1042         FNC_INFO;
1043
1044 #if 0
1045         /* assert reset lines */
1046         /* resets only the DBGTAP, not the ARM */
1047
1048         jtag_add_reset(1, 0);
1049         jtag_add_sleep(5000);
1050
1051         arm11_common_t * arm11 = target->arch_info;
1052         arm11->trst_active = true;
1053 #endif
1054
1055         if (target->reset_halt)
1056         {
1057                 int retval;
1058                 if ((retval = target_halt(target))!=ERROR_OK)
1059                         return retval;
1060         }
1061
1062         return ERROR_OK;
1063 }
1064
1065 int arm11_deassert_reset(struct target_s *target)
1066 {
1067         FNC_INFO;
1068
1069 #if 0
1070         LOG_DEBUG("target->state: %s",
1071                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
1072
1073
1074         /* deassert reset lines */
1075         jtag_add_reset(0, 0);
1076
1077         arm11_common_t * arm11 = target->arch_info;
1078         arm11->trst_active = false;
1079
1080         if (arm11->halt_requested)
1081                 return arm11_halt(target);
1082 #endif
1083
1084         return ERROR_OK;
1085 }
1086
1087 int arm11_soft_reset_halt(struct target_s *target)
1088 {
1089         FNC_INFO_NOTIMPLEMENTED;
1090
1091         return ERROR_OK;
1092 }
1093
1094 /* target register access for gdb */
1095 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1096 {
1097         FNC_INFO;
1098
1099         arm11_common_t * arm11 = target->arch_info;
1100
1101         *reg_list_size  = ARM11_GDB_REGISTER_COUNT;
1102         *reg_list               = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1103
1104         {size_t i;
1105         for (i = 16; i < 24; i++)
1106         {
1107                 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1108         }}
1109
1110         (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1111
1112         {size_t i;
1113         for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1114         {
1115                 if (arm11_reg_defs[i].gdb_num == -1)
1116                         continue;
1117
1118                 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1119         }}
1120
1121         return ERROR_OK;
1122 }
1123
1124 /* target memory access
1125  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1126  * count: number of items of <size>
1127  */
1128 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1129 {
1130         /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1131
1132         FNC_INFO;
1133
1134         if (target->state != TARGET_HALTED)
1135         {
1136                 LOG_WARNING("target was not halted");
1137                 return ERROR_TARGET_NOT_HALTED;
1138         }
1139
1140         LOG_DEBUG("ADDR %08x  SIZE %08x  COUNT %08x", address, size, count);
1141
1142         arm11_common_t * arm11 = target->arch_info;
1143
1144         arm11_run_instr_data_prepare(arm11);
1145
1146         /* MRC p14,0,r0,c0,c5,0 */
1147         arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1148
1149         switch (size)
1150         {
1151         case 1:
1152                 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1153                 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1154
1155                 {size_t i;
1156                 for (i = 0; i < count; i++)
1157                 {
1158                         /* ldrb    r1, [r0], #1 */
1159                         /* ldrb    r1, [r0] */
1160                         arm11_run_instr_no_data1(arm11,
1161                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1162
1163                         u32 res;
1164                         /* MCR p14,0,R1,c0,c5,0 */
1165                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1166
1167                         *buffer++ = res;
1168                 }}
1169
1170                 break;
1171
1172         case 2:
1173                 {
1174                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1175
1176                         u16 * buf16 = (u16*)buffer;
1177
1178                         {size_t i;
1179                         for (i = 0; i < count; i++)
1180                         {
1181                                 /* ldrh    r1, [r0], #2 */
1182                                 arm11_run_instr_no_data1(arm11,
1183                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1184
1185                                 u32 res;
1186
1187                                 /* MCR p14,0,R1,c0,c5,0 */
1188                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1189
1190                                 *buf16++ = res;
1191                         }}
1192
1193                         break;
1194                 }
1195
1196         case 4:
1197
1198                 /* LDC p14,c5,[R0],#4 */
1199                 /* LDC p14,c5,[R0] */
1200                 arm11_run_instr_data_from_core(arm11,
1201                         (!arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00),
1202                         (u32 *)buffer, count);
1203                 break;
1204         }
1205
1206         arm11_run_instr_data_finish(arm11);
1207
1208         return ERROR_OK;
1209 }
1210
1211 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1212 {
1213         FNC_INFO;
1214
1215         if (target->state != TARGET_HALTED)
1216         {
1217                 LOG_WARNING("target was not halted");
1218                 return ERROR_TARGET_NOT_HALTED;
1219         }
1220
1221         LOG_DEBUG("ADDR %08x  SIZE %08x  COUNT %08x", address, size, count);
1222
1223         arm11_common_t * arm11 = target->arch_info;
1224
1225         arm11_run_instr_data_prepare(arm11);
1226
1227         /* MRC p14,0,r0,c0,c5,0 */
1228         arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1229
1230         switch (size)
1231         {
1232         case 1:
1233                 {
1234                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1235
1236                         {size_t i;
1237                         for (i = 0; i < count; i++)
1238                         {
1239                                 /* MRC p14,0,r1,c0,c5,0 */
1240                                 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1241
1242                                 /* strb    r1, [r0], #1 */
1243                                 /* strb    r1, [r0] */
1244                                 arm11_run_instr_no_data1(arm11,
1245                                         !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1246                         }}
1247
1248                         break;
1249                 }
1250
1251         case 2:
1252                 {
1253                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1254
1255                         u16 * buf16 = (u16*)buffer;
1256
1257                         {size_t i;
1258                         for (i = 0; i < count; i++)
1259                         {
1260                                 /* MRC p14,0,r1,c0,c5,0 */
1261                                 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1262
1263                                 /* strh    r1, [r0], #2 */
1264                                 /* strh    r1, [r0] */
1265                                 arm11_run_instr_no_data1(arm11,
1266                                         !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1267                         }}
1268
1269                         break;
1270                 }
1271
1272         case 4:
1273                 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1274
1275                 if (!arm11_config_memwrite_burst)
1276                 {
1277                         /* STC p14,c5,[R0],#4 */
1278                         /* STC p14,c5,[R0]*/
1279                         arm11_run_instr_data_to_core(arm11,
1280                                 (!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
1281                                 (u32 *)buffer, count);
1282                 }
1283                 else
1284                 {
1285                         /* STC p14,c5,[R0],#4 */
1286                         /* STC p14,c5,[R0]*/
1287                         arm11_run_instr_data_to_core_noack(arm11,
1288                                 (!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
1289                                 (u32 *)buffer, count);
1290                 }
1291
1292                 break;
1293         }
1294
1295 #if 1
1296         /* r0 verification */
1297         if (!arm11_config_memrw_no_increment)
1298         {
1299                 u32 r0;
1300
1301                 /* MCR p14,0,R0,c0,c5,0 */
1302                 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1303
1304                 if (address + size * count != r0)
1305                 {
1306                         LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1307
1308                         if (arm11_config_memwrite_burst)
1309                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1310
1311                         if (arm11_config_memwrite_error_fatal)
1312                                 return ERROR_FAIL;
1313                 }
1314         }
1315 #endif
1316
1317         arm11_run_instr_data_finish(arm11);
1318
1319         return ERROR_OK;
1320 }
1321
1322
1323 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1324 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1325 {
1326         FNC_INFO;
1327
1328         if (target->state != TARGET_HALTED)
1329         {
1330                 LOG_WARNING("target was not halted");
1331                 return ERROR_TARGET_NOT_HALTED;
1332         }
1333
1334         return arm11_write_memory(target, address, 4, count, buffer);
1335 }
1336
1337 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1338 {
1339         FNC_INFO_NOTIMPLEMENTED;
1340
1341         return ERROR_OK;
1342 }
1343
1344 /* target break-/watchpoint control
1345 * rw: 0 = write, 1 = read, 2 = access
1346 */
1347 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1348 {
1349         FNC_INFO;
1350
1351         arm11_common_t * arm11 = target->arch_info;
1352
1353 #if 0
1354         if (breakpoint->type == BKPT_SOFT)
1355         {
1356                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1357                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1358         }
1359 #endif
1360
1361         if (!arm11->free_brps)
1362         {
1363                 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1364                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1365         }
1366
1367         if (breakpoint->length != 4)
1368         {
1369                 LOG_INFO("only breakpoints of four bytes length supported");
1370                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1371         }
1372
1373         arm11->free_brps--;
1374
1375         return ERROR_OK;
1376 }
1377
1378 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1379 {
1380         FNC_INFO;
1381
1382         arm11_common_t * arm11 = target->arch_info;
1383
1384         arm11->free_brps++;
1385
1386         return ERROR_OK;
1387 }
1388
1389 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1390 {
1391         FNC_INFO_NOTIMPLEMENTED;
1392
1393         return ERROR_OK;
1394 }
1395
1396 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1397 {
1398         FNC_INFO_NOTIMPLEMENTED;
1399
1400         return ERROR_OK;
1401 }
1402
1403 // HACKHACKHACK - FIXME mode/state
1404 /* target algorithm support */
1405 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1406                         int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
1407                         int timeout_ms, void *arch_info)
1408 {
1409                 arm11_common_t *arm11 = target->arch_info;
1410         armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
1411 //      enum armv4_5_state core_state = arm11->core_state;
1412 //      enum armv4_5_mode core_mode = arm11->core_mode;
1413         u32 context[16];
1414         u32 cpsr;
1415         int exit_breakpoint_size = 0;
1416         int i;
1417         int retval = ERROR_OK;
1418                 LOG_DEBUG("Running algorithm");
1419
1420         if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
1421         {
1422                 LOG_ERROR("current target isn't an ARMV4/5 target");
1423                 return ERROR_TARGET_INVALID;
1424         }
1425
1426         if (target->state != TARGET_HALTED)
1427         {
1428                 LOG_WARNING("target not halted");
1429                 return ERROR_TARGET_NOT_HALTED;
1430         }
1431
1432         // FIXME
1433 //      if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1434 //              return ERROR_FAIL;
1435
1436         // Save regs
1437         for (i = 0; i < 16; i++)
1438         {
1439                 context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
1440                 LOG_DEBUG("Save %i: 0x%x",i,context[i]);
1441         }
1442
1443         cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
1444         LOG_DEBUG("Save CPSR: 0x%x", cpsr);
1445
1446         for (i = 0; i < num_mem_params; i++)
1447         {
1448                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1449         }
1450
1451         // Set register parameters
1452         for (i = 0; i < num_reg_params; i++)
1453         {
1454                 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1455                 if (!reg)
1456                 {
1457                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1458                         exit(-1);
1459                 }
1460
1461                 if (reg->size != reg_params[i].size)
1462                 {
1463                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1464                         exit(-1);
1465                 }
1466                 arm11_set_reg(reg,reg_params[i].value);
1467 //              printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1468         }
1469
1470         exit_breakpoint_size = 4;
1471
1472 /*      arm11->core_state = arm11_algorithm_info->core_state;
1473         if (arm11->core_state == ARMV4_5_STATE_ARM)
1474                                 exit_breakpoint_size = 4;
1475         else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1476                 exit_breakpoint_size = 2;
1477         else
1478         {
1479                 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1480                 exit(-1);
1481         }
1482 */
1483         if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1484         {
1485                 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1486                 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1487                 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1488                 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1489         }
1490
1491         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1492         {
1493                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1494                 retval = ERROR_TARGET_FAILURE;
1495                 goto restore;
1496         }
1497
1498         // no debug, otherwise breakpoint is not set
1499         if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
1500         {
1501                 return retval;
1502         }
1503
1504         if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
1505         {
1506                 return retval;
1507         }
1508
1509         if (target->state != TARGET_HALTED)
1510         {
1511                 if ((retval=target_halt(target))!=ERROR_OK)
1512                         return retval;
1513                 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
1514                 {
1515                         return retval;
1516                 }
1517                 retval = ERROR_TARGET_TIMEOUT;
1518                 goto del_breakpoint;
1519         }
1520
1521         if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1522         {
1523                 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
1524                         buf_get_u32(arm11->reg_list[15].value, 0, 32));
1525                 retval = ERROR_TARGET_TIMEOUT;
1526                 goto del_breakpoint;
1527         }
1528
1529         for (i = 0; i < num_mem_params; i++)
1530         {
1531                 if (mem_params[i].direction != PARAM_OUT)
1532                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1533         }
1534
1535         for (i = 0; i < num_reg_params; i++)
1536         {
1537                 if (reg_params[i].direction != PARAM_OUT)
1538                 {
1539                         reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1540                         if (!reg)
1541                         {
1542                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1543                                 exit(-1);
1544                         }
1545
1546                         if (reg->size != reg_params[i].size)
1547                         {
1548                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1549                                 exit(-1);
1550                         }
1551
1552                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1553                 }
1554         }
1555
1556 del_breakpoint:
1557         breakpoint_remove(target, exit_point);
1558
1559 restore:
1560         // Restore context
1561         for (i = 0; i < 16; i++)
1562         {
1563                 LOG_DEBUG("restoring register %s with value 0x%8.8x",
1564                          arm11->reg_list[i].name, context[i]);
1565                 arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
1566         }
1567         LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
1568         arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
1569
1570 //      arm11->core_state = core_state;
1571 //      arm11->core_mode = core_mode;
1572
1573         return retval;
1574 }
1575
1576 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1577 {
1578         int retval = ERROR_OK;
1579         FNC_INFO;
1580
1581         NEW(arm11_common_t, arm11, 1);
1582
1583         arm11->target = target;
1584
1585         /* prepare JTAG information for the new target */
1586         arm11->jtag_info.tap    = target->tap;
1587         arm11->jtag_info.scann_size     = 5;
1588
1589         if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
1590         {
1591                 return retval;
1592         }
1593
1594         if (target->tap==NULL)
1595                 return ERROR_FAIL;
1596
1597         if (target->tap->ir_length != 5)
1598         {
1599                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1600                 return ERROR_COMMAND_SYNTAX_ERROR;
1601         }
1602
1603         target->arch_info = arm11;
1604
1605         return ERROR_OK;
1606 }
1607
1608 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1609 {
1610         /* Initialize anything we can set up without talking to the target */
1611         return arm11_build_reg_cache(target);
1612 }
1613
1614 /* talk to the target and set things up */
1615 int arm11_examine(struct target_s *target)
1616 {
1617         FNC_INFO;
1618         int retval;
1619
1620         arm11_common_t * arm11 = target->arch_info;
1621
1622         /* check IDCODE */
1623
1624         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1625
1626         scan_field_t            idcode_field;
1627
1628         arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1629
1630         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1631
1632         /* check DIDR */
1633
1634         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1635
1636         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1637
1638         scan_field_t            chain0_fields[2];
1639
1640         arm11_setup_field(arm11, 32, NULL,      &arm11->didr,           chain0_fields + 0);
1641         arm11_setup_field(arm11,  8, NULL,      &arm11->implementor,    chain0_fields + 1);
1642
1643         arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1644
1645         if ((retval=jtag_execute_queue())!=ERROR_OK)
1646                 return retval;
1647
1648
1649         switch (arm11->device_id & 0x0FFFF000)
1650         {
1651         case 0x07B36000:        LOG_INFO("found ARM1136"); break;
1652         case 0x07B56000:        LOG_INFO("found ARM1156"); break;
1653         case 0x07B76000:        LOG_INFO("found ARM1176"); break;
1654         default:
1655         {
1656                 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1657                 return ERROR_FAIL;
1658         }
1659         }
1660
1661         arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1662
1663         if (arm11->debug_version != ARM11_DEBUG_V6 &&
1664                 arm11->debug_version != ARM11_DEBUG_V61)
1665         {
1666                 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1667                 return ERROR_FAIL;
1668         }
1669
1670         arm11->brp      = ((arm11->didr >> 24) & 0x0F) + 1;
1671         arm11->wrp      = ((arm11->didr >> 28) & 0x0F) + 1;
1672
1673         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1674         arm11->free_brps = arm11->brp;
1675         arm11->free_wrps = arm11->wrp;
1676
1677         LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1678                 arm11->device_id,
1679                 arm11->implementor,
1680                 arm11->didr);
1681
1682         /* as a side-effect this reads DSCR and thus
1683          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1684          * as suggested by the spec.
1685          */
1686
1687         arm11_check_init(arm11, NULL);
1688
1689         target->type->examined = 1;
1690
1691         return ERROR_OK;
1692 }
1693
1694 int arm11_quit(void)
1695 {
1696         FNC_INFO_NOTIMPLEMENTED;
1697
1698         return ERROR_OK;
1699 }
1700
1701 /** Load a register that is marked !valid in the register cache */
1702 int arm11_get_reg(reg_t *reg)
1703 {
1704         FNC_INFO;
1705
1706         target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1707
1708         if (target->state != TARGET_HALTED)
1709         {
1710                 LOG_WARNING("target was not halted");
1711                 return ERROR_TARGET_NOT_HALTED;
1712         }
1713
1714         /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1715
1716 #if 0
1717         arm11_common_t *arm11 = target->arch_info;
1718         const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1719 #endif
1720
1721         return ERROR_OK;
1722 }
1723
1724 /** Change a value in the register cache */
1725 int arm11_set_reg(reg_t *reg, u8 *buf)
1726 {
1727         FNC_INFO;
1728
1729         target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1730         arm11_common_t *arm11 = target->arch_info;
1731 //        const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1732
1733         arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1734         reg->valid      = 1;
1735         reg->dirty      = 1;
1736
1737         return ERROR_OK;
1738 }
1739
1740 int arm11_build_reg_cache(target_t *target)
1741 {
1742         arm11_common_t *arm11 = target->arch_info;
1743
1744         NEW(reg_cache_t,                cache,                          1);
1745         NEW(reg_t,                              reg_list,                       ARM11_REGCACHE_COUNT);
1746         NEW(arm11_reg_state_t,  arm11_reg_states,       ARM11_REGCACHE_COUNT);
1747
1748         if (arm11_regs_arch_type == -1)
1749                 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1750
1751         register_init_dummy(&arm11_gdb_dummy_fp_reg);
1752         register_init_dummy(&arm11_gdb_dummy_fps_reg);
1753
1754         arm11->reg_list = reg_list;
1755
1756         /* Build the process context cache */
1757         cache->name             = "arm11 registers";
1758         cache->next             = NULL;
1759         cache->reg_list = reg_list;
1760         cache->num_regs = ARM11_REGCACHE_COUNT;
1761
1762         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1763         (*cache_p) = cache;
1764
1765         arm11->core_cache = cache;
1766 //        armv7m->process_context = cache;
1767
1768         size_t i;
1769
1770         /* Not very elegant assertion */
1771         if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1772                 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1773                 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1774         {
1775                 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1776                 exit(-1);
1777         }
1778
1779         for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1780         {
1781                 reg_t *                                         r       = reg_list                      + i;
1782                 const arm11_reg_defs_t *        rd      = arm11_reg_defs        + i;
1783                 arm11_reg_state_t *                     rs      = arm11_reg_states      + i;
1784
1785                 r->name                         = rd->name;
1786                 r->size                         = 32;
1787                 r->value                        = (u8 *)(arm11->reg_values + i);
1788                 r->dirty                        = 0;
1789                 r->valid                        = 0;
1790                 r->bitfield_desc        = NULL;
1791                 r->num_bitfields        = 0;
1792                 r->arch_type            = arm11_regs_arch_type;
1793                 r->arch_info            = rs;
1794
1795                 rs->def_index           = i;
1796                 rs->target                      = target;
1797         }
1798
1799         return ERROR_OK;
1800 }
1801
1802 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1803 {
1804         if (argc == 0)
1805         {
1806                 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1807                 return ERROR_OK;
1808         }
1809
1810         if (argc != 1)
1811                 return ERROR_COMMAND_SYNTAX_ERROR;
1812
1813         switch (args[0][0])
1814         {
1815         case '0':       /* 0 */
1816         case 'f':       /* false */
1817         case 'F':
1818         case 'd':       /* disable */
1819         case 'D':
1820                 *var = false;
1821                 break;
1822
1823         case '1':       /* 1 */
1824         case 't':       /* true */
1825         case 'T':
1826         case 'e':       /* enable */
1827         case 'E':
1828                 *var = true;
1829                 break;
1830         }
1831
1832         LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1833
1834         return ERROR_OK;
1835 }
1836
1837 #define BOOL_WRAPPER(name, print_name)  \
1838 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1839 { \
1840         return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1841 }
1842
1843 #define RC_TOP(name, descr, more)  \
1844 { \
1845         command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr);  \
1846         command_t * top_cmd = new_cmd; \
1847         more \
1848 }
1849
1850 #define RC_FINAL(name, descr, handler)  \
1851         register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1852
1853 #define RC_FINAL_BOOL(name, descr, var)  \
1854         register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1855
1856 BOOL_WRAPPER(memwrite_burst,                    "memory write burst mode")
1857 BOOL_WRAPPER(memwrite_error_fatal,              "fatal error mode for memory writes")
1858 BOOL_WRAPPER(memrw_no_increment,                "\"no increment\" mode for memory transfers")
1859 BOOL_WRAPPER(step_irq_enable,                   "IRQs while stepping")
1860
1861 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1862 {
1863         if (argc == 1)
1864         {
1865                 arm11_vcr = strtoul(args[0], NULL, 0);
1866         }
1867         else if (argc != 0)
1868         {
1869                 return ERROR_COMMAND_SYNTAX_ERROR;
1870         }
1871
1872         LOG_INFO("VCR 0x%08X", arm11_vcr);
1873         return ERROR_OK;
1874 }
1875
1876 const u32 arm11_coproc_instruction_limits[] =
1877 {
1878         15,                             /* coprocessor */
1879         7,                              /* opcode 1 */
1880         15,                             /* CRn */
1881         15,                             /* CRm */
1882         7,                              /* opcode 2 */
1883         0xFFFFFFFF,             /* value */
1884 };
1885
1886 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1887 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1888
1889 arm11_common_t * arm11_find_target(const char * arg)
1890 {
1891         jtag_tap_t *    tap;
1892         target_t *              t;
1893
1894         tap = jtag_TapByString(arg);
1895
1896         if (!tap)
1897                 return 0;
1898
1899         for (t = all_targets; t; t = t->next)
1900         {
1901                 if (t->tap != tap)
1902                         continue;
1903
1904                 /* if (t->type == arm11_target) */
1905                 if (0 == strcmp(t->type->name, "arm11"))
1906                         return t->arch_info;
1907         }
1908
1909         return 0;
1910 }
1911
1912 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1913 {
1914         if (argc != (read ? 6 : 7))
1915         {
1916                 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1917                 return -1;
1918         }
1919
1920         arm11_common_t * arm11 = arm11_find_target(args[0]);
1921
1922         if (!arm11)
1923         {
1924                 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1925                         read ? arm11_mrc_syntax : arm11_mcr_syntax);
1926
1927                 return -1;
1928         }
1929
1930         if (arm11->target->state != TARGET_HALTED)
1931         {
1932                 LOG_WARNING("target was not halted");
1933                 return ERROR_TARGET_NOT_HALTED;
1934         }
1935
1936         u32     values[6];
1937
1938         {size_t i;
1939         for (i = 0; i < (read ? 5 : 6); i++)
1940         {
1941                 values[i] = strtoul(args[i + 1], NULL, 0);
1942
1943                 if (values[i] > arm11_coproc_instruction_limits[i])
1944                 {
1945                         LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1946                                 (long)(i + 2), arm11_coproc_instruction_limits[i],
1947                                 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1948                         return -1;
1949                 }
1950         }}
1951
1952         u32 instr = 0xEE000010  |
1953                 (values[0] <<  8) |
1954                 (values[1] << 21) |
1955                 (values[2] << 16) |
1956                 (values[3] <<  0) |
1957                 (values[4] <<  5);
1958
1959         if (read)
1960                 instr |= 0x00100000;
1961
1962         arm11_run_instr_data_prepare(arm11);
1963
1964         if (read)
1965         {
1966                 u32 result;
1967                 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1968
1969                 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1970                         values[0], values[1], values[2], values[3], values[4], result, result);
1971         }
1972         else
1973         {
1974                 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1975
1976                 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1977                         values[0], values[1],
1978                         values[5],
1979                         values[2], values[3], values[4]);
1980         }
1981
1982         arm11_run_instr_data_finish(arm11);
1983
1984
1985         return ERROR_OK;
1986 }
1987
1988 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1989 {
1990         return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1991 }
1992
1993 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1994 {
1995         return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1996 }
1997
1998 int arm11_register_commands(struct command_context_s *cmd_ctx)
1999 {
2000         FNC_INFO;
2001
2002         command_t * top_cmd = NULL;
2003
2004         RC_TOP(                         "arm11",                                "arm11 specific commands",
2005
2006         RC_TOP(                         "memwrite",                             "Control memory write transfer mode",
2007
2008                 RC_FINAL_BOOL(  "burst",                                "Enable/Disable non-standard but fast burst mode (default: enabled)",
2009                                                 memwrite_burst)
2010
2011                 RC_FINAL_BOOL(  "error_fatal",                  "Terminate program if transfer error was found (default: enabled)",
2012                                                 memwrite_error_fatal)
2013         )
2014
2015         RC_FINAL_BOOL(          "no_increment",                 "Don't increment address on multi-read/-write (default: disabled)",
2016                                                 memrw_no_increment)
2017
2018         RC_FINAL_BOOL(          "step_irq_enable",              "Enable interrupts while stepping (default: disabled)",
2019                                                 step_irq_enable)
2020
2021         RC_FINAL(                       "vcr",                                  "Control (Interrupt) Vector Catch Register",
2022                                                 arm11_handle_vcr)
2023
2024         RC_FINAL(                       "mrc",                                  "Read Coprocessor register",
2025                                                 arm11_handle_mrc)
2026
2027         RC_FINAL(                       "mcr",                                  "Write Coprocessor register",
2028                                                 arm11_handle_mcr)
2029         )
2030
2031         return ERROR_OK;
2032 }