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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "arm11.h"
  30 #include "armv4_5.h"
  31 #include "arm_simulator.h"
  32 #include "time_support.h"
  33 #include "target_type.h"
  34
  35
  36 #if 0
  37 #define _DEBUG_INSTRUCTION_EXECUTION_
  38 #endif
  39
  40 #if 0
  41 #define FNC_INFO        LOG_DEBUG("-")
  42 #else
  43 #define FNC_INFO
  44 #endif
  45
  46 #if 1
  47 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
  48 #else
  49 #define FNC_INFO_NOTIMPLEMENTED
  50 #endif
  51
  52 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
  53
  54 bool    arm11_config_memwrite_burst                             = true;
  55 bool    arm11_config_memwrite_error_fatal               = true;
  56 uint32_t                arm11_vcr                                                               = 0;
  57 bool    arm11_config_step_irq_enable                    = false;
  58 bool    arm11_config_hardware_step                              = false;
  59
  60 #define ARM11_HANDLER(x)        \
  61         .x                              = arm11_##x
  62
  63
  64 static int arm11_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
  65 static int arm11_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
  66
  67 target_type_t arm11_target =
  68 {
  69         .name                   = "arm11",
  70
  71         ARM11_HANDLER(poll),
  72         ARM11_HANDLER(arch_state),
  73
  74         ARM11_HANDLER(target_request_data),
  75
  76         ARM11_HANDLER(halt),
  77         ARM11_HANDLER(resume),
  78         ARM11_HANDLER(step),
  79
  80         ARM11_HANDLER(assert_reset),
  81         ARM11_HANDLER(deassert_reset),
  82         ARM11_HANDLER(soft_reset_halt),
  83
  84         ARM11_HANDLER(get_gdb_reg_list),
  85
  86         ARM11_HANDLER(read_memory),
  87         ARM11_HANDLER(write_memory),
  88
  89         ARM11_HANDLER(bulk_write_memory),
  90
  91         ARM11_HANDLER(checksum_memory),
  92
  93         ARM11_HANDLER(add_breakpoint),
  94         ARM11_HANDLER(remove_breakpoint),
  95         ARM11_HANDLER(add_watchpoint),
  96         ARM11_HANDLER(remove_watchpoint),
  97
  98         ARM11_HANDLER(run_algorithm),
  99
 100         ARM11_HANDLER(register_commands),
 101         ARM11_HANDLER(target_create),
 102         ARM11_HANDLER(init_target),
 103         ARM11_HANDLER(examine),
 104         .mrc = arm11_mrc,
 105         .mcr = arm11_mcr,
 106
 107 };
 108
 109 int arm11_regs_arch_type = -1;
 110
 111
 112 enum arm11_regtype
 113 {
 114         ARM11_REGISTER_CORE,
 115         ARM11_REGISTER_CPSR,
 116
 117         ARM11_REGISTER_FX,
 118         ARM11_REGISTER_FPS,
 119
 120         ARM11_REGISTER_FIQ,
 121         ARM11_REGISTER_SVC,
 122         ARM11_REGISTER_ABT,
 123         ARM11_REGISTER_IRQ,
 124         ARM11_REGISTER_UND,
 125         ARM11_REGISTER_MON,
 126
 127         ARM11_REGISTER_SPSR_FIQ,
 128         ARM11_REGISTER_SPSR_SVC,
 129         ARM11_REGISTER_SPSR_ABT,
 130         ARM11_REGISTER_SPSR_IRQ,
 131         ARM11_REGISTER_SPSR_UND,
 132         ARM11_REGISTER_SPSR_MON,
 133
 134         /* debug regs */
 135         ARM11_REGISTER_DSCR,
 136         ARM11_REGISTER_WDTR,
 137         ARM11_REGISTER_RDTR,
 138 };
 139
 140
 141 typedef struct arm11_reg_defs_s
 142 {
 143         char *                                  name;
 144         uint32_t                                                num;
 145         int                                             gdb_num;
 146         enum arm11_regtype              type;
 147 } arm11_reg_defs_t;
 148
 149 /* update arm11_regcache_ids when changing this */
 150 static const arm11_reg_defs_t arm11_reg_defs[] =
 151 {
 152         {"r0",  0,      0,      ARM11_REGISTER_CORE},
 153         {"r1",  1,      1,      ARM11_REGISTER_CORE},
 154         {"r2",  2,      2,      ARM11_REGISTER_CORE},
 155         {"r3",  3,      3,      ARM11_REGISTER_CORE},
 156         {"r4",  4,      4,      ARM11_REGISTER_CORE},
 157         {"r5",  5,      5,      ARM11_REGISTER_CORE},
 158         {"r6",  6,      6,      ARM11_REGISTER_CORE},
 159         {"r7",  7,      7,      ARM11_REGISTER_CORE},
 160         {"r8",  8,      8,      ARM11_REGISTER_CORE},
 161         {"r9",  9,      9,      ARM11_REGISTER_CORE},
 162         {"r10", 10,     10,     ARM11_REGISTER_CORE},
 163         {"r11", 11,     11,     ARM11_REGISTER_CORE},
 164         {"r12", 12,     12,     ARM11_REGISTER_CORE},
 165         {"sp",  13,     13,     ARM11_REGISTER_CORE},
 166         {"lr",  14,     14,     ARM11_REGISTER_CORE},
 167         {"pc",  15,     15,     ARM11_REGISTER_CORE},
 168
 169 #if ARM11_REGCACHE_FREGS
 170         {"f0",  0,      16,     ARM11_REGISTER_FX},
 171         {"f1",  1,      17,     ARM11_REGISTER_FX},
 172         {"f2",  2,      18,     ARM11_REGISTER_FX},
 173         {"f3",  3,      19,     ARM11_REGISTER_FX},
 174         {"f4",  4,      20,     ARM11_REGISTER_FX},
 175         {"f5",  5,      21,     ARM11_REGISTER_FX},
 176         {"f6",  6,      22,     ARM11_REGISTER_FX},
 177         {"f7",  7,      23,     ARM11_REGISTER_FX},
 178         {"fps", 0,      24,     ARM11_REGISTER_FPS},
 179 #endif
 180
 181         {"cpsr",        0,      25,     ARM11_REGISTER_CPSR},
 182
 183 #if ARM11_REGCACHE_MODEREGS
 184         {"r8_fiq",      8,      -1,     ARM11_REGISTER_FIQ},
 185         {"r9_fiq",      9,      -1,     ARM11_REGISTER_FIQ},
 186         {"r10_fiq",     10,     -1,     ARM11_REGISTER_FIQ},
 187         {"r11_fiq",     11,     -1,     ARM11_REGISTER_FIQ},
 188         {"r12_fiq",     12,     -1,     ARM11_REGISTER_FIQ},
 189         {"r13_fiq",     13,     -1,     ARM11_REGISTER_FIQ},
 190         {"r14_fiq",     14,     -1,     ARM11_REGISTER_FIQ},
 191         {"spsr_fiq", 0, -1,     ARM11_REGISTER_SPSR_FIQ},
 192
 193         {"r13_svc",     13,     -1,     ARM11_REGISTER_SVC},
 194         {"r14_svc",     14,     -1,     ARM11_REGISTER_SVC},
 195         {"spsr_svc", 0, -1,     ARM11_REGISTER_SPSR_SVC},
 196
 197         {"r13_abt",     13,     -1,     ARM11_REGISTER_ABT},
 198         {"r14_abt",     14,     -1,     ARM11_REGISTER_ABT},
 199         {"spsr_abt", 0, -1,     ARM11_REGISTER_SPSR_ABT},
 200
 201         {"r13_irq",     13,     -1,     ARM11_REGISTER_IRQ},
 202         {"r14_irq",     14,     -1,     ARM11_REGISTER_IRQ},
 203         {"spsr_irq", 0, -1,     ARM11_REGISTER_SPSR_IRQ},
 204
 205         {"r13_und",     13,     -1,     ARM11_REGISTER_UND},
 206         {"r14_und",     14,     -1,     ARM11_REGISTER_UND},
 207         {"spsr_und", 0, -1,     ARM11_REGISTER_SPSR_UND},
 208
 209         /* ARM1176 only */
 210         {"r13_mon",     13,     -1,     ARM11_REGISTER_MON},
 211         {"r14_mon",     14,     -1,     ARM11_REGISTER_MON},
 212         {"spsr_mon", 0, -1,     ARM11_REGISTER_SPSR_MON},
 213 #endif
 214
 215         /* Debug Registers */
 216         {"dscr",        0,      -1,     ARM11_REGISTER_DSCR},
 217         {"wdtr",        0,      -1,     ARM11_REGISTER_WDTR},
 218         {"rdtr",        0,      -1,     ARM11_REGISTER_RDTR},
 219 };
 220
 221 enum arm11_regcache_ids
 222 {
 223         ARM11_RC_R0,
 224         ARM11_RC_RX                     = ARM11_RC_R0,
 225
 226         ARM11_RC_R1,
 227         ARM11_RC_R2,
 228         ARM11_RC_R3,
 229         ARM11_RC_R4,
 230         ARM11_RC_R5,
 231         ARM11_RC_R6,
 232         ARM11_RC_R7,
 233         ARM11_RC_R8,
 234         ARM11_RC_R9,
 235         ARM11_RC_R10,
 236         ARM11_RC_R11,
 237         ARM11_RC_R12,
 238         ARM11_RC_R13,
 239         ARM11_RC_SP                     = ARM11_RC_R13,
 240         ARM11_RC_R14,
 241         ARM11_RC_LR                     = ARM11_RC_R14,
 242         ARM11_RC_R15,
 243         ARM11_RC_PC                     = ARM11_RC_R15,
 244
 245 #if ARM11_REGCACHE_FREGS
 246         ARM11_RC_F0,
 247         ARM11_RC_FX                     = ARM11_RC_F0,
 248         ARM11_RC_F1,
 249         ARM11_RC_F2,
 250         ARM11_RC_F3,
 251         ARM11_RC_F4,
 252         ARM11_RC_F5,
 253         ARM11_RC_F6,
 254         ARM11_RC_F7,
 255         ARM11_RC_FPS,
 256 #endif
 257
 258         ARM11_RC_CPSR,
 259
 260 #if ARM11_REGCACHE_MODEREGS
 261         ARM11_RC_R8_FIQ,
 262         ARM11_RC_R9_FIQ,
 263         ARM11_RC_R10_FIQ,
 264         ARM11_RC_R11_FIQ,
 265         ARM11_RC_R12_FIQ,
 266         ARM11_RC_R13_FIQ,
 267         ARM11_RC_R14_FIQ,
 268         ARM11_RC_SPSR_FIQ,
 269
 270         ARM11_RC_R13_SVC,
 271         ARM11_RC_R14_SVC,
 272         ARM11_RC_SPSR_SVC,
 273
 274         ARM11_RC_R13_ABT,
 275         ARM11_RC_R14_ABT,
 276         ARM11_RC_SPSR_ABT,
 277
 278         ARM11_RC_R13_IRQ,
 279         ARM11_RC_R14_IRQ,
 280         ARM11_RC_SPSR_IRQ,
 281
 282         ARM11_RC_R13_UND,
 283         ARM11_RC_R14_UND,
 284         ARM11_RC_SPSR_UND,
 285
 286         ARM11_RC_R13_MON,
 287         ARM11_RC_R14_MON,
 288         ARM11_RC_SPSR_MON,
 289 #endif
 290
 291         ARM11_RC_DSCR,
 292         ARM11_RC_WDTR,
 293         ARM11_RC_RDTR,
 294
 295         ARM11_RC_MAX,
 296 };
 297
 298 #define ARM11_GDB_REGISTER_COUNT        26
 299
 300 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 301
 302 reg_t arm11_gdb_dummy_fp_reg =
 303 {
 304         "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 305 };
 306
 307 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 308
 309 reg_t arm11_gdb_dummy_fps_reg =
 310 {
 311         "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 312 };
 313
 314
 315
 316 /** Check and if necessary take control of the system
 317  *
 318  * \param arm11         Target state variable.
 319  * \param dscr          If the current DSCR content is
 320  *                                      available a pointer to a word holding the
 321  *                                      DSCR can be passed. Otherwise use NULL.
 322  */
 323 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
 324 {
 325         FNC_INFO;
 326
 327         uint32_t                        dscr_local_tmp_copy;
 328
 329         if (!dscr)
 330         {
 331                 dscr = &dscr_local_tmp_copy;
 332
 333                 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
 334         }
 335
 336         if (!(*dscr & ARM11_DSCR_MODE_SELECT))
 337         {
 338                 LOG_DEBUG("Bringing target into debug mode");
 339
 340                 *dscr |= ARM11_DSCR_MODE_SELECT;                /* Halt debug-mode */
 341                 arm11_write_DSCR(arm11, *dscr);
 342
 343                 /* add further reset initialization here */
 344
 345                 arm11->simulate_reset_on_next_halt = true;
 346
 347                 if (*dscr & ARM11_DSCR_CORE_HALTED)
 348                 {
 349                         /** \todo TODO: this needs further scrutiny because
 350                           * arm11_on_enter_debug_state() never gets properly called.
 351                           * As a result we don't read the actual register states from
 352                           * the target.
 353                           */
 354
 355                         arm11->target->state    = TARGET_HALTED;
 356                         arm11->target->debug_reason     = arm11_get_DSCR_debug_reason(*dscr);
 357                 }
 358                 else
 359                 {
 360                         arm11->target->state    = TARGET_RUNNING;
 361                         arm11->target->debug_reason     = DBG_REASON_NOTHALTED;
 362                 }
 363
 364                 arm11_sc7_clear_vbw(arm11);
 365         }
 366
 367         return ERROR_OK;
 368 }
 369
 370
 371
 372 #define R(x) \
 373         (arm11->reg_values[ARM11_RC_##x])
 374
 375 /** Save processor state.
 376   *
 377   * This is called when the HALT instruction has succeeded
 378   * or on other occasions that stop the processor.
 379   *
 380   */
 381 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 382 {
 383         int retval;
 384         FNC_INFO;
 385
 386         for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
 387         {
 388                 arm11->reg_list[i].valid        = 1;
 389                 arm11->reg_list[i].dirty        = 0;
 390         }
 391
 392         /* Save DSCR */
 393         CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
 394
 395         /* Save wDTR */
 396
 397         if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
 398         {
 399                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 400
 401                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 402
 403                 scan_field_t    chain5_fields[3];
 404
 405                 arm11_setup_field(arm11, 32, NULL, &R(WDTR),    chain5_fields + 0);
 406                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
 407                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
 408
 409                 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 410         }
 411         else
 412         {
 413                 arm11->reg_list[ARM11_RC_WDTR].valid    = 0;
 414         }
 415
 416
 417         /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
 418         /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
 419            ARM1136 seems to require this to issue ITR's as well */
 420
 421         uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
 422
 423         /* this executes JTAG queue: */
 424
 425         arm11_write_DSCR(arm11, new_dscr);
 426
 427
 428         /* From the spec:
 429            Before executing any instruction in debug state you have to drain the write buffer.
 430            This ensures that no imprecise Data Aborts can return at a later point:*/
 431
 432         /** \todo TODO: Test drain write buffer. */
 433
 434 #if 0
 435         while (1)
 436         {
 437                 /* MRC p14,0,R0,c5,c10,0 */
 438                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 439
 440                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 441                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 442
 443                 uint32_t dscr = arm11_read_DSCR(arm11);
 444
 445                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 446
 447                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 448                 {
 449                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 450
 451                         dscr = arm11_read_DSCR(arm11);
 452
 453                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 454
 455                         break;
 456                 }
 457         }
 458 #endif
 459
 460         retval = arm11_run_instr_data_prepare(arm11);
 461         if (retval != ERROR_OK)
 462                 return retval;
 463
 464         /* save r0 - r14 */
 465
 466         /** \todo TODO: handle other mode registers */
 467
 468         for (size_t i = 0; i < 15; i++)
 469         {
 470                 /* MCR p14,0,R?,c0,c5,0 */
 471                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
 472                 if (retval != ERROR_OK)
 473                         return retval;
 474         }
 475
 476         /* save rDTR */
 477
 478         /* check rDTRfull in DSCR */
 479
 480         if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
 481         {
 482                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 483                 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
 484                 if (retval != ERROR_OK)
 485                         return retval;
 486         }
 487         else
 488         {
 489                 arm11->reg_list[ARM11_RC_RDTR].valid    = 0;
 490         }
 491
 492         /* save CPSR */
 493
 494         /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
 495         retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
 496         if (retval != ERROR_OK)
 497                 return retval;
 498
 499         /* save PC */
 500
 501         /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
 502         retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
 503         if (retval != ERROR_OK)
 504                 return retval;
 505
 506         /* adjust PC depending on ARM state */
 507
 508         if (R(CPSR) & ARM11_CPSR_J)     /* Java state */
 509         {
 510                 arm11->reg_values[ARM11_RC_PC] -= 0;
 511         }
 512         else if (R(CPSR) & ARM11_CPSR_T)        /* Thumb state */
 513         {
 514                 arm11->reg_values[ARM11_RC_PC] -= 4;
 515         }
 516         else                                    /* ARM state */
 517         {
 518                 arm11->reg_values[ARM11_RC_PC] -= 8;
 519         }
 520
 521         if (arm11->simulate_reset_on_next_halt)
 522         {
 523                 arm11->simulate_reset_on_next_halt = false;
 524
 525                 LOG_DEBUG("Reset c1 Control Register");
 526
 527                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 528
 529                 /* MCR p15,0,R0,c1,c0,0 */
 530                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 531                 if (retval != ERROR_OK)
 532                         return retval;
 533
 534         }
 535
 536         retval = arm11_run_instr_data_finish(arm11);
 537         if (retval != ERROR_OK)
 538                 return retval;
 539
 540         arm11_dump_reg_changes(arm11);
 541
 542         return ERROR_OK;
 543 }
 544
 545 void arm11_dump_reg_changes(arm11_common_t * arm11)
 546 {
 547
 548         if (!(debug_level >= LOG_LVL_DEBUG))
 549         {
 550                 return;
 551         }
 552
 553         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 554         {
 555                 if (!arm11->reg_list[i].valid)
 556                 {
 557                         if (arm11->reg_history[i].valid)
 558                                 LOG_DEBUG("%8s INVALID   (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
 559                 }
 560                 else
 561                 {
 562                         if (arm11->reg_history[i].valid)
 563                         {
 564                                 if (arm11->reg_history[i].value != arm11->reg_values[i])
 565                                         LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
 566                         }
 567                         else
 568                         {
 569                                 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
 570                         }
 571                 }
 572         }
 573 }
 574
 575 /** Restore processor state
 576   *
 577   * This is called in preparation for the RESTART function.
 578   *
 579   */
 580 int arm11_leave_debug_state(arm11_common_t * arm11)
 581 {
 582         FNC_INFO;
 583         int retval;
 584
 585         retval = arm11_run_instr_data_prepare(arm11);
 586         if (retval != ERROR_OK)
 587                 return retval;
 588
 589         /** \todo TODO: handle other mode registers */
 590
 591         /* restore R1 - R14 */
 592
 593         for (size_t i = 1; i < 15; i++)
 594         {
 595                 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
 596                         continue;
 597
 598                 /* MRC p14,0,r?,c0,c5,0 */
 599                 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
 600
 601                 //      LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
 602         }
 603
 604         retval = arm11_run_instr_data_finish(arm11);
 605         if (retval != ERROR_OK)
 606                 return retval;
 607
 608         /* spec says clear wDTR and rDTR; we assume they are clear as
 609            otherwise our programming would be sloppy */
 610         {
 611                 uint32_t DSCR;
 612
 613                 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
 614
 615                 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 616                 {
 617                         /*
 618                         The wDTR/rDTR two registers that are used to send/receive data to/from
 619                         the core in tandem with corresponding instruction codes that are
 620                         written into the core. The RDTR FULL/WDTR FULL flag indicates that the
 621                         registers hold data that was written by one side (CPU or JTAG) and not
 622                         read out by the other side.
 623                         */
 624                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 625                         return ERROR_FAIL;
 626                 }
 627         }
 628
 629         retval = arm11_run_instr_data_prepare(arm11);
 630         if (retval != ERROR_OK)
 631                 return retval;
 632
 633         /* restore original wDTR */
 634
 635         if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
 636         {
 637                 /* MCR p14,0,R0,c0,c5,0 */
 638                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
 639                 if (retval != ERROR_OK)
 640                         return retval;
 641         }
 642
 643         /* restore CPSR */
 644
 645         /* MSR CPSR,R0*/
 646         retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
 647         if (retval != ERROR_OK)
 648                 return retval;
 649
 650
 651         /* restore PC */
 652
 653         /* MOV PC,R0 */
 654         retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
 655         if (retval != ERROR_OK)
 656                 return retval;
 657
 658
 659         /* restore R0 */
 660
 661         /* MRC p14,0,r0,c0,c5,0 */
 662         arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
 663
 664         retval = arm11_run_instr_data_finish(arm11);
 665         if (retval != ERROR_OK)
 666                 return retval;
 667
 668         /* restore DSCR */
 669
 670         arm11_write_DSCR(arm11, R(DSCR));
 671
 672         /* restore rDTR */
 673
 674         if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
 675         {
 676                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 677
 678                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 679
 680                 scan_field_t    chain5_fields[3];
 681
 682                 uint8_t                 Ready           = 0;    /* ignored */
 683                 uint8_t                 Valid           = 0;    /* ignored */
 684
 685                 arm11_setup_field(arm11, 32, &R(RDTR),  NULL, chain5_fields + 0);
 686                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 687                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 688
 689                 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 690         }
 691
 692         arm11_record_register_history(arm11);
 693
 694         return ERROR_OK;
 695 }
 696
 697 void arm11_record_register_history(arm11_common_t * arm11)
 698 {
 699         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 700         {
 701                 arm11->reg_history[i].value     = arm11->reg_values[i];
 702                 arm11->reg_history[i].valid     = arm11->reg_list[i].valid;
 703
 704                 arm11->reg_list[i].valid        = 0;
 705                 arm11->reg_list[i].dirty        = 0;
 706         }
 707 }
 708
 709
 710 /* poll current target status */
 711 int arm11_poll(struct target_s *target)
 712 {
 713         FNC_INFO;
 714         int retval;
 715
 716         arm11_common_t * arm11 = target->arch_info;
 717
 718         uint32_t        dscr;
 719
 720         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 721
 722         LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 723
 724         CHECK_RETVAL(arm11_check_init(arm11, &dscr));
 725
 726         if (dscr & ARM11_DSCR_CORE_HALTED)
 727         {
 728                 if (target->state != TARGET_HALTED)
 729                 {
 730                         enum target_state old_state = target->state;
 731
 732                         LOG_DEBUG("enter TARGET_HALTED");
 733                         target->state                   = TARGET_HALTED;
 734                         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 735                         retval = arm11_on_enter_debug_state(arm11);
 736                         if (retval != ERROR_OK)
 737                                 return retval;
 738
 739                         target_call_event_callbacks(target,
 740                                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
 741                 }
 742         }
 743         else
 744         {
 745                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 746                 {
 747                         LOG_DEBUG("enter TARGET_RUNNING");
 748                         target->state                   = TARGET_RUNNING;
 749                         target->debug_reason    = DBG_REASON_NOTHALTED;
 750                 }
 751         }
 752
 753         return ERROR_OK;
 754 }
 755 /* architecture specific status reply */
 756 int arm11_arch_state(struct target_s *target)
 757 {
 758         arm11_common_t * arm11 = target->arch_info;
 759
 760         LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 761                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 762                          R(CPSR),
 763                          R(PC));
 764
 765         return ERROR_OK;
 766 }
 767
 768 /* target request support */
 769 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
 770 {
 771         FNC_INFO_NOTIMPLEMENTED;
 772
 773         return ERROR_OK;
 774 }
 775
 776 /* target execution control */
 777 int arm11_halt(struct target_s *target)
 778 {
 779         FNC_INFO;
 780
 781         arm11_common_t * arm11 = target->arch_info;
 782
 783         LOG_DEBUG("target->state: %s",
 784                 target_state_name(target));
 785
 786         if (target->state == TARGET_UNKNOWN)
 787         {
 788                 arm11->simulate_reset_on_next_halt = true;
 789         }
 790
 791         if (target->state == TARGET_HALTED)
 792         {
 793                 LOG_DEBUG("target was already halted");
 794                 return ERROR_OK;
 795         }
 796
 797         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 798
 799         CHECK_RETVAL(jtag_execute_queue());
 800
 801         uint32_t dscr;
 802
 803         int i = 0;
 804         while (1)
 805         {
 806                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 807
 808                 if (dscr & ARM11_DSCR_CORE_HALTED)
 809                         break;
 810
 811
 812                 long long then = 0;
 813                 if (i == 1000)
 814                 {
 815                         then = timeval_ms();
 816                 }
 817                 if (i >= 1000)
 818                 {
 819                         if ((timeval_ms()-then) > 1000)
 820                         {
 821                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 822                                 return ERROR_FAIL;
 823                         }
 824                 }
 825                 i++;
 826         }
 827
 828         arm11_on_enter_debug_state(arm11);
 829
 830         enum target_state old_state     = target->state;
 831
 832         target->state           = TARGET_HALTED;
 833         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 834
 835         CHECK_RETVAL(
 836                 target_call_event_callbacks(target,
 837                         old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 838
 839         return ERROR_OK;
 840 }
 841
 842 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
 843 {
 844         FNC_INFO;
 845
 846         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 847         //      current, address, handle_breakpoints, debug_execution);
 848
 849         arm11_common_t * arm11 = target->arch_info;
 850
 851         LOG_DEBUG("target->state: %s",
 852                 target_state_name(target));
 853
 854
 855         if (target->state != TARGET_HALTED)
 856         {
 857                 LOG_ERROR("Target not halted");
 858                 return ERROR_TARGET_NOT_HALTED;
 859         }
 860
 861         if (!current)
 862                 R(PC) = address;
 863
 864         LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 865
 866         /* clear breakpoints/watchpoints and VCR*/
 867         arm11_sc7_clear_vbw(arm11);
 868
 869         /* Set up breakpoints */
 870         if (!debug_execution)
 871         {
 872                 /* check if one matches PC and step over it if necessary */
 873
 874                 breakpoint_t *  bp;
 875
 876                 for (bp = target->breakpoints; bp; bp = bp->next)
 877                 {
 878                         if (bp->address == R(PC))
 879                         {
 880                                 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 881                                 arm11_step(target, 1, 0, 0);
 882                                 break;
 883                         }
 884                 }
 885
 886                 /* set all breakpoints */
 887
 888                 size_t          brp_num = 0;
 889
 890                 for (bp = target->breakpoints; bp; bp = bp->next)
 891                 {
 892                         arm11_sc7_action_t      brp[2];
 893
 894                         brp[0].write    = 1;
 895                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 896                         brp[0].value    = bp->address;
 897                         brp[1].write    = 1;
 898                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 899                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 900
 901                         arm11_sc7_run(arm11, brp, asizeof(brp));
 902
 903                         LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
 904
 905                         brp_num++;
 906                 }
 907
 908                 arm11_sc7_set_vcr(arm11, arm11_vcr);
 909         }
 910
 911         arm11_leave_debug_state(arm11);
 912
 913         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 914
 915         CHECK_RETVAL(jtag_execute_queue());
 916
 917         int i = 0;
 918         while (1)
 919         {
 920                 uint32_t dscr;
 921
 922                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 923
 924                 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 925
 926                 if (dscr & ARM11_DSCR_CORE_RESTARTED)
 927                         break;
 928
 929
 930                 long long then = 0;
 931                 if (i == 1000)
 932                 {
 933                         then = timeval_ms();
 934                 }
 935                 if (i >= 1000)
 936                 {
 937                         if ((timeval_ms()-then) > 1000)
 938                         {
 939                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 940                                 return ERROR_FAIL;
 941                         }
 942                 }
 943                 i++;
 944         }
 945
 946         if (!debug_execution)
 947         {
 948                 target->state                   = TARGET_RUNNING;
 949                 target->debug_reason    = DBG_REASON_NOTHALTED;
 950
 951                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 952         }
 953         else
 954         {
 955                 target->state                   = TARGET_DEBUG_RUNNING;
 956                 target->debug_reason    = DBG_REASON_NOTHALTED;
 957
 958                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 959         }
 960
 961         return ERROR_OK;
 962 }
 963
 964
 965 static int armv4_5_to_arm11(int reg)
 966 {
 967         if (reg < 16)
 968                 return reg;
 969         switch (reg)
 970         {
 971         case ARMV4_5_CPSR:
 972                 return ARM11_RC_CPSR;
 973         case 16:
 974                 /* FIX!!! handle thumb better! */
 975                 return ARM11_RC_CPSR;
 976         default:
 977                 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
 978                 exit(-1);
 979         }
 980 }
 981
 982
 983 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
 984 {
 985         arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 986
 987         reg=armv4_5_to_arm11(reg);
 988
 989         return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
 990 }
 991
 992 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
 993 {
 994         arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 995
 996         reg=armv4_5_to_arm11(reg);
 997
 998         buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
 999 }
1000
1001 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
1002 {
1003         arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1004
1005         return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
1006 }
1007
1008 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
1009 {
1010 //      arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1011
1012         /* FIX!!!! we should implement thumb for arm11 */
1013         return ARMV4_5_STATE_ARM;
1014 }
1015
1016 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
1017 {
1018 //      arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1019
1020         /* FIX!!!! we should implement thumb for arm11 */
1021         LOG_ERROR("Not implemetned!");
1022 }
1023
1024
1025 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
1026 {
1027         //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1028
1029         /* FIX!!!! we should implement something that returns the current mode here!!! */
1030         return ARMV4_5_MODE_USR;
1031 }
1032
1033 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
1034 {
1035         struct arm_sim_interface sim;
1036
1037         sim.user_data=target->arch_info;
1038         sim.get_reg=&arm11_sim_get_reg;
1039         sim.set_reg=&arm11_sim_set_reg;
1040         sim.get_reg_mode=&arm11_sim_get_reg;
1041         sim.set_reg_mode=&arm11_sim_set_reg;
1042         sim.get_cpsr=&arm11_sim_get_cpsr;
1043         sim.get_mode=&arm11_sim_get_mode;
1044         sim.get_state=&arm11_sim_get_state;
1045         sim.set_state=&arm11_sim_set_state;
1046
1047         return arm_simulate_step_core(target, dry_run_pc, &sim);
1048
1049 }
1050
1051 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
1052 {
1053         FNC_INFO;
1054
1055         LOG_DEBUG("target->state: %s",
1056                 target_state_name(target));
1057
1058         if (target->state != TARGET_HALTED)
1059         {
1060                 LOG_WARNING("target was not halted");
1061                 return ERROR_TARGET_NOT_HALTED;
1062         }
1063
1064         arm11_common_t * arm11 = target->arch_info;
1065
1066         if (!current)
1067                 R(PC) = address;
1068
1069         LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1070
1071
1072         /** \todo TODO: Thumb not supported here */
1073
1074         uint32_t        next_instruction;
1075
1076         CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1077
1078         /* skip over BKPT */
1079         if ((next_instruction & 0xFFF00070) == 0xe1200070)
1080         {
1081                 R(PC) += 4;
1082                 arm11->reg_list[ARM11_RC_PC].valid = 1;
1083                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1084                 LOG_DEBUG("Skipping BKPT");
1085         }
1086         /* skip over Wait for interrupt / Standby */
1087         /* mcr  15, 0, r?, cr7, cr0, {4} */
1088         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1089         {
1090                 R(PC) += 4;
1091                 arm11->reg_list[ARM11_RC_PC].valid = 1;
1092                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1093                 LOG_DEBUG("Skipping WFI");
1094         }
1095         /* ignore B to self */
1096         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1097         {
1098                 LOG_DEBUG("Not stepping jump to self");
1099         }
1100         else
1101         {
1102                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1103                 * with this. */
1104
1105                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1106                 * the VCR might be something worth looking into. */
1107
1108
1109                 /* Set up breakpoint for stepping */
1110
1111                 arm11_sc7_action_t      brp[2];
1112
1113                 brp[0].write    = 1;
1114                 brp[0].address  = ARM11_SC7_BVR0;
1115                 brp[1].write    = 1;
1116                 brp[1].address  = ARM11_SC7_BCR0;
1117
1118                 if (arm11_config_hardware_step)
1119                 {
1120                         /* hardware single stepping be used if possible or is it better to
1121                          * always use the same code path? Hardware single stepping is not supported
1122                          * on all hardware
1123                          */
1124                          brp[0].value   = R(PC);
1125                          brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1126                 } else
1127                 {
1128                         /* sets a breakpoint on the next PC(calculated by simulation),
1129                          */
1130                         uint32_t next_pc;
1131                         int retval;
1132                         retval = arm11_simulate_step(target, &next_pc);
1133                         if (retval != ERROR_OK)
1134                                 return retval;
1135
1136                         brp[0].value    = next_pc;
1137                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1138                 }
1139
1140                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1141
1142                 /* resume */
1143
1144
1145                 if (arm11_config_step_irq_enable)
1146                         R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;              /* should be redundant */
1147                 else
1148                         R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1149
1150
1151                 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1152
1153                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1154
1155                 CHECK_RETVAL(jtag_execute_queue());
1156
1157                 /* wait for halt */
1158                 int i = 0;
1159                 while (1)
1160                 {
1161                         uint32_t dscr;
1162
1163                         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1164
1165                         LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1166
1167                         if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1168                                 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1169                                 break;
1170
1171                         long long then = 0;
1172                         if (i == 1000)
1173                         {
1174                                 then = timeval_ms();
1175                         }
1176                         if (i >= 1000)
1177                         {
1178                                 if ((timeval_ms()-then) > 1000)
1179                                 {
1180                                         LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1181                                         return ERROR_FAIL;
1182                                 }
1183                         }
1184                         i++;
1185                 }
1186
1187                 /* clear breakpoint */
1188                 arm11_sc7_clear_vbw(arm11);
1189
1190                 /* save state */
1191                 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1192
1193             /* restore default state */
1194                 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1195
1196         }
1197
1198         //        target->state         = TARGET_HALTED;
1199         target->debug_reason    = DBG_REASON_SINGLESTEP;
1200
1201         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1202
1203         return ERROR_OK;
1204 }
1205
1206 int arm11_assert_reset(target_t *target)
1207 {
1208         FNC_INFO;
1209         int retval;
1210
1211         arm11_common_t * arm11 = target->arch_info;
1212         retval = arm11_check_init(arm11, NULL);
1213         if (retval != ERROR_OK)
1214                 return retval;
1215
1216         target->state = TARGET_UNKNOWN;
1217
1218         /* we would very much like to reset into the halted, state,
1219          * but resetting and halting is second best... */
1220         if (target->reset_halt)
1221         {
1222                 CHECK_RETVAL(target_halt(target));
1223         }
1224
1225
1226         /* srst is funny. We can not do *anything* else while it's asserted
1227          * and it has unkonwn side effects. Make sure no other code runs
1228          * meanwhile.
1229          *
1230          * Code below assumes srst:
1231          *
1232          * - Causes power-on-reset (but of what parts of the system?). Bug
1233          * in arm11?
1234          *
1235          * - Messes us TAP state without asserting trst.
1236          *
1237          * - There is another bug in the arm11 core. When you generate an access to
1238          * external logic (for example ddr controller via AHB bus) and that block
1239          * is not configured (perhaps it is still held in reset), that transaction
1240          * will never complete. This will hang arm11 core but it will also hang
1241          * JTAG controller. Nothing, short of srst assertion will bring it out of
1242          * this.
1243          *
1244          * Mysteries:
1245          *
1246          * - What should the PC be after an srst reset when starting in the halted
1247          * state?
1248          */
1249
1250         jtag_add_reset(0, 1);
1251         jtag_add_reset(0, 0);
1252
1253         /* How long do we have to wait? */
1254         jtag_add_sleep(5000);
1255
1256         /* un-mess up TAP state */
1257         jtag_add_tlr();
1258
1259         retval = jtag_execute_queue();
1260         if (retval != ERROR_OK)
1261         {
1262                 return retval;
1263         }
1264
1265         return ERROR_OK;
1266 }
1267
1268 int arm11_deassert_reset(target_t *target)
1269 {
1270         return ERROR_OK;
1271 }
1272
1273 int arm11_soft_reset_halt(struct target_s *target)
1274 {
1275         FNC_INFO_NOTIMPLEMENTED;
1276
1277         return ERROR_OK;
1278 }
1279
1280 /* target register access for gdb */
1281 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1282 {
1283         FNC_INFO;
1284
1285         arm11_common_t * arm11 = target->arch_info;
1286
1287         *reg_list_size  = ARM11_GDB_REGISTER_COUNT;
1288         *reg_list               = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1289
1290         for (size_t i = 16; i < 24; i++)
1291         {
1292                 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1293         }
1294
1295         (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1296
1297         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1298         {
1299                 if (arm11_reg_defs[i].gdb_num == -1)
1300                         continue;
1301
1302                 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1303         }
1304
1305         return ERROR_OK;
1306 }
1307
1308 /* target memory access
1309  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1310  * count: number of items of <size>
1311  *
1312  * arm11_config_memrw_no_increment - in the future we may want to be able
1313  * to read/write a range of data to a "port". a "port" is an action on
1314  * read memory address for some peripheral.
1315  */
1316 int arm11_read_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1317                 bool arm11_config_memrw_no_increment)
1318 {
1319         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1320         int retval;
1321
1322         FNC_INFO;
1323
1324         if (target->state != TARGET_HALTED)
1325         {
1326                 LOG_WARNING("target was not halted");
1327                 return ERROR_TARGET_NOT_HALTED;
1328         }
1329
1330         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1331
1332         arm11_common_t * arm11 = target->arch_info;
1333
1334         retval = arm11_run_instr_data_prepare(arm11);
1335         if (retval != ERROR_OK)
1336                 return retval;
1337
1338         /* MRC p14,0,r0,c0,c5,0 */
1339         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1340         if (retval != ERROR_OK)
1341                 return retval;
1342
1343         switch (size)
1344         {
1345         case 1:
1346                 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1347                 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1348
1349                 for (size_t i = 0; i < count; i++)
1350                 {
1351                         /* ldrb    r1, [r0], #1 */
1352                         /* ldrb    r1, [r0] */
1353                         arm11_run_instr_no_data1(arm11,
1354                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1355
1356                         uint32_t res;
1357                         /* MCR p14,0,R1,c0,c5,0 */
1358                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1359
1360                         *buffer++ = res;
1361                 }
1362
1363                 break;
1364
1365         case 2:
1366                 {
1367                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1368
1369                         for (size_t i = 0; i < count; i++)
1370                         {
1371                                 /* ldrh    r1, [r0], #2 */
1372                                 arm11_run_instr_no_data1(arm11,
1373                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1374
1375                                 uint32_t res;
1376
1377                                 /* MCR p14,0,R1,c0,c5,0 */
1378                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1379
1380                                 uint16_t svalue = res;
1381                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1382                         }
1383
1384                         break;
1385                 }
1386
1387         case 4:
1388                 {
1389                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1390                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1391                 uint32_t *words = (uint32_t *)buffer;
1392
1393                 /* LDC p14,c5,[R0],#4 */
1394                 /* LDC p14,c5,[R0] */
1395                 arm11_run_instr_data_from_core(arm11, instr, words, count);
1396                 break;
1397                 }
1398         }
1399
1400         return arm11_run_instr_data_finish(arm11);
1401 }
1402
1403 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1404 {
1405         return arm11_read_memory_inner(target, address, size, count, buffer, false);
1406 }
1407
1408 /*
1409 * arm11_config_memrw_no_increment - in the future we may want to be able
1410 * to read/write a range of data to a "port". a "port" is an action on
1411 * read memory address for some peripheral.
1412 */
1413 int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1414                 bool arm11_config_memrw_no_increment)
1415 {
1416         int retval;
1417         FNC_INFO;
1418
1419         if (target->state != TARGET_HALTED)
1420         {
1421                 LOG_WARNING("target was not halted");
1422                 return ERROR_TARGET_NOT_HALTED;
1423         }
1424
1425         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1426
1427         arm11_common_t * arm11 = target->arch_info;
1428
1429         retval = arm11_run_instr_data_prepare(arm11);
1430         if (retval != ERROR_OK)
1431                 return retval;
1432
1433         /* MRC p14,0,r0,c0,c5,0 */
1434         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1435         if (retval != ERROR_OK)
1436                 return retval;
1437
1438         /* burst writes are not used for single words as those may well be
1439          * reset init script writes.
1440          *
1441          * The other advantage is that as burst writes are default, we'll
1442          * now exercise both burst and non-burst code paths with the
1443          * default settings, increasing code coverage.
1444          */
1445         bool burst = arm11_config_memwrite_burst && (count > 1);
1446
1447         switch (size)
1448         {
1449         case 1:
1450                 {
1451                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1452
1453                         for (size_t i = 0; i < count; i++)
1454                         {
1455                                 /* MRC p14,0,r1,c0,c5,0 */
1456                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1457                                 if (retval != ERROR_OK)
1458                                         return retval;
1459
1460                                 /* strb    r1, [r0], #1 */
1461                                 /* strb    r1, [r0] */
1462                                 retval = arm11_run_instr_no_data1(arm11,
1463                                         !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1464                                 if (retval != ERROR_OK)
1465                                         return retval;
1466                         }
1467
1468                         break;
1469                 }
1470
1471         case 2:
1472                 {
1473                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1474
1475                         for (size_t i = 0; i < count; i++)
1476                         {
1477                                 uint16_t value;
1478                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1479
1480                                 /* MRC p14,0,r1,c0,c5,0 */
1481                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1482                                 if (retval != ERROR_OK)
1483                                         return retval;
1484
1485                                 /* strh    r1, [r0], #2 */
1486                                 /* strh    r1, [r0] */
1487                                 retval = arm11_run_instr_no_data1(arm11,
1488                                         !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1489                                 if (retval != ERROR_OK)
1490                                         return retval;
1491                         }
1492
1493                         break;
1494                 }
1495
1496         case 4: {
1497                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1498
1499                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1500                 uint32_t *words = (uint32_t*)buffer;
1501
1502                 if (!burst)
1503                 {
1504                         /* STC p14,c5,[R0],#4 */
1505                         /* STC p14,c5,[R0]*/
1506                         retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1507                         if (retval != ERROR_OK)
1508                                 return retval;
1509                 }
1510                 else
1511                 {
1512                         /* STC p14,c5,[R0],#4 */
1513                         /* STC p14,c5,[R0]*/
1514                         retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1515                         if (retval != ERROR_OK)
1516                                 return retval;
1517                 }
1518
1519                 break;
1520         }
1521         }
1522
1523         /* r0 verification */
1524         if (!arm11_config_memrw_no_increment)
1525         {
1526                 uint32_t r0;
1527
1528                 /* MCR p14,0,R0,c0,c5,0 */
1529                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1530                 if (retval != ERROR_OK)
1531                         return retval;
1532
1533                 if (address + size * count != r0)
1534                 {
1535                         LOG_ERROR("Data transfer failed. Expected end "
1536                                         "address 0x%08x, got 0x%08x",
1537                                         (unsigned) (address + size * count),
1538                                         (unsigned) r0);
1539
1540                         if (burst)
1541                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1542
1543                         if (arm11_config_memwrite_error_fatal)
1544                                 return ERROR_FAIL;
1545                 }
1546         }
1547
1548         return arm11_run_instr_data_finish(arm11);
1549 }
1550
1551 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1552 {
1553         return arm11_write_memory_inner(target, address, size, count, buffer, false);
1554 }
1555
1556 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1557 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1558 {
1559         FNC_INFO;
1560
1561         if (target->state != TARGET_HALTED)
1562         {
1563                 LOG_WARNING("target was not halted");
1564                 return ERROR_TARGET_NOT_HALTED;
1565         }
1566
1567         return arm11_write_memory(target, address, 4, count, buffer);
1568 }
1569
1570 /* here we have nothing target specific to contribute, so we fail and then the
1571  * fallback code will read data from the target and calculate the CRC on the
1572  * host.
1573  */
1574 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1575 {
1576         return ERROR_FAIL;
1577 }
1578
1579 /* target break-/watchpoint control
1580 * rw: 0 = write, 1 = read, 2 = access
1581 */
1582 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1583 {
1584         FNC_INFO;
1585
1586         arm11_common_t * arm11 = target->arch_info;
1587
1588 #if 0
1589         if (breakpoint->type == BKPT_SOFT)
1590         {
1591                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1592                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1593         }
1594 #endif
1595
1596         if (!arm11->free_brps)
1597         {
1598                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1599                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1600         }
1601
1602         if (breakpoint->length != 4)
1603         {
1604                 LOG_DEBUG("only breakpoints of four bytes length supported");
1605                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1606         }
1607
1608         arm11->free_brps--;
1609
1610         return ERROR_OK;
1611 }
1612
1613 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1614 {
1615         FNC_INFO;
1616
1617         arm11_common_t * arm11 = target->arch_info;
1618
1619         arm11->free_brps++;
1620
1621         return ERROR_OK;
1622 }
1623
1624 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1625 {
1626         FNC_INFO_NOTIMPLEMENTED;
1627
1628         return ERROR_OK;
1629 }
1630
1631 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1632 {
1633         FNC_INFO_NOTIMPLEMENTED;
1634
1635         return ERROR_OK;
1636 }
1637
1638 // HACKHACKHACK - FIXME mode/state
1639 /* target algorithm support */
1640 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1641                         int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1642                         int timeout_ms, void *arch_info)
1643 {
1644                 arm11_common_t *arm11 = target->arch_info;
1645 //      enum armv4_5_state core_state = arm11->core_state;
1646 //      enum armv4_5_mode core_mode = arm11->core_mode;
1647         uint32_t context[16];
1648         uint32_t cpsr;
1649         int exit_breakpoint_size = 0;
1650         int retval = ERROR_OK;
1651                 LOG_DEBUG("Running algorithm");
1652
1653
1654         if (target->state != TARGET_HALTED)
1655         {
1656                 LOG_WARNING("target not halted");
1657                 return ERROR_TARGET_NOT_HALTED;
1658         }
1659
1660         // FIXME
1661 //      if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1662 //              return ERROR_FAIL;
1663
1664         // Save regs
1665         for (unsigned i = 0; i < 16; i++)
1666         {
1667                 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1668                 LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
1669         }
1670
1671         cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1672         LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1673
1674         for (int i = 0; i < num_mem_params; i++)
1675         {
1676                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1677         }
1678
1679         // Set register parameters
1680         for (int i = 0; i < num_reg_params; i++)
1681         {
1682                 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1683                 if (!reg)
1684                 {
1685                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1686                         exit(-1);
1687                 }
1688
1689                 if (reg->size != reg_params[i].size)
1690                 {
1691                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1692                         exit(-1);
1693                 }
1694                 arm11_set_reg(reg,reg_params[i].value);
1695 //              printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1696         }
1697
1698         exit_breakpoint_size = 4;
1699
1700 /*      arm11->core_state = arm11_algorithm_info->core_state;
1701         if (arm11->core_state == ARMV4_5_STATE_ARM)
1702                                 exit_breakpoint_size = 4;
1703         else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1704                 exit_breakpoint_size = 2;
1705         else
1706         {
1707                 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1708                 exit(-1);
1709         }
1710 */
1711
1712
1713 /* arm11 at this point only supports ARM not THUMB mode
1714    however if this test needs to be reactivated the current state can be read back
1715    from CPSR */
1716 #if 0
1717         if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1718         {
1719                 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1720                 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1721                 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1722                 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1723         }
1724 #endif
1725
1726         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1727         {
1728                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1729                 retval = ERROR_TARGET_FAILURE;
1730                 goto restore;
1731         }
1732
1733         // no debug, otherwise breakpoint is not set
1734         CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1735
1736         CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1737
1738         if (target->state != TARGET_HALTED)
1739         {
1740                 CHECK_RETVAL(target_halt(target));
1741
1742                 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1743
1744                 retval = ERROR_TARGET_TIMEOUT;
1745
1746                 goto del_breakpoint;
1747         }
1748
1749         if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1750         {
1751                 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1752                         buf_get_u32(arm11->reg_list[15].value, 0, 32));
1753                 retval = ERROR_TARGET_TIMEOUT;
1754                 goto del_breakpoint;
1755         }
1756
1757         for (int i = 0; i < num_mem_params; i++)
1758         {
1759                 if (mem_params[i].direction != PARAM_OUT)
1760                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1761         }
1762
1763         for (int i = 0; i < num_reg_params; i++)
1764         {
1765                 if (reg_params[i].direction != PARAM_OUT)
1766                 {
1767                         reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1768                         if (!reg)
1769                         {
1770                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1771                                 exit(-1);
1772                         }
1773
1774                         if (reg->size != reg_params[i].size)
1775                         {
1776                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1777                                 exit(-1);
1778                         }
1779
1780                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1781                 }
1782         }
1783
1784 del_breakpoint:
1785         breakpoint_remove(target, exit_point);
1786
1787 restore:
1788         // Restore context
1789         for (size_t i = 0; i < 16; i++)
1790         {
1791                 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1792                          arm11->reg_list[i].name, context[i]);
1793                 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1794         }
1795         LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1796         arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1797
1798 //      arm11->core_state = core_state;
1799 //      arm11->core_mode = core_mode;
1800
1801         return retval;
1802 }
1803
1804 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1805 {
1806         FNC_INFO;
1807
1808         NEW(arm11_common_t, arm11, 1);
1809
1810         arm11->target = target;
1811
1812         if (target->tap == NULL)
1813                 return ERROR_FAIL;
1814
1815         if (target->tap->ir_length != 5)
1816         {
1817                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1818                 return ERROR_COMMAND_SYNTAX_ERROR;
1819         }
1820
1821         target->arch_info = arm11;
1822
1823         return ERROR_OK;
1824 }
1825
1826 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1827 {
1828         /* Initialize anything we can set up without talking to the target */
1829         return arm11_build_reg_cache(target);
1830 }
1831
1832 /* talk to the target and set things up */
1833 int arm11_examine(struct target_s *target)
1834 {
1835         int retval;
1836
1837         FNC_INFO;
1838
1839         arm11_common_t * arm11 = target->arch_info;
1840
1841         /* check IDCODE */
1842
1843         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1844
1845         scan_field_t            idcode_field;
1846
1847         arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1848
1849         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1850
1851         /* check DIDR */
1852
1853         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1854
1855         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1856
1857         scan_field_t            chain0_fields[2];
1858
1859         arm11_setup_field(arm11, 32, NULL,      &arm11->didr,           chain0_fields + 0);
1860         arm11_setup_field(arm11,  8, NULL,      &arm11->implementor,    chain0_fields + 1);
1861
1862         arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1863
1864         CHECK_RETVAL(jtag_execute_queue());
1865
1866         switch (arm11->device_id & 0x0FFFF000)
1867         {
1868         case 0x07B36000:        LOG_INFO("found ARM1136"); break;
1869         case 0x07B56000:        LOG_INFO("found ARM1156"); break;
1870         case 0x07B76000:        LOG_INFO("found ARM1176"); break;
1871         default:
1872         {
1873                 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1874                 return ERROR_FAIL;
1875         }
1876         }
1877
1878         arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1879
1880         if (arm11->debug_version != ARM11_DEBUG_V6 &&
1881                 arm11->debug_version != ARM11_DEBUG_V61)
1882         {
1883                 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1884                 return ERROR_FAIL;
1885         }
1886
1887         arm11->brp      = ((arm11->didr >> 24) & 0x0F) + 1;
1888         arm11->wrp      = ((arm11->didr >> 28) & 0x0F) + 1;
1889
1890         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1891         arm11->free_brps = arm11->brp;
1892         arm11->free_wrps = arm11->wrp;
1893
1894         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1895                 arm11->device_id,
1896                 (int)(arm11->implementor),
1897                 arm11->didr);
1898
1899         /* as a side-effect this reads DSCR and thus
1900          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1901          * as suggested by the spec.
1902          */
1903
1904         retval = arm11_check_init(arm11, NULL);
1905         if (retval != ERROR_OK)
1906                 return retval;
1907
1908         target_set_examined(target);
1909
1910         return ERROR_OK;
1911 }
1912
1913
1914 /** Load a register that is marked !valid in the register cache */
1915 int arm11_get_reg(reg_t *reg)
1916 {
1917         FNC_INFO;
1918
1919         target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1920
1921         if (target->state != TARGET_HALTED)
1922         {
1923                 LOG_WARNING("target was not halted");
1924                 return ERROR_TARGET_NOT_HALTED;
1925         }
1926
1927         /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1928
1929 #if 0
1930         arm11_common_t *arm11 = target->arch_info;
1931         const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1932 #endif
1933
1934         return ERROR_OK;
1935 }
1936
1937 /** Change a value in the register cache */
1938 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1939 {
1940         FNC_INFO;
1941
1942         target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1943         arm11_common_t *arm11 = target->arch_info;
1944 //        const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1945
1946         arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1947         reg->valid      = 1;
1948         reg->dirty      = 1;
1949
1950         return ERROR_OK;
1951 }
1952
1953 int arm11_build_reg_cache(target_t *target)
1954 {
1955         arm11_common_t *arm11 = target->arch_info;
1956
1957         NEW(reg_cache_t,                cache,                          1);
1958         NEW(reg_t,                              reg_list,                       ARM11_REGCACHE_COUNT);
1959         NEW(arm11_reg_state_t,  arm11_reg_states,       ARM11_REGCACHE_COUNT);
1960
1961         if (arm11_regs_arch_type == -1)
1962                 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1963
1964         register_init_dummy(&arm11_gdb_dummy_fp_reg);
1965         register_init_dummy(&arm11_gdb_dummy_fps_reg);
1966
1967         arm11->reg_list = reg_list;
1968
1969         /* Build the process context cache */
1970         cache->name             = "arm11 registers";
1971         cache->next             = NULL;
1972         cache->reg_list = reg_list;
1973         cache->num_regs = ARM11_REGCACHE_COUNT;
1974
1975         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1976         (*cache_p) = cache;
1977
1978         arm11->core_cache = cache;
1979 //        armv7m->process_context = cache;
1980
1981         size_t i;
1982
1983         /* Not very elegant assertion */
1984         if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1985                 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1986                 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1987         {
1988                 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1989                 exit(-1);
1990         }
1991
1992         for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1993         {
1994                 reg_t *                                         r       = reg_list                      + i;
1995                 const arm11_reg_defs_t *        rd      = arm11_reg_defs        + i;
1996                 arm11_reg_state_t *                     rs      = arm11_reg_states      + i;
1997
1998                 r->name                         = rd->name;
1999                 r->size                         = 32;
2000                 r->value                        = (uint8_t *)(arm11->reg_values + i);
2001                 r->dirty                        = 0;
2002                 r->valid                        = 0;
2003                 r->bitfield_desc        = NULL;
2004                 r->num_bitfields        = 0;
2005                 r->arch_type            = arm11_regs_arch_type;
2006                 r->arch_info            = rs;
2007
2008                 rs->def_index           = i;
2009                 rs->target                      = target;
2010         }
2011
2012         return ERROR_OK;
2013 }
2014
2015 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
2016 {
2017         if (argc == 0)
2018         {
2019                 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
2020                 return ERROR_OK;
2021         }
2022
2023         if (argc != 1)
2024                 return ERROR_COMMAND_SYNTAX_ERROR;
2025
2026         switch (args[0][0])
2027         {
2028         case '0':       /* 0 */
2029         case 'f':       /* false */
2030         case 'F':
2031         case 'd':       /* disable */
2032         case 'D':
2033                 *var = false;
2034                 break;
2035
2036         case '1':       /* 1 */
2037         case 't':       /* true */
2038         case 'T':
2039         case 'e':       /* enable */
2040         case 'E':
2041                 *var = true;
2042                 break;
2043         }
2044
2045         LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
2046
2047         return ERROR_OK;
2048 }
2049
2050 #define BOOL_WRAPPER(name, print_name)  \
2051 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
2052 { \
2053         return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
2054 }
2055
2056 BOOL_WRAPPER(memwrite_burst,                    "memory write burst mode")
2057 BOOL_WRAPPER(memwrite_error_fatal,              "fatal error mode for memory writes")
2058 BOOL_WRAPPER(step_irq_enable,                   "IRQs while stepping")
2059 BOOL_WRAPPER(hardware_step,                     "hardware single step")
2060
2061 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2062 {
2063         if (argc == 1)
2064         {
2065                 arm11_vcr = strtoul(args[0], NULL, 0);
2066         }
2067         else if (argc != 0)
2068         {
2069                 return ERROR_COMMAND_SYNTAX_ERROR;
2070         }
2071
2072         LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2073         return ERROR_OK;
2074 }
2075
2076 const uint32_t arm11_coproc_instruction_limits[] =
2077 {
2078         15,                             /* coprocessor */
2079         7,                              /* opcode 1 */
2080         15,                             /* CRn */
2081         15,                             /* CRm */
2082         7,                              /* opcode 2 */
2083         0xFFFFFFFF,             /* value */
2084 };
2085
2086 arm11_common_t * arm11_find_target(const char * arg)
2087 {
2088         jtag_tap_t *    tap;
2089         target_t *              t;
2090
2091         tap = jtag_tap_by_string(arg);
2092
2093         if (!tap)
2094                 return 0;
2095
2096         for (t = all_targets; t; t = t->next)
2097         {
2098                 if (t->tap != tap)
2099                         continue;
2100
2101                 /* if (t->type == arm11_target) */
2102                 if (0 == strcmp(target_get_name(t), "arm11"))
2103                         return t->arch_info;
2104         }
2105
2106         return 0;
2107 }
2108
2109 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
2110 {
2111         int retval;
2112
2113         if (argc != (read ? 6 : 7))
2114         {
2115                 LOG_ERROR("Invalid number of arguments.");
2116                 return ERROR_COMMAND_SYNTAX_ERROR;
2117         }
2118
2119         arm11_common_t * arm11 = arm11_find_target(args[0]);
2120
2121         if (!arm11)
2122         {
2123                 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
2124                 return ERROR_COMMAND_SYNTAX_ERROR;
2125         }
2126
2127         if (arm11->target->state != TARGET_HALTED)
2128         {
2129                 LOG_WARNING("target was not halted");
2130                 return ERROR_TARGET_NOT_HALTED;
2131         }
2132
2133         uint32_t        values[6];
2134
2135         for (size_t i = 0; i < (read ? 5 : 6); i++)
2136         {
2137                 values[i] = strtoul(args[i + 1], NULL, 0);
2138
2139                 if (values[i] > arm11_coproc_instruction_limits[i])
2140                 {
2141                         LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
2142                                   (long)(i + 2),
2143                                   arm11_coproc_instruction_limits[i]);
2144                         return ERROR_COMMAND_SYNTAX_ERROR;
2145                 }
2146         }
2147
2148         uint32_t instr = 0xEE000010     |
2149                 (values[0] <<  8) |
2150                 (values[1] << 21) |
2151                 (values[2] << 16) |
2152                 (values[3] <<  0) |
2153                 (values[4] <<  5);
2154
2155         if (read)
2156                 instr |= 0x00100000;
2157
2158         retval = arm11_run_instr_data_prepare(arm11);
2159         if (retval != ERROR_OK)
2160                 return retval;
2161
2162         if (read)
2163         {
2164                 uint32_t result;
2165                 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2166                 if (retval != ERROR_OK)
2167                         return retval;
2168
2169                 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2170                          (int)(values[0]),
2171                          (int)(values[1]),
2172                          (int)(values[2]),
2173                          (int)(values[3]),
2174                          (int)(values[4]), result, result);
2175         }
2176         else
2177         {
2178                 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2179                 if (retval != ERROR_OK)
2180                         return retval;
2181
2182                 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2183                          (int)(values[0]), (int)(values[1]),
2184                          values[5],
2185                          (int)(values[2]), (int)(values[3]), (int)(values[4]));
2186         }
2187
2188         return arm11_run_instr_data_finish(arm11);
2189 }
2190
2191 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2192 {
2193         return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2194 }
2195
2196 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2197 {
2198         return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2199 }
2200
2201 static int arm11_mrc_inner(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value, bool read)
2202 {
2203         int retval;
2204         arm11_common_t * arm11 = target->arch_info;
2205
2206         uint32_t instr = 0xEE000010     |
2207                 (cpnum <<  8) |
2208                 (op1 << 21) |
2209                 (CRn << 16) |
2210                 (CRm <<  0) |
2211                 (op2 <<  5);
2212
2213         if (read)
2214                 instr |= 0x00100000;
2215
2216         retval = arm11_run_instr_data_prepare(arm11);
2217         if (retval != ERROR_OK)
2218                 return retval;
2219
2220         if (read)
2221         {
2222                 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value);
2223                 if (retval != ERROR_OK)
2224                         return retval;
2225         }
2226         else
2227         {
2228                 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value);
2229                 if (retval != ERROR_OK)
2230                         return retval;
2231         }
2232
2233         return arm11_run_instr_data_finish(arm11);
2234 }
2235
2236 static int arm11_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
2237 {
2238         return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
2239 }
2240
2241 static int arm11_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
2242 {
2243         return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
2244 }
2245
2246
2247 int arm11_register_commands(struct command_context_s *cmd_ctx)
2248 {
2249         FNC_INFO;
2250
2251         command_t *top_cmd, *mw_cmd;
2252
2253         top_cmd = register_command(cmd_ctx, NULL, "arm11",
2254                         NULL, COMMAND_ANY, NULL);
2255
2256         /* "hardware_step" is only here to check if the default
2257          * simulate + breakpoint implementation is broken.
2258          * TEMPORARY! NOT DOCUMENTED!
2259          */
2260         register_command(cmd_ctx, top_cmd, "hardware_step",
2261                         arm11_handle_bool_hardware_step, COMMAND_ANY,
2262                         "DEBUG ONLY - Hardware single stepping"
2263                                 " (default: disabled)");
2264
2265         register_command(cmd_ctx, top_cmd, "mcr",
2266                         arm11_handle_mcr, COMMAND_ANY,
2267                         "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
2268
2269         mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2270                         NULL, COMMAND_ANY, NULL);
2271         register_command(cmd_ctx, mw_cmd, "burst",
2272                         arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2273                         "Enable/Disable non-standard but fast burst mode"
2274                                 " (default: enabled)");
2275         register_command(cmd_ctx, mw_cmd, "error_fatal",
2276                         arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2277                         "Terminate program if transfer error was found"
2278                                 " (default: enabled)");
2279
2280         register_command(cmd_ctx, top_cmd, "mrc",
2281                         arm11_handle_mrc, COMMAND_ANY,
2282                         "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
2283         register_command(cmd_ctx, top_cmd, "step_irq_enable",
2284                         arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2285                         "Enable interrupts while stepping"
2286                                 " (default: disabled)");
2287         register_command(cmd_ctx, top_cmd, "vcr",
2288                         arm11_handle_vcr, COMMAND_ANY,
2289                         "Control (Interrupt) Vector Catch Register");
2290
2291         return ERROR_OK;
2292 }