git.gag.com Git - fw/openocd/blob - src/target/arm11.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "etm.h"
  30 #include "breakpoints.h"
  31 #include "arm11_dbgtap.h"
  32 #include "arm_simulator.h"
  33 #include "time_support.h"
  34 #include "target_type.h"
  35 #include "algorithm.h"
  36 #include "register.h"
  37
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 #if 0
  44 #define FNC_INFO        LOG_DEBUG("-")
  45 #else
  46 #define FNC_INFO
  47 #endif
  48
  49 #if 1
  50 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
  51 #else
  52 #define FNC_INFO_NOTIMPLEMENTED
  53 #endif
  54
  55 static bool arm11_config_memwrite_burst = true;
  56 static bool arm11_config_memwrite_error_fatal = true;
  57 static uint32_t arm11_vcr = 0;
  58 static bool arm11_config_step_irq_enable = false;
  59 static bool arm11_config_hardware_step = false;
  60
  61 enum arm11_regtype
  62 {
  63         ARM11_REGISTER_CORE,
  64         ARM11_REGISTER_CPSR,
  65
  66         ARM11_REGISTER_FX,
  67         ARM11_REGISTER_FPS,
  68
  69         ARM11_REGISTER_FIQ,
  70         ARM11_REGISTER_SVC,
  71         ARM11_REGISTER_ABT,
  72         ARM11_REGISTER_IRQ,
  73         ARM11_REGISTER_UND,
  74         ARM11_REGISTER_MON,
  75
  76         ARM11_REGISTER_SPSR_FIQ,
  77         ARM11_REGISTER_SPSR_SVC,
  78         ARM11_REGISTER_SPSR_ABT,
  79         ARM11_REGISTER_SPSR_IRQ,
  80         ARM11_REGISTER_SPSR_UND,
  81         ARM11_REGISTER_SPSR_MON,
  82
  83         /* debug regs */
  84         ARM11_REGISTER_DSCR,
  85         ARM11_REGISTER_WDTR,
  86         ARM11_REGISTER_RDTR,
  87 };
  88
  89
  90 struct arm11_reg_defs
  91 {
  92         char *                                  name;
  93         uint32_t                                                num;
  94         int                                             gdb_num;
  95         enum arm11_regtype              type;
  96 };
  97
  98 /* update arm11_regcache_ids when changing this */
  99 static const struct arm11_reg_defs arm11_reg_defs[] =
 100 {
 101         {"r0",  0,      0,      ARM11_REGISTER_CORE},
 102         {"r1",  1,      1,      ARM11_REGISTER_CORE},
 103         {"r2",  2,      2,      ARM11_REGISTER_CORE},
 104         {"r3",  3,      3,      ARM11_REGISTER_CORE},
 105         {"r4",  4,      4,      ARM11_REGISTER_CORE},
 106         {"r5",  5,      5,      ARM11_REGISTER_CORE},
 107         {"r6",  6,      6,      ARM11_REGISTER_CORE},
 108         {"r7",  7,      7,      ARM11_REGISTER_CORE},
 109         {"r8",  8,      8,      ARM11_REGISTER_CORE},
 110         {"r9",  9,      9,      ARM11_REGISTER_CORE},
 111         {"r10", 10,     10,     ARM11_REGISTER_CORE},
 112         {"r11", 11,     11,     ARM11_REGISTER_CORE},
 113         {"r12", 12,     12,     ARM11_REGISTER_CORE},
 114         {"sp",  13,     13,     ARM11_REGISTER_CORE},
 115         {"lr",  14,     14,     ARM11_REGISTER_CORE},
 116         {"pc",  15,     15,     ARM11_REGISTER_CORE},
 117
 118 #if ARM11_REGCACHE_FREGS
 119         {"f0",  0,      16,     ARM11_REGISTER_FX},
 120         {"f1",  1,      17,     ARM11_REGISTER_FX},
 121         {"f2",  2,      18,     ARM11_REGISTER_FX},
 122         {"f3",  3,      19,     ARM11_REGISTER_FX},
 123         {"f4",  4,      20,     ARM11_REGISTER_FX},
 124         {"f5",  5,      21,     ARM11_REGISTER_FX},
 125         {"f6",  6,      22,     ARM11_REGISTER_FX},
 126         {"f7",  7,      23,     ARM11_REGISTER_FX},
 127         {"fps", 0,      24,     ARM11_REGISTER_FPS},
 128 #endif
 129
 130         {"cpsr",        0,      25,     ARM11_REGISTER_CPSR},
 131
 132 #if ARM11_REGCACHE_MODEREGS
 133         {"r8_fiq",      8,      -1,     ARM11_REGISTER_FIQ},
 134         {"r9_fiq",      9,      -1,     ARM11_REGISTER_FIQ},
 135         {"r10_fiq",     10,     -1,     ARM11_REGISTER_FIQ},
 136         {"r11_fiq",     11,     -1,     ARM11_REGISTER_FIQ},
 137         {"r12_fiq",     12,     -1,     ARM11_REGISTER_FIQ},
 138         {"r13_fiq",     13,     -1,     ARM11_REGISTER_FIQ},
 139         {"r14_fiq",     14,     -1,     ARM11_REGISTER_FIQ},
 140         {"spsr_fiq", 0, -1,     ARM11_REGISTER_SPSR_FIQ},
 141
 142         {"r13_svc",     13,     -1,     ARM11_REGISTER_SVC},
 143         {"r14_svc",     14,     -1,     ARM11_REGISTER_SVC},
 144         {"spsr_svc", 0, -1,     ARM11_REGISTER_SPSR_SVC},
 145
 146         {"r13_abt",     13,     -1,     ARM11_REGISTER_ABT},
 147         {"r14_abt",     14,     -1,     ARM11_REGISTER_ABT},
 148         {"spsr_abt", 0, -1,     ARM11_REGISTER_SPSR_ABT},
 149
 150         {"r13_irq",     13,     -1,     ARM11_REGISTER_IRQ},
 151         {"r14_irq",     14,     -1,     ARM11_REGISTER_IRQ},
 152         {"spsr_irq", 0, -1,     ARM11_REGISTER_SPSR_IRQ},
 153
 154         {"r13_und",     13,     -1,     ARM11_REGISTER_UND},
 155         {"r14_und",     14,     -1,     ARM11_REGISTER_UND},
 156         {"spsr_und", 0, -1,     ARM11_REGISTER_SPSR_UND},
 157
 158         /* ARM1176 only */
 159         {"r13_mon",     13,     -1,     ARM11_REGISTER_MON},
 160         {"r14_mon",     14,     -1,     ARM11_REGISTER_MON},
 161         {"spsr_mon", 0, -1,     ARM11_REGISTER_SPSR_MON},
 162 #endif
 163
 164         /* Debug Registers */
 165         {"dscr",        0,      -1,     ARM11_REGISTER_DSCR},
 166         {"wdtr",        0,      -1,     ARM11_REGISTER_WDTR},
 167         {"rdtr",        0,      -1,     ARM11_REGISTER_RDTR},
 168 };
 169
 170 enum arm11_regcache_ids
 171 {
 172         ARM11_RC_R0,
 173         ARM11_RC_RX                     = ARM11_RC_R0,
 174
 175         ARM11_RC_R1,
 176         ARM11_RC_R2,
 177         ARM11_RC_R3,
 178         ARM11_RC_R4,
 179         ARM11_RC_R5,
 180         ARM11_RC_R6,
 181         ARM11_RC_R7,
 182         ARM11_RC_R8,
 183         ARM11_RC_R9,
 184         ARM11_RC_R10,
 185         ARM11_RC_R11,
 186         ARM11_RC_R12,
 187         ARM11_RC_R13,
 188         ARM11_RC_SP                     = ARM11_RC_R13,
 189         ARM11_RC_R14,
 190         ARM11_RC_LR                     = ARM11_RC_R14,
 191         ARM11_RC_R15,
 192         ARM11_RC_PC                     = ARM11_RC_R15,
 193
 194 #if ARM11_REGCACHE_FREGS
 195         ARM11_RC_F0,
 196         ARM11_RC_FX                     = ARM11_RC_F0,
 197         ARM11_RC_F1,
 198         ARM11_RC_F2,
 199         ARM11_RC_F3,
 200         ARM11_RC_F4,
 201         ARM11_RC_F5,
 202         ARM11_RC_F6,
 203         ARM11_RC_F7,
 204         ARM11_RC_FPS,
 205 #endif
 206
 207         ARM11_RC_CPSR,
 208
 209 #if ARM11_REGCACHE_MODEREGS
 210         ARM11_RC_R8_FIQ,
 211         ARM11_RC_R9_FIQ,
 212         ARM11_RC_R10_FIQ,
 213         ARM11_RC_R11_FIQ,
 214         ARM11_RC_R12_FIQ,
 215         ARM11_RC_R13_FIQ,
 216         ARM11_RC_R14_FIQ,
 217         ARM11_RC_SPSR_FIQ,
 218
 219         ARM11_RC_R13_SVC,
 220         ARM11_RC_R14_SVC,
 221         ARM11_RC_SPSR_SVC,
 222
 223         ARM11_RC_R13_ABT,
 224         ARM11_RC_R14_ABT,
 225         ARM11_RC_SPSR_ABT,
 226
 227         ARM11_RC_R13_IRQ,
 228         ARM11_RC_R14_IRQ,
 229         ARM11_RC_SPSR_IRQ,
 230
 231         ARM11_RC_R13_UND,
 232         ARM11_RC_R14_UND,
 233         ARM11_RC_SPSR_UND,
 234
 235         ARM11_RC_R13_MON,
 236         ARM11_RC_R14_MON,
 237         ARM11_RC_SPSR_MON,
 238 #endif
 239
 240         ARM11_RC_DSCR,
 241         ARM11_RC_WDTR,
 242         ARM11_RC_RDTR,
 243
 244         ARM11_RC_MAX,
 245 };
 246
 247 #define ARM11_GDB_REGISTER_COUNT        26
 248
 249 static int arm11_on_enter_debug_state(struct arm11_common *arm11);
 250 static int arm11_step(struct target *target, int current,
 251                 uint32_t address, int handle_breakpoints);
 252 /* helpers */
 253 static int arm11_build_reg_cache(struct target *target);
 254 static int arm11_set_reg(struct reg *reg, uint8_t *buf);
 255 static int arm11_get_reg(struct reg *reg);
 256
 257 static void arm11_record_register_history(struct arm11_common * arm11);
 258 static void arm11_dump_reg_changes(struct arm11_common * arm11);
 259
 260
 261 /** Check and if necessary take control of the system
 262  *
 263  * \param arm11         Target state variable.
 264  * \param dscr          If the current DSCR content is
 265  *                                      available a pointer to a word holding the
 266  *                                      DSCR can be passed. Otherwise use NULL.
 267  */
 268 static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
 269 {
 270         FNC_INFO;
 271
 272         uint32_t                        dscr_local_tmp_copy;
 273
 274         if (!dscr)
 275         {
 276                 dscr = &dscr_local_tmp_copy;
 277
 278                 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
 279         }
 280
 281         if (!(*dscr & ARM11_DSCR_MODE_SELECT))
 282         {
 283                 LOG_DEBUG("Bringing target into debug mode");
 284
 285                 *dscr |= ARM11_DSCR_MODE_SELECT;                /* Halt debug-mode */
 286                 arm11_write_DSCR(arm11, *dscr);
 287
 288                 /* add further reset initialization here */
 289
 290                 arm11->simulate_reset_on_next_halt = true;
 291
 292                 if (*dscr & ARM11_DSCR_CORE_HALTED)
 293                 {
 294                         /** \todo TODO: this needs further scrutiny because
 295                           * arm11_on_enter_debug_state() never gets properly called.
 296                           * As a result we don't read the actual register states from
 297                           * the target.
 298                           */
 299
 300                         arm11->target->state    = TARGET_HALTED;
 301                         arm11->target->debug_reason     = arm11_get_DSCR_debug_reason(*dscr);
 302                 }
 303                 else
 304                 {
 305                         arm11->target->state    = TARGET_RUNNING;
 306                         arm11->target->debug_reason     = DBG_REASON_NOTHALTED;
 307                 }
 308
 309                 arm11_sc7_clear_vbw(arm11);
 310         }
 311
 312         return ERROR_OK;
 313 }
 314
 315
 316
 317 #define R(x) \
 318         (arm11->reg_values[ARM11_RC_##x])
 319
 320 /** Save processor state.
 321   *
 322   * This is called when the HALT instruction has succeeded
 323   * or on other occasions that stop the processor.
 324   *
 325   */
 326 static int arm11_on_enter_debug_state(struct arm11_common *arm11)
 327 {
 328         int retval;
 329         FNC_INFO;
 330
 331         for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
 332         {
 333                 arm11->reg_list[i].valid        = 1;
 334                 arm11->reg_list[i].dirty        = 0;
 335         }
 336
 337         /* Save DSCR */
 338         CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
 339
 340         /* Save wDTR */
 341
 342         if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
 343         {
 344                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 345
 346                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 347
 348                 struct scan_field       chain5_fields[3];
 349
 350                 arm11_setup_field(arm11, 32, NULL, &R(WDTR),    chain5_fields + 0);
 351                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
 352                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
 353
 354                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 355         }
 356         else
 357         {
 358                 arm11->reg_list[ARM11_RC_WDTR].valid    = 0;
 359         }
 360
 361
 362         /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
 363         /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
 364            ARM1136 seems to require this to issue ITR's as well */
 365
 366         uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
 367
 368         /* this executes JTAG queue: */
 369
 370         arm11_write_DSCR(arm11, new_dscr);
 371
 372
 373         /* From the spec:
 374            Before executing any instruction in debug state you have to drain the write buffer.
 375            This ensures that no imprecise Data Aborts can return at a later point:*/
 376
 377         /** \todo TODO: Test drain write buffer. */
 378
 379 #if 0
 380         while (1)
 381         {
 382                 /* MRC p14,0,R0,c5,c10,0 */
 383                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 384
 385                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 386                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 387
 388                 uint32_t dscr = arm11_read_DSCR(arm11);
 389
 390                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 391
 392                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 393                 {
 394                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 395
 396                         dscr = arm11_read_DSCR(arm11);
 397
 398                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 399
 400                         break;
 401                 }
 402         }
 403 #endif
 404
 405         retval = arm11_run_instr_data_prepare(arm11);
 406         if (retval != ERROR_OK)
 407                 return retval;
 408
 409         /* save r0 - r14 */
 410
 411         /** \todo TODO: handle other mode registers */
 412
 413         for (size_t i = 0; i < 15; i++)
 414         {
 415                 /* MCR p14,0,R?,c0,c5,0 */
 416                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
 417                 if (retval != ERROR_OK)
 418                         return retval;
 419         }
 420
 421         /* save rDTR */
 422
 423         /* check rDTRfull in DSCR */
 424
 425         if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
 426         {
 427                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 428                 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
 429                 if (retval != ERROR_OK)
 430                         return retval;
 431         }
 432         else
 433         {
 434                 arm11->reg_list[ARM11_RC_RDTR].valid    = 0;
 435         }
 436
 437         /* save CPSR */
 438
 439         /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
 440         retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
 441         if (retval != ERROR_OK)
 442                 return retval;
 443
 444         /* save PC */
 445
 446         /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
 447         retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
 448         if (retval != ERROR_OK)
 449                 return retval;
 450
 451         /* adjust PC depending on ARM state */
 452
 453         if (R(CPSR) & ARM11_CPSR_J)     /* Java state */
 454         {
 455                 arm11->reg_values[ARM11_RC_PC] -= 0;
 456         }
 457         else if (R(CPSR) & ARM11_CPSR_T)        /* Thumb state */
 458         {
 459                 arm11->reg_values[ARM11_RC_PC] -= 4;
 460         }
 461         else                                    /* ARM state */
 462         {
 463                 arm11->reg_values[ARM11_RC_PC] -= 8;
 464         }
 465
 466         if (arm11->simulate_reset_on_next_halt)
 467         {
 468                 arm11->simulate_reset_on_next_halt = false;
 469
 470                 LOG_DEBUG("Reset c1 Control Register");
 471
 472                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 473
 474                 /* MCR p15,0,R0,c1,c0,0 */
 475                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 476                 if (retval != ERROR_OK)
 477                         return retval;
 478
 479         }
 480
 481         retval = arm11_run_instr_data_finish(arm11);
 482         if (retval != ERROR_OK)
 483                 return retval;
 484
 485         arm11_dump_reg_changes(arm11);
 486
 487         return ERROR_OK;
 488 }
 489
 490 void arm11_dump_reg_changes(struct arm11_common * arm11)
 491 {
 492
 493         if (!(debug_level >= LOG_LVL_DEBUG))
 494         {
 495                 return;
 496         }
 497
 498         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 499         {
 500                 if (!arm11->reg_list[i].valid)
 501                 {
 502                         if (arm11->reg_history[i].valid)
 503                                 LOG_DEBUG("%8s INVALID   (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
 504                 }
 505                 else
 506                 {
 507                         if (arm11->reg_history[i].valid)
 508                         {
 509                                 if (arm11->reg_history[i].value != arm11->reg_values[i])
 510                                         LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
 511                         }
 512                         else
 513                         {
 514                                 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
 515                         }
 516                 }
 517         }
 518 }
 519
 520 /** Restore processor state
 521   *
 522   * This is called in preparation for the RESTART function.
 523   *
 524   */
 525 static int arm11_leave_debug_state(struct arm11_common *arm11)
 526 {
 527         FNC_INFO;
 528         int retval;
 529
 530         retval = arm11_run_instr_data_prepare(arm11);
 531         if (retval != ERROR_OK)
 532                 return retval;
 533
 534         /** \todo TODO: handle other mode registers */
 535
 536         /* restore R1 - R14 */
 537
 538         for (size_t i = 1; i < 15; i++)
 539         {
 540                 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
 541                         continue;
 542
 543                 /* MRC p14,0,r?,c0,c5,0 */
 544                 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
 545
 546                 //      LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
 547         }
 548
 549         retval = arm11_run_instr_data_finish(arm11);
 550         if (retval != ERROR_OK)
 551                 return retval;
 552
 553         /* spec says clear wDTR and rDTR; we assume they are clear as
 554            otherwise our programming would be sloppy */
 555         {
 556                 uint32_t DSCR;
 557
 558                 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
 559
 560                 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 561                 {
 562                         /*
 563                         The wDTR/rDTR two registers that are used to send/receive data to/from
 564                         the core in tandem with corresponding instruction codes that are
 565                         written into the core. The RDTR FULL/WDTR FULL flag indicates that the
 566                         registers hold data that was written by one side (CPU or JTAG) and not
 567                         read out by the other side.
 568                         */
 569                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 570                         return ERROR_FAIL;
 571                 }
 572         }
 573
 574         retval = arm11_run_instr_data_prepare(arm11);
 575         if (retval != ERROR_OK)
 576                 return retval;
 577
 578         /* restore original wDTR */
 579
 580         if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
 581         {
 582                 /* MCR p14,0,R0,c0,c5,0 */
 583                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
 584                 if (retval != ERROR_OK)
 585                         return retval;
 586         }
 587
 588         /* restore CPSR */
 589
 590         /* MSR CPSR,R0*/
 591         retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
 592         if (retval != ERROR_OK)
 593                 return retval;
 594
 595
 596         /* restore PC */
 597
 598         /* MOV PC,R0 */
 599         retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
 600         if (retval != ERROR_OK)
 601                 return retval;
 602
 603
 604         /* restore R0 */
 605
 606         /* MRC p14,0,r0,c0,c5,0 */
 607         arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
 608
 609         retval = arm11_run_instr_data_finish(arm11);
 610         if (retval != ERROR_OK)
 611                 return retval;
 612
 613         /* restore DSCR */
 614
 615         arm11_write_DSCR(arm11, R(DSCR));
 616
 617         /* restore rDTR */
 618
 619         if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
 620         {
 621                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 622
 623                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 624
 625                 struct scan_field       chain5_fields[3];
 626
 627                 uint8_t                 Ready           = 0;    /* ignored */
 628                 uint8_t                 Valid           = 0;    /* ignored */
 629
 630                 arm11_setup_field(arm11, 32, &R(RDTR),  NULL, chain5_fields + 0);
 631                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 632                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 633
 634                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 635         }
 636
 637         arm11_record_register_history(arm11);
 638
 639         return ERROR_OK;
 640 }
 641
 642 static void arm11_record_register_history(struct arm11_common *arm11)
 643 {
 644         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 645         {
 646                 arm11->reg_history[i].value     = arm11->reg_values[i];
 647                 arm11->reg_history[i].valid     = arm11->reg_list[i].valid;
 648
 649                 arm11->reg_list[i].valid        = 0;
 650                 arm11->reg_list[i].dirty        = 0;
 651         }
 652 }
 653
 654
 655 /* poll current target status */
 656 static int arm11_poll(struct target *target)
 657 {
 658         FNC_INFO;
 659         int retval;
 660         struct arm11_common *arm11 = target_to_arm11(target);
 661         uint32_t        dscr;
 662
 663         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 664
 665         LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 666
 667         CHECK_RETVAL(arm11_check_init(arm11, &dscr));
 668
 669         if (dscr & ARM11_DSCR_CORE_HALTED)
 670         {
 671                 if (target->state != TARGET_HALTED)
 672                 {
 673                         enum target_state old_state = target->state;
 674
 675                         LOG_DEBUG("enter TARGET_HALTED");
 676                         target->state                   = TARGET_HALTED;
 677                         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 678                         retval = arm11_on_enter_debug_state(arm11);
 679                         if (retval != ERROR_OK)
 680                                 return retval;
 681
 682                         target_call_event_callbacks(target,
 683                                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
 684                 }
 685         }
 686         else
 687         {
 688                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 689                 {
 690                         LOG_DEBUG("enter TARGET_RUNNING");
 691                         target->state                   = TARGET_RUNNING;
 692                         target->debug_reason    = DBG_REASON_NOTHALTED;
 693                 }
 694         }
 695
 696         return ERROR_OK;
 697 }
 698 /* architecture specific status reply */
 699 static int arm11_arch_state(struct target *target)
 700 {
 701         struct arm11_common *arm11 = target_to_arm11(target);
 702
 703         LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 704                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 705                          R(CPSR),
 706                          R(PC));
 707
 708         return ERROR_OK;
 709 }
 710
 711 /* target request support */
 712 static int arm11_target_request_data(struct target *target,
 713                 uint32_t size, uint8_t *buffer)
 714 {
 715         FNC_INFO_NOTIMPLEMENTED;
 716
 717         return ERROR_OK;
 718 }
 719
 720 /* target execution control */
 721 static int arm11_halt(struct target *target)
 722 {
 723         FNC_INFO;
 724         struct arm11_common *arm11 = target_to_arm11(target);
 725
 726         LOG_DEBUG("target->state: %s",
 727                 target_state_name(target));
 728
 729         if (target->state == TARGET_UNKNOWN)
 730         {
 731                 arm11->simulate_reset_on_next_halt = true;
 732         }
 733
 734         if (target->state == TARGET_HALTED)
 735         {
 736                 LOG_DEBUG("target was already halted");
 737                 return ERROR_OK;
 738         }
 739
 740         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 741
 742         CHECK_RETVAL(jtag_execute_queue());
 743
 744         uint32_t dscr;
 745
 746         int i = 0;
 747         while (1)
 748         {
 749                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 750
 751                 if (dscr & ARM11_DSCR_CORE_HALTED)
 752                         break;
 753
 754
 755                 long long then = 0;
 756                 if (i == 1000)
 757                 {
 758                         then = timeval_ms();
 759                 }
 760                 if (i >= 1000)
 761                 {
 762                         if ((timeval_ms()-then) > 1000)
 763                         {
 764                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 765                                 return ERROR_FAIL;
 766                         }
 767                 }
 768                 i++;
 769         }
 770
 771         arm11_on_enter_debug_state(arm11);
 772
 773         enum target_state old_state     = target->state;
 774
 775         target->state           = TARGET_HALTED;
 776         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 777
 778         CHECK_RETVAL(
 779                 target_call_event_callbacks(target,
 780                         old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 781
 782         return ERROR_OK;
 783 }
 784
 785 static int arm11_resume(struct target *target, int current,
 786                 uint32_t address, int handle_breakpoints, int debug_execution)
 787 {
 788         FNC_INFO;
 789
 790         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 791         //      current, address, handle_breakpoints, debug_execution);
 792
 793         struct arm11_common *arm11 = target_to_arm11(target);
 794
 795         LOG_DEBUG("target->state: %s",
 796                 target_state_name(target));
 797
 798
 799         if (target->state != TARGET_HALTED)
 800         {
 801                 LOG_ERROR("Target not halted");
 802                 return ERROR_TARGET_NOT_HALTED;
 803         }
 804
 805         if (!current)
 806                 R(PC) = address;
 807
 808         LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 809
 810         /* clear breakpoints/watchpoints and VCR*/
 811         arm11_sc7_clear_vbw(arm11);
 812
 813         /* Set up breakpoints */
 814         if (!debug_execution)
 815         {
 816                 /* check if one matches PC and step over it if necessary */
 817
 818                 struct breakpoint *     bp;
 819
 820                 for (bp = target->breakpoints; bp; bp = bp->next)
 821                 {
 822                         if (bp->address == R(PC))
 823                         {
 824                                 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 825                                 arm11_step(target, 1, 0, 0);
 826                                 break;
 827                         }
 828                 }
 829
 830                 /* set all breakpoints */
 831
 832                 size_t          brp_num = 0;
 833
 834                 for (bp = target->breakpoints; bp; bp = bp->next)
 835                 {
 836                         struct arm11_sc7_action brp[2];
 837
 838                         brp[0].write    = 1;
 839                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 840                         brp[0].value    = bp->address;
 841                         brp[1].write    = 1;
 842                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 843                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 844
 845                         arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
 846
 847                         LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
 848
 849                         brp_num++;
 850                 }
 851
 852                 arm11_sc7_set_vcr(arm11, arm11_vcr);
 853         }
 854
 855         arm11_leave_debug_state(arm11);
 856
 857         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 858
 859         CHECK_RETVAL(jtag_execute_queue());
 860
 861         int i = 0;
 862         while (1)
 863         {
 864                 uint32_t dscr;
 865
 866                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 867
 868                 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 869
 870                 if (dscr & ARM11_DSCR_CORE_RESTARTED)
 871                         break;
 872
 873
 874                 long long then = 0;
 875                 if (i == 1000)
 876                 {
 877                         then = timeval_ms();
 878                 }
 879                 if (i >= 1000)
 880                 {
 881                         if ((timeval_ms()-then) > 1000)
 882                         {
 883                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 884                                 return ERROR_FAIL;
 885                         }
 886                 }
 887                 i++;
 888         }
 889
 890         if (!debug_execution)
 891         {
 892                 target->state                   = TARGET_RUNNING;
 893                 target->debug_reason    = DBG_REASON_NOTHALTED;
 894
 895                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 896         }
 897         else
 898         {
 899                 target->state                   = TARGET_DEBUG_RUNNING;
 900                 target->debug_reason    = DBG_REASON_NOTHALTED;
 901
 902                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 903         }
 904
 905         return ERROR_OK;
 906 }
 907
 908
 909 static int armv4_5_to_arm11(int reg)
 910 {
 911         if (reg < 16)
 912                 return reg;
 913         switch (reg)
 914         {
 915         case ARMV4_5_CPSR:
 916                 return ARM11_RC_CPSR;
 917         case 16:
 918                 /* FIX!!! handle thumb better! */
 919                 return ARM11_RC_CPSR;
 920         default:
 921                 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
 922                 exit(-1);
 923         }
 924 }
 925
 926
 927 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
 928 {
 929         struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 930
 931         reg=armv4_5_to_arm11(reg);
 932
 933         return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
 934 }
 935
 936 static void arm11_sim_set_reg(struct arm_sim_interface *sim,
 937                 int reg, uint32_t value)
 938 {
 939         struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 940
 941         reg=armv4_5_to_arm11(reg);
 942
 943         buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
 944 }
 945
 946 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
 947                 int pos, int bits)
 948 {
 949         struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 950
 951         return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
 952 }
 953
 954 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
 955 {
 956 //      struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 957
 958         /* FIX!!!! we should implement thumb for arm11 */
 959         return ARMV4_5_STATE_ARM;
 960 }
 961
 962 static void arm11_sim_set_state(struct arm_sim_interface *sim,
 963                 enum armv4_5_state mode)
 964 {
 965 //      struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 966
 967         /* FIX!!!! we should implement thumb for arm11 */
 968         LOG_ERROR("Not implemetned!");
 969 }
 970
 971
 972 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
 973 {
 974         //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 975
 976         /* FIX!!!! we should implement something that returns the current mode here!!! */
 977         return ARMV4_5_MODE_USR;
 978 }
 979
 980 static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc)
 981 {
 982         struct arm_sim_interface sim;
 983
 984         sim.user_data=target->arch_info;
 985         sim.get_reg=&arm11_sim_get_reg;
 986         sim.set_reg=&arm11_sim_set_reg;
 987         sim.get_reg_mode=&arm11_sim_get_reg;
 988         sim.set_reg_mode=&arm11_sim_set_reg;
 989         sim.get_cpsr=&arm11_sim_get_cpsr;
 990         sim.get_mode=&arm11_sim_get_mode;
 991         sim.get_state=&arm11_sim_get_state;
 992         sim.set_state=&arm11_sim_set_state;
 993
 994         return arm_simulate_step_core(target, dry_run_pc, &sim);
 995
 996 }
 997
 998 static int arm11_step(struct target *target, int current,
 999                 uint32_t address, int handle_breakpoints)
1000 {
1001         FNC_INFO;
1002
1003         LOG_DEBUG("target->state: %s",
1004                 target_state_name(target));
1005
1006         if (target->state != TARGET_HALTED)
1007         {
1008                 LOG_WARNING("target was not halted");
1009                 return ERROR_TARGET_NOT_HALTED;
1010         }
1011
1012         struct arm11_common *arm11 = target_to_arm11(target);
1013
1014         if (!current)
1015                 R(PC) = address;
1016
1017         LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1018
1019
1020         /** \todo TODO: Thumb not supported here */
1021
1022         uint32_t        next_instruction;
1023
1024         CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1025
1026         /* skip over BKPT */
1027         if ((next_instruction & 0xFFF00070) == 0xe1200070)
1028         {
1029                 R(PC) += 4;
1030                 arm11->reg_list[ARM11_RC_PC].valid = 1;
1031                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1032                 LOG_DEBUG("Skipping BKPT");
1033         }
1034         /* skip over Wait for interrupt / Standby */
1035         /* mcr  15, 0, r?, cr7, cr0, {4} */
1036         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1037         {
1038                 R(PC) += 4;
1039                 arm11->reg_list[ARM11_RC_PC].valid = 1;
1040                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1041                 LOG_DEBUG("Skipping WFI");
1042         }
1043         /* ignore B to self */
1044         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1045         {
1046                 LOG_DEBUG("Not stepping jump to self");
1047         }
1048         else
1049         {
1050                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1051                 * with this. */
1052
1053                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1054                 * the VCR might be something worth looking into. */
1055
1056
1057                 /* Set up breakpoint for stepping */
1058
1059                 struct arm11_sc7_action brp[2];
1060
1061                 brp[0].write    = 1;
1062                 brp[0].address  = ARM11_SC7_BVR0;
1063                 brp[1].write    = 1;
1064                 brp[1].address  = ARM11_SC7_BCR0;
1065
1066                 if (arm11_config_hardware_step)
1067                 {
1068                         /* hardware single stepping be used if possible or is it better to
1069                          * always use the same code path? Hardware single stepping is not supported
1070                          * on all hardware
1071                          */
1072                          brp[0].value   = R(PC);
1073                          brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1074                 } else
1075                 {
1076                         /* sets a breakpoint on the next PC(calculated by simulation),
1077                          */
1078                         uint32_t next_pc;
1079                         int retval;
1080                         retval = arm11_simulate_step(target, &next_pc);
1081                         if (retval != ERROR_OK)
1082                                 return retval;
1083
1084                         brp[0].value    = next_pc;
1085                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1086                 }
1087
1088                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
1089
1090                 /* resume */
1091
1092
1093                 if (arm11_config_step_irq_enable)
1094                         R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;              /* should be redundant */
1095                 else
1096                         R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1097
1098
1099                 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1100
1101                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1102
1103                 CHECK_RETVAL(jtag_execute_queue());
1104
1105                 /* wait for halt */
1106                 int i = 0;
1107                 while (1)
1108                 {
1109                         uint32_t dscr;
1110
1111                         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1112
1113                         LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1114
1115                         if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1116                                 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1117                                 break;
1118
1119                         long long then = 0;
1120                         if (i == 1000)
1121                         {
1122                                 then = timeval_ms();
1123                         }
1124                         if (i >= 1000)
1125                         {
1126                                 if ((timeval_ms()-then) > 1000)
1127                                 {
1128                                         LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1129                                         return ERROR_FAIL;
1130                                 }
1131                         }
1132                         i++;
1133                 }
1134
1135                 /* clear breakpoint */
1136                 arm11_sc7_clear_vbw(arm11);
1137
1138                 /* save state */
1139                 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1140
1141             /* restore default state */
1142                 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1143
1144         }
1145
1146         //        target->state         = TARGET_HALTED;
1147         target->debug_reason    = DBG_REASON_SINGLESTEP;
1148
1149         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1150
1151         return ERROR_OK;
1152 }
1153
1154 static int arm11_assert_reset(struct target *target)
1155 {
1156         FNC_INFO;
1157         int retval;
1158         struct arm11_common *arm11 = target_to_arm11(target);
1159
1160         retval = arm11_check_init(arm11, NULL);
1161         if (retval != ERROR_OK)
1162                 return retval;
1163
1164         target->state = TARGET_UNKNOWN;
1165
1166         /* we would very much like to reset into the halted, state,
1167          * but resetting and halting is second best... */
1168         if (target->reset_halt)
1169         {
1170                 CHECK_RETVAL(target_halt(target));
1171         }
1172
1173
1174         /* srst is funny. We can not do *anything* else while it's asserted
1175          * and it has unkonwn side effects. Make sure no other code runs
1176          * meanwhile.
1177          *
1178          * Code below assumes srst:
1179          *
1180          * - Causes power-on-reset (but of what parts of the system?). Bug
1181          * in arm11?
1182          *
1183          * - Messes us TAP state without asserting trst.
1184          *
1185          * - There is another bug in the arm11 core. When you generate an access to
1186          * external logic (for example ddr controller via AHB bus) and that block
1187          * is not configured (perhaps it is still held in reset), that transaction
1188          * will never complete. This will hang arm11 core but it will also hang
1189          * JTAG controller. Nothing, short of srst assertion will bring it out of
1190          * this.
1191          *
1192          * Mysteries:
1193          *
1194          * - What should the PC be after an srst reset when starting in the halted
1195          * state?
1196          */
1197
1198         jtag_add_reset(0, 1);
1199         jtag_add_reset(0, 0);
1200
1201         /* How long do we have to wait? */
1202         jtag_add_sleep(5000);
1203
1204         /* un-mess up TAP state */
1205         jtag_add_tlr();
1206
1207         retval = jtag_execute_queue();
1208         if (retval != ERROR_OK)
1209         {
1210                 return retval;
1211         }
1212
1213         return ERROR_OK;
1214 }
1215
1216 static int arm11_deassert_reset(struct target *target)
1217 {
1218         return ERROR_OK;
1219 }
1220
1221 static int arm11_soft_reset_halt(struct target *target)
1222 {
1223         FNC_INFO_NOTIMPLEMENTED;
1224
1225         return ERROR_OK;
1226 }
1227
1228 /* target register access for gdb */
1229 static int arm11_get_gdb_reg_list(struct target *target,
1230                 struct reg **reg_list[], int *reg_list_size)
1231 {
1232         FNC_INFO;
1233         struct arm11_common *arm11 = target_to_arm11(target);
1234
1235         *reg_list_size  = ARM11_GDB_REGISTER_COUNT;
1236         *reg_list               = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
1237
1238         /* nine unused legacy FPA registers are expected by GDB */
1239         for (size_t i = 16; i < 24; i++)
1240                 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1241         (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1242
1243         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1244         {
1245                 if (arm11_reg_defs[i].gdb_num == -1)
1246                         continue;
1247
1248                 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1249         }
1250
1251         return ERROR_OK;
1252 }
1253
1254 /* target memory access
1255  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1256  * count: number of items of <size>
1257  *
1258  * arm11_config_memrw_no_increment - in the future we may want to be able
1259  * to read/write a range of data to a "port". a "port" is an action on
1260  * read memory address for some peripheral.
1261  */
1262 static int arm11_read_memory_inner(struct target *target,
1263                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1264                 bool arm11_config_memrw_no_increment)
1265 {
1266         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1267         int retval;
1268
1269         FNC_INFO;
1270
1271         if (target->state != TARGET_HALTED)
1272         {
1273                 LOG_WARNING("target was not halted");
1274                 return ERROR_TARGET_NOT_HALTED;
1275         }
1276
1277         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1278
1279         struct arm11_common *arm11 = target_to_arm11(target);
1280
1281         retval = arm11_run_instr_data_prepare(arm11);
1282         if (retval != ERROR_OK)
1283                 return retval;
1284
1285         /* MRC p14,0,r0,c0,c5,0 */
1286         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1287         if (retval != ERROR_OK)
1288                 return retval;
1289
1290         switch (size)
1291         {
1292         case 1:
1293                 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1294                 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1295
1296                 for (size_t i = 0; i < count; i++)
1297                 {
1298                         /* ldrb    r1, [r0], #1 */
1299                         /* ldrb    r1, [r0] */
1300                         arm11_run_instr_no_data1(arm11,
1301                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1302
1303                         uint32_t res;
1304                         /* MCR p14,0,R1,c0,c5,0 */
1305                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1306
1307                         *buffer++ = res;
1308                 }
1309
1310                 break;
1311
1312         case 2:
1313                 {
1314                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1315
1316                         for (size_t i = 0; i < count; i++)
1317                         {
1318                                 /* ldrh    r1, [r0], #2 */
1319                                 arm11_run_instr_no_data1(arm11,
1320                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1321
1322                                 uint32_t res;
1323
1324                                 /* MCR p14,0,R1,c0,c5,0 */
1325                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1326
1327                                 uint16_t svalue = res;
1328                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1329                         }
1330
1331                         break;
1332                 }
1333
1334         case 4:
1335                 {
1336                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1337                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1338                 uint32_t *words = (uint32_t *)buffer;
1339
1340                 /* LDC p14,c5,[R0],#4 */
1341                 /* LDC p14,c5,[R0] */
1342                 arm11_run_instr_data_from_core(arm11, instr, words, count);
1343                 break;
1344                 }
1345         }
1346
1347         return arm11_run_instr_data_finish(arm11);
1348 }
1349
1350 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1351 {
1352         return arm11_read_memory_inner(target, address, size, count, buffer, false);
1353 }
1354
1355 /*
1356 * arm11_config_memrw_no_increment - in the future we may want to be able
1357 * to read/write a range of data to a "port". a "port" is an action on
1358 * read memory address for some peripheral.
1359 */
1360 static int arm11_write_memory_inner(struct target *target,
1361                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1362                 bool arm11_config_memrw_no_increment)
1363 {
1364         int retval;
1365         FNC_INFO;
1366
1367         if (target->state != TARGET_HALTED)
1368         {
1369                 LOG_WARNING("target was not halted");
1370                 return ERROR_TARGET_NOT_HALTED;
1371         }
1372
1373         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1374
1375         struct arm11_common *arm11 = target_to_arm11(target);
1376
1377         retval = arm11_run_instr_data_prepare(arm11);
1378         if (retval != ERROR_OK)
1379                 return retval;
1380
1381         /* MRC p14,0,r0,c0,c5,0 */
1382         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1383         if (retval != ERROR_OK)
1384                 return retval;
1385
1386         /* burst writes are not used for single words as those may well be
1387          * reset init script writes.
1388          *
1389          * The other advantage is that as burst writes are default, we'll
1390          * now exercise both burst and non-burst code paths with the
1391          * default settings, increasing code coverage.
1392          */
1393         bool burst = arm11_config_memwrite_burst && (count > 1);
1394
1395         switch (size)
1396         {
1397         case 1:
1398                 {
1399                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1400
1401                         for (size_t i = 0; i < count; i++)
1402                         {
1403                                 /* MRC p14,0,r1,c0,c5,0 */
1404                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1405                                 if (retval != ERROR_OK)
1406                                         return retval;
1407
1408                                 /* strb    r1, [r0], #1 */
1409                                 /* strb    r1, [r0] */
1410                                 retval = arm11_run_instr_no_data1(arm11,
1411                                         !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1412                                 if (retval != ERROR_OK)
1413                                         return retval;
1414                         }
1415
1416                         break;
1417                 }
1418
1419         case 2:
1420                 {
1421                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1422
1423                         for (size_t i = 0; i < count; i++)
1424                         {
1425                                 uint16_t value;
1426                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1427
1428                                 /* MRC p14,0,r1,c0,c5,0 */
1429                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1430                                 if (retval != ERROR_OK)
1431                                         return retval;
1432
1433                                 /* strh    r1, [r0], #2 */
1434                                 /* strh    r1, [r0] */
1435                                 retval = arm11_run_instr_no_data1(arm11,
1436                                         !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1437                                 if (retval != ERROR_OK)
1438                                         return retval;
1439                         }
1440
1441                         break;
1442                 }
1443
1444         case 4: {
1445                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1446
1447                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1448                 uint32_t *words = (uint32_t*)buffer;
1449
1450                 if (!burst)
1451                 {
1452                         /* STC p14,c5,[R0],#4 */
1453                         /* STC p14,c5,[R0]*/
1454                         retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1455                         if (retval != ERROR_OK)
1456                                 return retval;
1457                 }
1458                 else
1459                 {
1460                         /* STC p14,c5,[R0],#4 */
1461                         /* STC p14,c5,[R0]*/
1462                         retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1463                         if (retval != ERROR_OK)
1464                                 return retval;
1465                 }
1466
1467                 break;
1468         }
1469         }
1470
1471         /* r0 verification */
1472         if (!arm11_config_memrw_no_increment)
1473         {
1474                 uint32_t r0;
1475
1476                 /* MCR p14,0,R0,c0,c5,0 */
1477                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1478                 if (retval != ERROR_OK)
1479                         return retval;
1480
1481                 if (address + size * count != r0)
1482                 {
1483                         LOG_ERROR("Data transfer failed. Expected end "
1484                                         "address 0x%08x, got 0x%08x",
1485                                         (unsigned) (address + size * count),
1486                                         (unsigned) r0);
1487
1488                         if (burst)
1489                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1490
1491                         if (arm11_config_memwrite_error_fatal)
1492                                 return ERROR_FAIL;
1493                 }
1494         }
1495
1496         return arm11_run_instr_data_finish(arm11);
1497 }
1498
1499 static int arm11_write_memory(struct target *target,
1500                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1501 {
1502         return arm11_write_memory_inner(target, address, size, count, buffer, false);
1503 }
1504
1505 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1506 static int arm11_bulk_write_memory(struct target *target,
1507                 uint32_t address, uint32_t count, uint8_t *buffer)
1508 {
1509         FNC_INFO;
1510
1511         if (target->state != TARGET_HALTED)
1512         {
1513                 LOG_WARNING("target was not halted");
1514                 return ERROR_TARGET_NOT_HALTED;
1515         }
1516
1517         return arm11_write_memory(target, address, 4, count, buffer);
1518 }
1519
1520 /* target break-/watchpoint control
1521 * rw: 0 = write, 1 = read, 2 = access
1522 */
1523 static int arm11_add_breakpoint(struct target *target,
1524                 struct breakpoint *breakpoint)
1525 {
1526         FNC_INFO;
1527         struct arm11_common *arm11 = target_to_arm11(target);
1528
1529 #if 0
1530         if (breakpoint->type == BKPT_SOFT)
1531         {
1532                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1533                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1534         }
1535 #endif
1536
1537         if (!arm11->free_brps)
1538         {
1539                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1540                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1541         }
1542
1543         if (breakpoint->length != 4)
1544         {
1545                 LOG_DEBUG("only breakpoints of four bytes length supported");
1546                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1547         }
1548
1549         arm11->free_brps--;
1550
1551         return ERROR_OK;
1552 }
1553
1554 static int arm11_remove_breakpoint(struct target *target,
1555                 struct breakpoint *breakpoint)
1556 {
1557         FNC_INFO;
1558         struct arm11_common *arm11 = target_to_arm11(target);
1559
1560         arm11->free_brps++;
1561
1562         return ERROR_OK;
1563 }
1564
1565 static int arm11_add_watchpoint(struct target *target,
1566                 struct watchpoint *watchpoint)
1567 {
1568         FNC_INFO_NOTIMPLEMENTED;
1569
1570         return ERROR_OK;
1571 }
1572
1573 static int arm11_remove_watchpoint(struct target *target,
1574                 struct watchpoint *watchpoint)
1575 {
1576         FNC_INFO_NOTIMPLEMENTED;
1577
1578         return ERROR_OK;
1579 }
1580
1581 // HACKHACKHACK - FIXME mode/state
1582 /* target algorithm support */
1583 static int arm11_run_algorithm(struct target *target,
1584                 int num_mem_params, struct mem_param *mem_params,
1585                 int num_reg_params, struct reg_param *reg_params,
1586                 uint32_t entry_point, uint32_t exit_point,
1587                 int timeout_ms, void *arch_info)
1588 {
1589         struct arm11_common *arm11 = target_to_arm11(target);
1590 //      enum armv4_5_state core_state = arm11->core_state;
1591 //      enum armv4_5_mode core_mode = arm11->core_mode;
1592         uint32_t context[16];
1593         uint32_t cpsr;
1594         int exit_breakpoint_size = 0;
1595         int retval = ERROR_OK;
1596                 LOG_DEBUG("Running algorithm");
1597
1598
1599         if (target->state != TARGET_HALTED)
1600         {
1601                 LOG_WARNING("target not halted");
1602                 return ERROR_TARGET_NOT_HALTED;
1603         }
1604
1605         // FIXME
1606 //      if (!is_arm_mode(arm11->core_mode))
1607 //              return ERROR_FAIL;
1608
1609         // Save regs
1610         for (unsigned i = 0; i < 16; i++)
1611         {
1612                 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1613                 LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
1614         }
1615
1616         cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1617         LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1618
1619         for (int i = 0; i < num_mem_params; i++)
1620         {
1621                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1622         }
1623
1624         // Set register parameters
1625         for (int i = 0; i < num_reg_params; i++)
1626         {
1627                 struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1628                 if (!reg)
1629                 {
1630                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1631                         return ERROR_INVALID_ARGUMENTS;
1632                 }
1633
1634                 if (reg->size != reg_params[i].size)
1635                 {
1636                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1637                         return ERROR_INVALID_ARGUMENTS;
1638                 }
1639                 arm11_set_reg(reg,reg_params[i].value);
1640 //              printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1641         }
1642
1643         exit_breakpoint_size = 4;
1644
1645 /*      arm11->core_state = arm11_algorithm_info->core_state;
1646         if (arm11->core_state == ARMV4_5_STATE_ARM)
1647                                 exit_breakpoint_size = 4;
1648         else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1649                 exit_breakpoint_size = 2;
1650         else
1651         {
1652                 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1653                 exit(-1);
1654         }
1655 */
1656
1657
1658 /* arm11 at this point only supports ARM not THUMB mode
1659    however if this test needs to be reactivated the current state can be read back
1660    from CPSR */
1661 #if 0
1662         if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1663         {
1664                 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1665                 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1666                 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1667                 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1668         }
1669 #endif
1670
1671         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1672         {
1673                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1674                 retval = ERROR_TARGET_FAILURE;
1675                 goto restore;
1676         }
1677
1678         // no debug, otherwise breakpoint is not set
1679         CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1680
1681         CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1682
1683         if (target->state != TARGET_HALTED)
1684         {
1685                 CHECK_RETVAL(target_halt(target));
1686
1687                 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1688
1689                 retval = ERROR_TARGET_TIMEOUT;
1690
1691                 goto del_breakpoint;
1692         }
1693
1694         if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1695         {
1696                 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1697                         buf_get_u32(arm11->reg_list[15].value, 0, 32));
1698                 retval = ERROR_TARGET_TIMEOUT;
1699                 goto del_breakpoint;
1700         }
1701
1702         for (int i = 0; i < num_mem_params; i++)
1703         {
1704                 if (mem_params[i].direction != PARAM_OUT)
1705                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1706         }
1707
1708         for (int i = 0; i < num_reg_params; i++)
1709         {
1710                 if (reg_params[i].direction != PARAM_OUT)
1711                 {
1712                         struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1713                         if (!reg)
1714                         {
1715                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1716                                 retval = ERROR_INVALID_ARGUMENTS;
1717                                 goto del_breakpoint;
1718                         }
1719
1720                         if (reg->size != reg_params[i].size)
1721                         {
1722                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1723                                 retval = ERROR_INVALID_ARGUMENTS;
1724                                 goto del_breakpoint;
1725                         }
1726
1727                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1728                 }
1729         }
1730
1731 del_breakpoint:
1732         breakpoint_remove(target, exit_point);
1733
1734 restore:
1735         // Restore context
1736         for (size_t i = 0; i < 16; i++)
1737         {
1738                 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1739                          arm11->reg_list[i].name, context[i]);
1740                 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1741         }
1742         LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1743         arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1744
1745 //      arm11->core_state = core_state;
1746 //      arm11->core_mode = core_mode;
1747
1748         return retval;
1749 }
1750
1751 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1752 {
1753         FNC_INFO;
1754
1755         NEW(struct arm11_common, arm11, 1);
1756
1757         arm11->target = target;
1758
1759         if (target->tap == NULL)
1760                 return ERROR_FAIL;
1761
1762         if (target->tap->ir_length != 5)
1763         {
1764                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1765                 return ERROR_COMMAND_SYNTAX_ERROR;
1766         }
1767
1768         armv4_5_init_arch_info(target, &arm11->arm);
1769
1770         arm11->jtag_info.tap = target->tap;
1771         arm11->jtag_info.scann_size = 5;
1772         arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1773         /* cur_scan_chain == 0 */
1774         arm11->jtag_info.intest_instr = ARM11_INTEST;
1775
1776         return ERROR_OK;
1777 }
1778
1779 static int arm11_init_target(struct command_context *cmd_ctx,
1780                 struct target *target)
1781 {
1782         /* Initialize anything we can set up without talking to the target */
1783         return arm11_build_reg_cache(target);
1784 }
1785
1786 /* talk to the target and set things up */
1787 static int arm11_examine(struct target *target)
1788 {
1789         int retval;
1790
1791         FNC_INFO;
1792         struct arm11_common *arm11 = target_to_arm11(target);
1793
1794         /* check IDCODE */
1795
1796         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1797
1798         struct scan_field               idcode_field;
1799
1800         arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1801
1802         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1803
1804         /* check DIDR */
1805
1806         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1807
1808         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1809
1810         struct scan_field               chain0_fields[2];
1811
1812         arm11_setup_field(arm11, 32, NULL,      &arm11->didr,           chain0_fields + 0);
1813         arm11_setup_field(arm11,  8, NULL,      &arm11->implementor,    chain0_fields + 1);
1814
1815         arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1816
1817         CHECK_RETVAL(jtag_execute_queue());
1818
1819         switch (arm11->device_id & 0x0FFFF000)
1820         {
1821         case 0x07B36000:        LOG_INFO("found ARM1136"); break;
1822         case 0x07B56000:        LOG_INFO("found ARM1156"); break;
1823         case 0x07B76000:        LOG_INFO("found ARM1176"); break;
1824         default:
1825                 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1826                 return ERROR_FAIL;
1827         }
1828
1829         arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1830
1831         if (arm11->debug_version != ARM11_DEBUG_V6 &&
1832                 arm11->debug_version != ARM11_DEBUG_V61)
1833         {
1834                 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1835                 return ERROR_FAIL;
1836         }
1837
1838         arm11->brp      = ((arm11->didr >> 24) & 0x0F) + 1;
1839         arm11->wrp      = ((arm11->didr >> 28) & 0x0F) + 1;
1840
1841         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1842         arm11->free_brps = arm11->brp;
1843         arm11->free_wrps = arm11->wrp;
1844
1845         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1846                 arm11->device_id,
1847                 (int)(arm11->implementor),
1848                 arm11->didr);
1849
1850         /* as a side-effect this reads DSCR and thus
1851          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1852          * as suggested by the spec.
1853          */
1854
1855         retval = arm11_check_init(arm11, NULL);
1856         if (retval != ERROR_OK)
1857                 return retval;
1858
1859         /* ETM on ARM11 still uses original scanchain 6 access mode */
1860         if (arm11->arm.etm && !target_was_examined(target)) {
1861                 *register_get_last_cache_p(&target->reg_cache) =
1862                         etm_build_reg_cache(target, &arm11->jtag_info,
1863                                         arm11->arm.etm);
1864                 retval = etm_setup(target);
1865         }
1866
1867         target_set_examined(target);
1868
1869         return ERROR_OK;
1870 }
1871
1872
1873 /** Load a register that is marked !valid in the register cache */
1874 static int arm11_get_reg(struct reg *reg)
1875 {
1876         FNC_INFO;
1877
1878         struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
1879
1880         if (target->state != TARGET_HALTED)
1881         {
1882                 LOG_WARNING("target was not halted");
1883                 return ERROR_TARGET_NOT_HALTED;
1884         }
1885
1886         /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1887
1888 #if 0
1889         struct arm11_common *arm11 = target_to_arm11(target);
1890         const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1891 #endif
1892
1893         return ERROR_OK;
1894 }
1895
1896 /** Change a value in the register cache */
1897 static int arm11_set_reg(struct reg *reg, uint8_t *buf)
1898 {
1899         FNC_INFO;
1900
1901         struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
1902         struct arm11_common *arm11 = target_to_arm11(target);
1903 //      const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1904
1905         arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1906         reg->valid      = 1;
1907         reg->dirty      = 1;
1908
1909         return ERROR_OK;
1910 }
1911
1912 static const struct reg_arch_type arm11_reg_type = {
1913         .get = arm11_get_reg,
1914         .set = arm11_set_reg,
1915 };
1916
1917 static int arm11_build_reg_cache(struct target *target)
1918 {
1919         struct arm11_common *arm11 = target_to_arm11(target);
1920
1921         NEW(struct reg_cache,           cache,                          1);
1922         NEW(struct reg,                         reg_list,                       ARM11_REGCACHE_COUNT);
1923         NEW(struct arm11_reg_state,     arm11_reg_states,       ARM11_REGCACHE_COUNT);
1924
1925         arm11->reg_list = reg_list;
1926
1927         /* Build the process context cache */
1928         cache->name             = "arm11 registers";
1929         cache->next             = NULL;
1930         cache->reg_list = reg_list;
1931         cache->num_regs = ARM11_REGCACHE_COUNT;
1932
1933         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1934         (*cache_p) = cache;
1935
1936         arm11->core_cache = cache;
1937 //        armv7m->process_context = cache;
1938
1939         size_t i;
1940
1941         /* Not very elegant assertion */
1942         if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
1943                 ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
1944                 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1945         {
1946                 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, ARRAY_SIZE(arm11->reg_values), ARRAY_SIZE(arm11_reg_defs), ARM11_RC_MAX);
1947                 exit(-1);
1948         }
1949
1950         for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1951         {
1952                 struct reg *                                            r       = reg_list                      + i;
1953                 const struct arm11_reg_defs *   rd      = arm11_reg_defs        + i;
1954                 struct arm11_reg_state *                        rs      = arm11_reg_states      + i;
1955
1956                 r->name                         = rd->name;
1957                 r->size                         = 32;
1958                 r->value                        = (uint8_t *)(arm11->reg_values + i);
1959                 r->dirty                        = 0;
1960                 r->valid                        = 0;
1961                 r->type = &arm11_reg_type;
1962                 r->arch_info            = rs;
1963
1964                 rs->def_index           = i;
1965                 rs->target                      = target;
1966         }
1967
1968         return ERROR_OK;
1969 }
1970
1971 static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
1972 {
1973         if (CMD_ARGC == 0)
1974         {
1975                 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1976                 return ERROR_OK;
1977         }
1978
1979         if (CMD_ARGC != 1)
1980                 return ERROR_COMMAND_SYNTAX_ERROR;
1981
1982         switch (CMD_ARGV[0][0])
1983         {
1984         case '0':       /* 0 */
1985         case 'f':       /* false */
1986         case 'F':
1987         case 'd':       /* disable */
1988         case 'D':
1989                 *var = false;
1990                 break;
1991
1992         case '1':       /* 1 */
1993         case 't':       /* true */
1994         case 'T':
1995         case 'e':       /* enable */
1996         case 'E':
1997                 *var = true;
1998                 break;
1999         }
2000
2001         LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
2002
2003         return ERROR_OK;
2004 }
2005
2006 #define BOOL_WRAPPER(name, print_name)  \
2007 COMMAND_HANDLER(arm11_handle_bool_##name) \
2008 { \
2009         return CALL_COMMAND_HANDLER(arm11_handle_bool, \
2010                         &arm11_config_##name, print_name); \
2011 }
2012
2013 BOOL_WRAPPER(memwrite_burst,                    "memory write burst mode")
2014 BOOL_WRAPPER(memwrite_error_fatal,              "fatal error mode for memory writes")
2015 BOOL_WRAPPER(step_irq_enable,                   "IRQs while stepping")
2016 BOOL_WRAPPER(hardware_step,                     "hardware single step")
2017
2018 COMMAND_HANDLER(arm11_handle_vcr)
2019 {
2020         switch (CMD_ARGC) {
2021         case 0:
2022                 break;
2023         case 1:
2024                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
2025                 break;
2026         default:
2027                 return ERROR_COMMAND_SYNTAX_ERROR;
2028         }
2029
2030         LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2031         return ERROR_OK;
2032 }
2033
2034 static const uint32_t arm11_coproc_instruction_limits[] =
2035 {
2036         15,                             /* coprocessor */
2037         7,                              /* opcode 1 */
2038         15,                             /* CRn */
2039         15,                             /* CRm */
2040         7,                              /* opcode 2 */
2041         0xFFFFFFFF,             /* value */
2042 };
2043
2044 static int arm11_mrc_inner(struct target *target, int cpnum,
2045                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
2046                 uint32_t *value, bool read)
2047 {
2048         int retval;
2049         struct arm11_common *arm11 = target_to_arm11(target);
2050
2051         if (target->state != TARGET_HALTED)
2052         {
2053                 LOG_ERROR("Target not halted");
2054                 return ERROR_FAIL;
2055         }
2056
2057         uint32_t instr = 0xEE000010     |
2058                 (cpnum <<  8) |
2059                 (op1 << 21) |
2060                 (CRn << 16) |
2061                 (CRm <<  0) |
2062                 (op2 <<  5);
2063
2064         if (read)
2065                 instr |= 0x00100000;
2066
2067         retval = arm11_run_instr_data_prepare(arm11);
2068         if (retval != ERROR_OK)
2069                 return retval;
2070
2071         if (read)
2072         {
2073                 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value);
2074                 if (retval != ERROR_OK)
2075                         return retval;
2076         }
2077         else
2078         {
2079                 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value);
2080                 if (retval != ERROR_OK)
2081                         return retval;
2082         }
2083
2084         return arm11_run_instr_data_finish(arm11);
2085 }
2086
2087 static int arm11_mrc(struct target *target, int cpnum,
2088                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
2089 {
2090         return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
2091 }
2092
2093 static int arm11_mcr(struct target *target, int cpnum,
2094                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
2095 {
2096         return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
2097 }
2098
2099 static int arm11_register_commands(struct command_context *cmd_ctx)
2100 {
2101         FNC_INFO;
2102
2103         struct command *top_cmd, *mw_cmd;
2104
2105         armv4_5_register_commands(cmd_ctx);
2106
2107         top_cmd = register_command(cmd_ctx, NULL, "arm11",
2108                         NULL, COMMAND_ANY, NULL);
2109
2110         /* "hardware_step" is only here to check if the default
2111          * simulate + breakpoint implementation is broken.
2112          * TEMPORARY! NOT DOCUMENTED!
2113          */
2114         register_command(cmd_ctx, top_cmd, "hardware_step",
2115                         arm11_handle_bool_hardware_step, COMMAND_ANY,
2116                         "DEBUG ONLY - Hardware single stepping"
2117                                 " (default: disabled)");
2118
2119         mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2120                         NULL, COMMAND_ANY, NULL);
2121         register_command(cmd_ctx, mw_cmd, "burst",
2122                         arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2123                         "Enable/Disable non-standard but fast burst mode"
2124                                 " (default: enabled)");
2125         register_command(cmd_ctx, mw_cmd, "error_fatal",
2126                         arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2127                         "Terminate program if transfer error was found"
2128                                 " (default: enabled)");
2129
2130         register_command(cmd_ctx, top_cmd, "step_irq_enable",
2131                         arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2132                         "Enable interrupts while stepping"
2133                                 " (default: disabled)");
2134         register_command(cmd_ctx, top_cmd, "vcr",
2135                         arm11_handle_vcr, COMMAND_ANY,
2136                         "Control (Interrupt) Vector Catch Register");
2137
2138         return etm_register_commands(cmd_ctx);
2139 }
2140
2141 /** Holds methods for ARM11xx targets. */
2142 struct target_type arm11_target = {
2143         .name =                 "arm11",
2144
2145         .poll =                 arm11_poll,
2146         .arch_state =           arm11_arch_state,
2147
2148         .target_request_data =  arm11_target_request_data,
2149
2150         .halt =                 arm11_halt,
2151         .resume =               arm11_resume,
2152         .step =                 arm11_step,
2153
2154         .assert_reset =         arm11_assert_reset,
2155         .deassert_reset =       arm11_deassert_reset,
2156         .soft_reset_halt =      arm11_soft_reset_halt,
2157
2158         .get_gdb_reg_list =     arm11_get_gdb_reg_list,
2159
2160         .read_memory =          arm11_read_memory,
2161         .write_memory =         arm11_write_memory,
2162
2163         .bulk_write_memory =    arm11_bulk_write_memory,
2164
2165         .checksum_memory =      arm_checksum_memory,
2166         .blank_check_memory =   arm_blank_check_memory,
2167
2168         .add_breakpoint =       arm11_add_breakpoint,
2169         .remove_breakpoint =    arm11_remove_breakpoint,
2170         .add_watchpoint =       arm11_add_watchpoint,
2171         .remove_watchpoint =    arm11_remove_watchpoint,
2172
2173         .run_algorithm =        arm11_run_algorithm,
2174
2175         .register_commands =    arm11_register_commands,
2176         .target_create =        arm11_target_create,
2177         .init_target =          arm11_init_target,
2178         .examine =              arm11_examine,
2179
2180         .mrc =                  arm11_mrc,
2181         .mcr =                  arm11_mcr,
2182 };