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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "arm11.h"
  30 #include "arm11_dbgtap.h"
  31 #include "armv4_5.h"
  32 #include "arm_simulator.h"
  33 #include "time_support.h"
  34 #include "target_type.h"
  35
  36
  37 #if 0
  38 #define _DEBUG_INSTRUCTION_EXECUTION_
  39 #endif
  40
  41 #if 0
  42 #define FNC_INFO        LOG_DEBUG("-")
  43 #else
  44 #define FNC_INFO
  45 #endif
  46
  47 #if 1
  48 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
  49 #else
  50 #define FNC_INFO_NOTIMPLEMENTED
  51 #endif
  52
  53 static bool arm11_config_memwrite_burst = true;
  54 static bool arm11_config_memwrite_error_fatal = true;
  55 static uint32_t arm11_vcr = 0;
  56 static bool arm11_config_step_irq_enable = false;
  57 static bool arm11_config_hardware_step = false;
  58
  59 static int arm11_regs_arch_type = -1;
  60
  61 enum arm11_regtype
  62 {
  63         ARM11_REGISTER_CORE,
  64         ARM11_REGISTER_CPSR,
  65
  66         ARM11_REGISTER_FX,
  67         ARM11_REGISTER_FPS,
  68
  69         ARM11_REGISTER_FIQ,
  70         ARM11_REGISTER_SVC,
  71         ARM11_REGISTER_ABT,
  72         ARM11_REGISTER_IRQ,
  73         ARM11_REGISTER_UND,
  74         ARM11_REGISTER_MON,
  75
  76         ARM11_REGISTER_SPSR_FIQ,
  77         ARM11_REGISTER_SPSR_SVC,
  78         ARM11_REGISTER_SPSR_ABT,
  79         ARM11_REGISTER_SPSR_IRQ,
  80         ARM11_REGISTER_SPSR_UND,
  81         ARM11_REGISTER_SPSR_MON,
  82
  83         /* debug regs */
  84         ARM11_REGISTER_DSCR,
  85         ARM11_REGISTER_WDTR,
  86         ARM11_REGISTER_RDTR,
  87 };
  88
  89
  90 struct arm11_reg_defs
  91 {
  92         char *                                  name;
  93         uint32_t                                                num;
  94         int                                             gdb_num;
  95         enum arm11_regtype              type;
  96 };
  97
  98 /* update arm11_regcache_ids when changing this */
  99 static const struct arm11_reg_defs arm11_reg_defs[] =
 100 {
 101         {"r0",  0,      0,      ARM11_REGISTER_CORE},
 102         {"r1",  1,      1,      ARM11_REGISTER_CORE},
 103         {"r2",  2,      2,      ARM11_REGISTER_CORE},
 104         {"r3",  3,      3,      ARM11_REGISTER_CORE},
 105         {"r4",  4,      4,      ARM11_REGISTER_CORE},
 106         {"r5",  5,      5,      ARM11_REGISTER_CORE},
 107         {"r6",  6,      6,      ARM11_REGISTER_CORE},
 108         {"r7",  7,      7,      ARM11_REGISTER_CORE},
 109         {"r8",  8,      8,      ARM11_REGISTER_CORE},
 110         {"r9",  9,      9,      ARM11_REGISTER_CORE},
 111         {"r10", 10,     10,     ARM11_REGISTER_CORE},
 112         {"r11", 11,     11,     ARM11_REGISTER_CORE},
 113         {"r12", 12,     12,     ARM11_REGISTER_CORE},
 114         {"sp",  13,     13,     ARM11_REGISTER_CORE},
 115         {"lr",  14,     14,     ARM11_REGISTER_CORE},
 116         {"pc",  15,     15,     ARM11_REGISTER_CORE},
 117
 118 #if ARM11_REGCACHE_FREGS
 119         {"f0",  0,      16,     ARM11_REGISTER_FX},
 120         {"f1",  1,      17,     ARM11_REGISTER_FX},
 121         {"f2",  2,      18,     ARM11_REGISTER_FX},
 122         {"f3",  3,      19,     ARM11_REGISTER_FX},
 123         {"f4",  4,      20,     ARM11_REGISTER_FX},
 124         {"f5",  5,      21,     ARM11_REGISTER_FX},
 125         {"f6",  6,      22,     ARM11_REGISTER_FX},
 126         {"f7",  7,      23,     ARM11_REGISTER_FX},
 127         {"fps", 0,      24,     ARM11_REGISTER_FPS},
 128 #endif
 129
 130         {"cpsr",        0,      25,     ARM11_REGISTER_CPSR},
 131
 132 #if ARM11_REGCACHE_MODEREGS
 133         {"r8_fiq",      8,      -1,     ARM11_REGISTER_FIQ},
 134         {"r9_fiq",      9,      -1,     ARM11_REGISTER_FIQ},
 135         {"r10_fiq",     10,     -1,     ARM11_REGISTER_FIQ},
 136         {"r11_fiq",     11,     -1,     ARM11_REGISTER_FIQ},
 137         {"r12_fiq",     12,     -1,     ARM11_REGISTER_FIQ},
 138         {"r13_fiq",     13,     -1,     ARM11_REGISTER_FIQ},
 139         {"r14_fiq",     14,     -1,     ARM11_REGISTER_FIQ},
 140         {"spsr_fiq", 0, -1,     ARM11_REGISTER_SPSR_FIQ},
 141
 142         {"r13_svc",     13,     -1,     ARM11_REGISTER_SVC},
 143         {"r14_svc",     14,     -1,     ARM11_REGISTER_SVC},
 144         {"spsr_svc", 0, -1,     ARM11_REGISTER_SPSR_SVC},
 145
 146         {"r13_abt",     13,     -1,     ARM11_REGISTER_ABT},
 147         {"r14_abt",     14,     -1,     ARM11_REGISTER_ABT},
 148         {"spsr_abt", 0, -1,     ARM11_REGISTER_SPSR_ABT},
 149
 150         {"r13_irq",     13,     -1,     ARM11_REGISTER_IRQ},
 151         {"r14_irq",     14,     -1,     ARM11_REGISTER_IRQ},
 152         {"spsr_irq", 0, -1,     ARM11_REGISTER_SPSR_IRQ},
 153
 154         {"r13_und",     13,     -1,     ARM11_REGISTER_UND},
 155         {"r14_und",     14,     -1,     ARM11_REGISTER_UND},
 156         {"spsr_und", 0, -1,     ARM11_REGISTER_SPSR_UND},
 157
 158         /* ARM1176 only */
 159         {"r13_mon",     13,     -1,     ARM11_REGISTER_MON},
 160         {"r14_mon",     14,     -1,     ARM11_REGISTER_MON},
 161         {"spsr_mon", 0, -1,     ARM11_REGISTER_SPSR_MON},
 162 #endif
 163
 164         /* Debug Registers */
 165         {"dscr",        0,      -1,     ARM11_REGISTER_DSCR},
 166         {"wdtr",        0,      -1,     ARM11_REGISTER_WDTR},
 167         {"rdtr",        0,      -1,     ARM11_REGISTER_RDTR},
 168 };
 169
 170 enum arm11_regcache_ids
 171 {
 172         ARM11_RC_R0,
 173         ARM11_RC_RX                     = ARM11_RC_R0,
 174
 175         ARM11_RC_R1,
 176         ARM11_RC_R2,
 177         ARM11_RC_R3,
 178         ARM11_RC_R4,
 179         ARM11_RC_R5,
 180         ARM11_RC_R6,
 181         ARM11_RC_R7,
 182         ARM11_RC_R8,
 183         ARM11_RC_R9,
 184         ARM11_RC_R10,
 185         ARM11_RC_R11,
 186         ARM11_RC_R12,
 187         ARM11_RC_R13,
 188         ARM11_RC_SP                     = ARM11_RC_R13,
 189         ARM11_RC_R14,
 190         ARM11_RC_LR                     = ARM11_RC_R14,
 191         ARM11_RC_R15,
 192         ARM11_RC_PC                     = ARM11_RC_R15,
 193
 194 #if ARM11_REGCACHE_FREGS
 195         ARM11_RC_F0,
 196         ARM11_RC_FX                     = ARM11_RC_F0,
 197         ARM11_RC_F1,
 198         ARM11_RC_F2,
 199         ARM11_RC_F3,
 200         ARM11_RC_F4,
 201         ARM11_RC_F5,
 202         ARM11_RC_F6,
 203         ARM11_RC_F7,
 204         ARM11_RC_FPS,
 205 #endif
 206
 207         ARM11_RC_CPSR,
 208
 209 #if ARM11_REGCACHE_MODEREGS
 210         ARM11_RC_R8_FIQ,
 211         ARM11_RC_R9_FIQ,
 212         ARM11_RC_R10_FIQ,
 213         ARM11_RC_R11_FIQ,
 214         ARM11_RC_R12_FIQ,
 215         ARM11_RC_R13_FIQ,
 216         ARM11_RC_R14_FIQ,
 217         ARM11_RC_SPSR_FIQ,
 218
 219         ARM11_RC_R13_SVC,
 220         ARM11_RC_R14_SVC,
 221         ARM11_RC_SPSR_SVC,
 222
 223         ARM11_RC_R13_ABT,
 224         ARM11_RC_R14_ABT,
 225         ARM11_RC_SPSR_ABT,
 226
 227         ARM11_RC_R13_IRQ,
 228         ARM11_RC_R14_IRQ,
 229         ARM11_RC_SPSR_IRQ,
 230
 231         ARM11_RC_R13_UND,
 232         ARM11_RC_R14_UND,
 233         ARM11_RC_SPSR_UND,
 234
 235         ARM11_RC_R13_MON,
 236         ARM11_RC_R14_MON,
 237         ARM11_RC_SPSR_MON,
 238 #endif
 239
 240         ARM11_RC_DSCR,
 241         ARM11_RC_WDTR,
 242         ARM11_RC_RDTR,
 243
 244         ARM11_RC_MAX,
 245 };
 246
 247 #define ARM11_GDB_REGISTER_COUNT        26
 248
 249 /* FIXME these are *identical* to the ARMv4_5 dummies ...  except
 250  * for their names, and being static vs global, and having different
 251  * addresses.  Ditto ARMv7a and ARMv7m dummies.
 252  */
 253
 254 static uint8_t arm11_gdb_dummy_fp_value[12];
 255
 256 static struct reg arm11_gdb_dummy_fp_reg =
 257 {
 258         .name = "GDB dummy floating-point register",
 259         .value = arm11_gdb_dummy_fp_value,
 260         .dirty = 0,
 261         .valid = 1,
 262         .size = 96,
 263         .arch_info = NULL,
 264         .arch_type = 0,
 265 };
 266
 267 static uint8_t arm11_gdb_dummy_fps_value[4];
 268
 269 static struct reg arm11_gdb_dummy_fps_reg =
 270 {
 271         .name = "GDB dummy floating-point status register",
 272         .value = arm11_gdb_dummy_fps_value,
 273         .dirty = 0,
 274         .valid = 1,
 275         .size = 32,
 276         .arch_info = NULL,
 277         .arch_type = 0,
 278 };
 279
 280
 281 static int arm11_on_enter_debug_state(struct arm11_common *arm11);
 282 static int arm11_step(struct target *target, int current,
 283                 uint32_t address, int handle_breakpoints);
 284 /* helpers */
 285 static int arm11_build_reg_cache(struct target *target);
 286 static int arm11_set_reg(struct reg *reg, uint8_t *buf);
 287 static int arm11_get_reg(struct reg *reg);
 288
 289 static void arm11_record_register_history(struct arm11_common * arm11);
 290 static void arm11_dump_reg_changes(struct arm11_common * arm11);
 291
 292
 293 /** Check and if necessary take control of the system
 294  *
 295  * \param arm11         Target state variable.
 296  * \param dscr          If the current DSCR content is
 297  *                                      available a pointer to a word holding the
 298  *                                      DSCR can be passed. Otherwise use NULL.
 299  */
 300 static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
 301 {
 302         FNC_INFO;
 303
 304         uint32_t                        dscr_local_tmp_copy;
 305
 306         if (!dscr)
 307         {
 308                 dscr = &dscr_local_tmp_copy;
 309
 310                 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
 311         }
 312
 313         if (!(*dscr & ARM11_DSCR_MODE_SELECT))
 314         {
 315                 LOG_DEBUG("Bringing target into debug mode");
 316
 317                 *dscr |= ARM11_DSCR_MODE_SELECT;                /* Halt debug-mode */
 318                 arm11_write_DSCR(arm11, *dscr);
 319
 320                 /* add further reset initialization here */
 321
 322                 arm11->simulate_reset_on_next_halt = true;
 323
 324                 if (*dscr & ARM11_DSCR_CORE_HALTED)
 325                 {
 326                         /** \todo TODO: this needs further scrutiny because
 327                           * arm11_on_enter_debug_state() never gets properly called.
 328                           * As a result we don't read the actual register states from
 329                           * the target.
 330                           */
 331
 332                         arm11->target->state    = TARGET_HALTED;
 333                         arm11->target->debug_reason     = arm11_get_DSCR_debug_reason(*dscr);
 334                 }
 335                 else
 336                 {
 337                         arm11->target->state    = TARGET_RUNNING;
 338                         arm11->target->debug_reason     = DBG_REASON_NOTHALTED;
 339                 }
 340
 341                 arm11_sc7_clear_vbw(arm11);
 342         }
 343
 344         return ERROR_OK;
 345 }
 346
 347
 348
 349 #define R(x) \
 350         (arm11->reg_values[ARM11_RC_##x])
 351
 352 /** Save processor state.
 353   *
 354   * This is called when the HALT instruction has succeeded
 355   * or on other occasions that stop the processor.
 356   *
 357   */
 358 static int arm11_on_enter_debug_state(struct arm11_common *arm11)
 359 {
 360         int retval;
 361         FNC_INFO;
 362
 363         for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
 364         {
 365                 arm11->reg_list[i].valid        = 1;
 366                 arm11->reg_list[i].dirty        = 0;
 367         }
 368
 369         /* Save DSCR */
 370         CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
 371
 372         /* Save wDTR */
 373
 374         if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
 375         {
 376                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 377
 378                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 379
 380                 struct scan_field       chain5_fields[3];
 381
 382                 arm11_setup_field(arm11, 32, NULL, &R(WDTR),    chain5_fields + 0);
 383                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
 384                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
 385
 386                 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 387         }
 388         else
 389         {
 390                 arm11->reg_list[ARM11_RC_WDTR].valid    = 0;
 391         }
 392
 393
 394         /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
 395         /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
 396            ARM1136 seems to require this to issue ITR's as well */
 397
 398         uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
 399
 400         /* this executes JTAG queue: */
 401
 402         arm11_write_DSCR(arm11, new_dscr);
 403
 404
 405         /* From the spec:
 406            Before executing any instruction in debug state you have to drain the write buffer.
 407            This ensures that no imprecise Data Aborts can return at a later point:*/
 408
 409         /** \todo TODO: Test drain write buffer. */
 410
 411 #if 0
 412         while (1)
 413         {
 414                 /* MRC p14,0,R0,c5,c10,0 */
 415                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 416
 417                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 418                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 419
 420                 uint32_t dscr = arm11_read_DSCR(arm11);
 421
 422                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 423
 424                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 425                 {
 426                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 427
 428                         dscr = arm11_read_DSCR(arm11);
 429
 430                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 431
 432                         break;
 433                 }
 434         }
 435 #endif
 436
 437         retval = arm11_run_instr_data_prepare(arm11);
 438         if (retval != ERROR_OK)
 439                 return retval;
 440
 441         /* save r0 - r14 */
 442
 443         /** \todo TODO: handle other mode registers */
 444
 445         for (size_t i = 0; i < 15; i++)
 446         {
 447                 /* MCR p14,0,R?,c0,c5,0 */
 448                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
 449                 if (retval != ERROR_OK)
 450                         return retval;
 451         }
 452
 453         /* save rDTR */
 454
 455         /* check rDTRfull in DSCR */
 456
 457         if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
 458         {
 459                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 460                 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
 461                 if (retval != ERROR_OK)
 462                         return retval;
 463         }
 464         else
 465         {
 466                 arm11->reg_list[ARM11_RC_RDTR].valid    = 0;
 467         }
 468
 469         /* save CPSR */
 470
 471         /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
 472         retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
 473         if (retval != ERROR_OK)
 474                 return retval;
 475
 476         /* save PC */
 477
 478         /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
 479         retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
 480         if (retval != ERROR_OK)
 481                 return retval;
 482
 483         /* adjust PC depending on ARM state */
 484
 485         if (R(CPSR) & ARM11_CPSR_J)     /* Java state */
 486         {
 487                 arm11->reg_values[ARM11_RC_PC] -= 0;
 488         }
 489         else if (R(CPSR) & ARM11_CPSR_T)        /* Thumb state */
 490         {
 491                 arm11->reg_values[ARM11_RC_PC] -= 4;
 492         }
 493         else                                    /* ARM state */
 494         {
 495                 arm11->reg_values[ARM11_RC_PC] -= 8;
 496         }
 497
 498         if (arm11->simulate_reset_on_next_halt)
 499         {
 500                 arm11->simulate_reset_on_next_halt = false;
 501
 502                 LOG_DEBUG("Reset c1 Control Register");
 503
 504                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 505
 506                 /* MCR p15,0,R0,c1,c0,0 */
 507                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 508                 if (retval != ERROR_OK)
 509                         return retval;
 510
 511         }
 512
 513         retval = arm11_run_instr_data_finish(arm11);
 514         if (retval != ERROR_OK)
 515                 return retval;
 516
 517         arm11_dump_reg_changes(arm11);
 518
 519         return ERROR_OK;
 520 }
 521
 522 void arm11_dump_reg_changes(struct arm11_common * arm11)
 523 {
 524
 525         if (!(debug_level >= LOG_LVL_DEBUG))
 526         {
 527                 return;
 528         }
 529
 530         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 531         {
 532                 if (!arm11->reg_list[i].valid)
 533                 {
 534                         if (arm11->reg_history[i].valid)
 535                                 LOG_DEBUG("%8s INVALID   (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
 536                 }
 537                 else
 538                 {
 539                         if (arm11->reg_history[i].valid)
 540                         {
 541                                 if (arm11->reg_history[i].value != arm11->reg_values[i])
 542                                         LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
 543                         }
 544                         else
 545                         {
 546                                 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
 547                         }
 548                 }
 549         }
 550 }
 551
 552 /** Restore processor state
 553   *
 554   * This is called in preparation for the RESTART function.
 555   *
 556   */
 557 static int arm11_leave_debug_state(struct arm11_common *arm11)
 558 {
 559         FNC_INFO;
 560         int retval;
 561
 562         retval = arm11_run_instr_data_prepare(arm11);
 563         if (retval != ERROR_OK)
 564                 return retval;
 565
 566         /** \todo TODO: handle other mode registers */
 567
 568         /* restore R1 - R14 */
 569
 570         for (size_t i = 1; i < 15; i++)
 571         {
 572                 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
 573                         continue;
 574
 575                 /* MRC p14,0,r?,c0,c5,0 */
 576                 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
 577
 578                 //      LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
 579         }
 580
 581         retval = arm11_run_instr_data_finish(arm11);
 582         if (retval != ERROR_OK)
 583                 return retval;
 584
 585         /* spec says clear wDTR and rDTR; we assume they are clear as
 586            otherwise our programming would be sloppy */
 587         {
 588                 uint32_t DSCR;
 589
 590                 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
 591
 592                 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 593                 {
 594                         /*
 595                         The wDTR/rDTR two registers that are used to send/receive data to/from
 596                         the core in tandem with corresponding instruction codes that are
 597                         written into the core. The RDTR FULL/WDTR FULL flag indicates that the
 598                         registers hold data that was written by one side (CPU or JTAG) and not
 599                         read out by the other side.
 600                         */
 601                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 602                         return ERROR_FAIL;
 603                 }
 604         }
 605
 606         retval = arm11_run_instr_data_prepare(arm11);
 607         if (retval != ERROR_OK)
 608                 return retval;
 609
 610         /* restore original wDTR */
 611
 612         if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
 613         {
 614                 /* MCR p14,0,R0,c0,c5,0 */
 615                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
 616                 if (retval != ERROR_OK)
 617                         return retval;
 618         }
 619
 620         /* restore CPSR */
 621
 622         /* MSR CPSR,R0*/
 623         retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
 624         if (retval != ERROR_OK)
 625                 return retval;
 626
 627
 628         /* restore PC */
 629
 630         /* MOV PC,R0 */
 631         retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
 632         if (retval != ERROR_OK)
 633                 return retval;
 634
 635
 636         /* restore R0 */
 637
 638         /* MRC p14,0,r0,c0,c5,0 */
 639         arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
 640
 641         retval = arm11_run_instr_data_finish(arm11);
 642         if (retval != ERROR_OK)
 643                 return retval;
 644
 645         /* restore DSCR */
 646
 647         arm11_write_DSCR(arm11, R(DSCR));
 648
 649         /* restore rDTR */
 650
 651         if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
 652         {
 653                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 654
 655                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 656
 657                 struct scan_field       chain5_fields[3];
 658
 659                 uint8_t                 Ready           = 0;    /* ignored */
 660                 uint8_t                 Valid           = 0;    /* ignored */
 661
 662                 arm11_setup_field(arm11, 32, &R(RDTR),  NULL, chain5_fields + 0);
 663                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 664                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 665
 666                 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 667         }
 668
 669         arm11_record_register_history(arm11);
 670
 671         return ERROR_OK;
 672 }
 673
 674 static void arm11_record_register_history(struct arm11_common *arm11)
 675 {
 676         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 677         {
 678                 arm11->reg_history[i].value     = arm11->reg_values[i];
 679                 arm11->reg_history[i].valid     = arm11->reg_list[i].valid;
 680
 681                 arm11->reg_list[i].valid        = 0;
 682                 arm11->reg_list[i].dirty        = 0;
 683         }
 684 }
 685
 686
 687 /* poll current target status */
 688 static int arm11_poll(struct target *target)
 689 {
 690         FNC_INFO;
 691         int retval;
 692         struct arm11_common *arm11 = target_to_arm11(target);
 693         uint32_t        dscr;
 694
 695         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 696
 697         LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 698
 699         CHECK_RETVAL(arm11_check_init(arm11, &dscr));
 700
 701         if (dscr & ARM11_DSCR_CORE_HALTED)
 702         {
 703                 if (target->state != TARGET_HALTED)
 704                 {
 705                         enum target_state old_state = target->state;
 706
 707                         LOG_DEBUG("enter TARGET_HALTED");
 708                         target->state                   = TARGET_HALTED;
 709                         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 710                         retval = arm11_on_enter_debug_state(arm11);
 711                         if (retval != ERROR_OK)
 712                                 return retval;
 713
 714                         target_call_event_callbacks(target,
 715                                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
 716                 }
 717         }
 718         else
 719         {
 720                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 721                 {
 722                         LOG_DEBUG("enter TARGET_RUNNING");
 723                         target->state                   = TARGET_RUNNING;
 724                         target->debug_reason    = DBG_REASON_NOTHALTED;
 725                 }
 726         }
 727
 728         return ERROR_OK;
 729 }
 730 /* architecture specific status reply */
 731 static int arm11_arch_state(struct target *target)
 732 {
 733         struct arm11_common *arm11 = target_to_arm11(target);
 734
 735         LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 736                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 737                          R(CPSR),
 738                          R(PC));
 739
 740         return ERROR_OK;
 741 }
 742
 743 /* target request support */
 744 static int arm11_target_request_data(struct target *target,
 745                 uint32_t size, uint8_t *buffer)
 746 {
 747         FNC_INFO_NOTIMPLEMENTED;
 748
 749         return ERROR_OK;
 750 }
 751
 752 /* target execution control */
 753 static int arm11_halt(struct target *target)
 754 {
 755         FNC_INFO;
 756         struct arm11_common *arm11 = target_to_arm11(target);
 757
 758         LOG_DEBUG("target->state: %s",
 759                 target_state_name(target));
 760
 761         if (target->state == TARGET_UNKNOWN)
 762         {
 763                 arm11->simulate_reset_on_next_halt = true;
 764         }
 765
 766         if (target->state == TARGET_HALTED)
 767         {
 768                 LOG_DEBUG("target was already halted");
 769                 return ERROR_OK;
 770         }
 771
 772         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 773
 774         CHECK_RETVAL(jtag_execute_queue());
 775
 776         uint32_t dscr;
 777
 778         int i = 0;
 779         while (1)
 780         {
 781                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 782
 783                 if (dscr & ARM11_DSCR_CORE_HALTED)
 784                         break;
 785
 786
 787                 long long then = 0;
 788                 if (i == 1000)
 789                 {
 790                         then = timeval_ms();
 791                 }
 792                 if (i >= 1000)
 793                 {
 794                         if ((timeval_ms()-then) > 1000)
 795                         {
 796                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 797                                 return ERROR_FAIL;
 798                         }
 799                 }
 800                 i++;
 801         }
 802
 803         arm11_on_enter_debug_state(arm11);
 804
 805         enum target_state old_state     = target->state;
 806
 807         target->state           = TARGET_HALTED;
 808         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 809
 810         CHECK_RETVAL(
 811                 target_call_event_callbacks(target,
 812                         old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 813
 814         return ERROR_OK;
 815 }
 816
 817 static int arm11_resume(struct target *target, int current,
 818                 uint32_t address, int handle_breakpoints, int debug_execution)
 819 {
 820         FNC_INFO;
 821
 822         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 823         //      current, address, handle_breakpoints, debug_execution);
 824
 825         struct arm11_common *arm11 = target_to_arm11(target);
 826
 827         LOG_DEBUG("target->state: %s",
 828                 target_state_name(target));
 829
 830
 831         if (target->state != TARGET_HALTED)
 832         {
 833                 LOG_ERROR("Target not halted");
 834                 return ERROR_TARGET_NOT_HALTED;
 835         }
 836
 837         if (!current)
 838                 R(PC) = address;
 839
 840         LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 841
 842         /* clear breakpoints/watchpoints and VCR*/
 843         arm11_sc7_clear_vbw(arm11);
 844
 845         /* Set up breakpoints */
 846         if (!debug_execution)
 847         {
 848                 /* check if one matches PC and step over it if necessary */
 849
 850                 struct breakpoint *     bp;
 851
 852                 for (bp = target->breakpoints; bp; bp = bp->next)
 853                 {
 854                         if (bp->address == R(PC))
 855                         {
 856                                 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 857                                 arm11_step(target, 1, 0, 0);
 858                                 break;
 859                         }
 860                 }
 861
 862                 /* set all breakpoints */
 863
 864                 size_t          brp_num = 0;
 865
 866                 for (bp = target->breakpoints; bp; bp = bp->next)
 867                 {
 868                         struct arm11_sc7_action brp[2];
 869
 870                         brp[0].write    = 1;
 871                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 872                         brp[0].value    = bp->address;
 873                         brp[1].write    = 1;
 874                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 875                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 876
 877                         arm11_sc7_run(arm11, brp, asizeof(brp));
 878
 879                         LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
 880
 881                         brp_num++;
 882                 }
 883
 884                 arm11_sc7_set_vcr(arm11, arm11_vcr);
 885         }
 886
 887         arm11_leave_debug_state(arm11);
 888
 889         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 890
 891         CHECK_RETVAL(jtag_execute_queue());
 892
 893         int i = 0;
 894         while (1)
 895         {
 896                 uint32_t dscr;
 897
 898                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 899
 900                 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 901
 902                 if (dscr & ARM11_DSCR_CORE_RESTARTED)
 903                         break;
 904
 905
 906                 long long then = 0;
 907                 if (i == 1000)
 908                 {
 909                         then = timeval_ms();
 910                 }
 911                 if (i >= 1000)
 912                 {
 913                         if ((timeval_ms()-then) > 1000)
 914                         {
 915                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 916                                 return ERROR_FAIL;
 917                         }
 918                 }
 919                 i++;
 920         }
 921
 922         if (!debug_execution)
 923         {
 924                 target->state                   = TARGET_RUNNING;
 925                 target->debug_reason    = DBG_REASON_NOTHALTED;
 926
 927                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 928         }
 929         else
 930         {
 931                 target->state                   = TARGET_DEBUG_RUNNING;
 932                 target->debug_reason    = DBG_REASON_NOTHALTED;
 933
 934                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 935         }
 936
 937         return ERROR_OK;
 938 }
 939
 940
 941 static int armv4_5_to_arm11(int reg)
 942 {
 943         if (reg < 16)
 944                 return reg;
 945         switch (reg)
 946         {
 947         case ARMV4_5_CPSR:
 948                 return ARM11_RC_CPSR;
 949         case 16:
 950                 /* FIX!!! handle thumb better! */
 951                 return ARM11_RC_CPSR;
 952         default:
 953                 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
 954                 exit(-1);
 955         }
 956 }
 957
 958
 959 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
 960 {
 961         struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 962
 963         reg=armv4_5_to_arm11(reg);
 964
 965         return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
 966 }
 967
 968 static void arm11_sim_set_reg(struct arm_sim_interface *sim,
 969                 int reg, uint32_t value)
 970 {
 971         struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 972
 973         reg=armv4_5_to_arm11(reg);
 974
 975         buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
 976 }
 977
 978 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
 979                 int pos, int bits)
 980 {
 981         struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 982
 983         return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
 984 }
 985
 986 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
 987 {
 988 //      struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 989
 990         /* FIX!!!! we should implement thumb for arm11 */
 991         return ARMV4_5_STATE_ARM;
 992 }
 993
 994 static void arm11_sim_set_state(struct arm_sim_interface *sim,
 995                 enum armv4_5_state mode)
 996 {
 997 //      struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 998
 999         /* FIX!!!! we should implement thumb for arm11 */
1000         LOG_ERROR("Not implemetned!");
1001 }
1002
1003
1004 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
1005 {
1006         //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
1007
1008         /* FIX!!!! we should implement something that returns the current mode here!!! */
1009         return ARMV4_5_MODE_USR;
1010 }
1011
1012 static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc)
1013 {
1014         struct arm_sim_interface sim;
1015
1016         sim.user_data=target->arch_info;
1017         sim.get_reg=&arm11_sim_get_reg;
1018         sim.set_reg=&arm11_sim_set_reg;
1019         sim.get_reg_mode=&arm11_sim_get_reg;
1020         sim.set_reg_mode=&arm11_sim_set_reg;
1021         sim.get_cpsr=&arm11_sim_get_cpsr;
1022         sim.get_mode=&arm11_sim_get_mode;
1023         sim.get_state=&arm11_sim_get_state;
1024         sim.set_state=&arm11_sim_set_state;
1025
1026         return arm_simulate_step_core(target, dry_run_pc, &sim);
1027
1028 }
1029
1030 static int arm11_step(struct target *target, int current,
1031                 uint32_t address, int handle_breakpoints)
1032 {
1033         FNC_INFO;
1034
1035         LOG_DEBUG("target->state: %s",
1036                 target_state_name(target));
1037
1038         if (target->state != TARGET_HALTED)
1039         {
1040                 LOG_WARNING("target was not halted");
1041                 return ERROR_TARGET_NOT_HALTED;
1042         }
1043
1044         struct arm11_common *arm11 = target_to_arm11(target);
1045
1046         if (!current)
1047                 R(PC) = address;
1048
1049         LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1050
1051
1052         /** \todo TODO: Thumb not supported here */
1053
1054         uint32_t        next_instruction;
1055
1056         CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1057
1058         /* skip over BKPT */
1059         if ((next_instruction & 0xFFF00070) == 0xe1200070)
1060         {
1061                 R(PC) += 4;
1062                 arm11->reg_list[ARM11_RC_PC].valid = 1;
1063                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1064                 LOG_DEBUG("Skipping BKPT");
1065         }
1066         /* skip over Wait for interrupt / Standby */
1067         /* mcr  15, 0, r?, cr7, cr0, {4} */
1068         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1069         {
1070                 R(PC) += 4;
1071                 arm11->reg_list[ARM11_RC_PC].valid = 1;
1072                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1073                 LOG_DEBUG("Skipping WFI");
1074         }
1075         /* ignore B to self */
1076         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1077         {
1078                 LOG_DEBUG("Not stepping jump to self");
1079         }
1080         else
1081         {
1082                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1083                 * with this. */
1084
1085                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1086                 * the VCR might be something worth looking into. */
1087
1088
1089                 /* Set up breakpoint for stepping */
1090
1091                 struct arm11_sc7_action brp[2];
1092
1093                 brp[0].write    = 1;
1094                 brp[0].address  = ARM11_SC7_BVR0;
1095                 brp[1].write    = 1;
1096                 brp[1].address  = ARM11_SC7_BCR0;
1097
1098                 if (arm11_config_hardware_step)
1099                 {
1100                         /* hardware single stepping be used if possible or is it better to
1101                          * always use the same code path? Hardware single stepping is not supported
1102                          * on all hardware
1103                          */
1104                          brp[0].value   = R(PC);
1105                          brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1106                 } else
1107                 {
1108                         /* sets a breakpoint on the next PC(calculated by simulation),
1109                          */
1110                         uint32_t next_pc;
1111                         int retval;
1112                         retval = arm11_simulate_step(target, &next_pc);
1113                         if (retval != ERROR_OK)
1114                                 return retval;
1115
1116                         brp[0].value    = next_pc;
1117                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1118                 }
1119
1120                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1121
1122                 /* resume */
1123
1124
1125                 if (arm11_config_step_irq_enable)
1126                         R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;              /* should be redundant */
1127                 else
1128                         R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1129
1130
1131                 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1132
1133                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1134
1135                 CHECK_RETVAL(jtag_execute_queue());
1136
1137                 /* wait for halt */
1138                 int i = 0;
1139                 while (1)
1140                 {
1141                         uint32_t dscr;
1142
1143                         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1144
1145                         LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1146
1147                         if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1148                                 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1149                                 break;
1150
1151                         long long then = 0;
1152                         if (i == 1000)
1153                         {
1154                                 then = timeval_ms();
1155                         }
1156                         if (i >= 1000)
1157                         {
1158                                 if ((timeval_ms()-then) > 1000)
1159                                 {
1160                                         LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1161                                         return ERROR_FAIL;
1162                                 }
1163                         }
1164                         i++;
1165                 }
1166
1167                 /* clear breakpoint */
1168                 arm11_sc7_clear_vbw(arm11);
1169
1170                 /* save state */
1171                 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1172
1173             /* restore default state */
1174                 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1175
1176         }
1177
1178         //        target->state         = TARGET_HALTED;
1179         target->debug_reason    = DBG_REASON_SINGLESTEP;
1180
1181         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1182
1183         return ERROR_OK;
1184 }
1185
1186 static int arm11_assert_reset(struct target *target)
1187 {
1188         FNC_INFO;
1189         int retval;
1190         struct arm11_common *arm11 = target_to_arm11(target);
1191
1192         retval = arm11_check_init(arm11, NULL);
1193         if (retval != ERROR_OK)
1194                 return retval;
1195
1196         target->state = TARGET_UNKNOWN;
1197
1198         /* we would very much like to reset into the halted, state,
1199          * but resetting and halting is second best... */
1200         if (target->reset_halt)
1201         {
1202                 CHECK_RETVAL(target_halt(target));
1203         }
1204
1205
1206         /* srst is funny. We can not do *anything* else while it's asserted
1207          * and it has unkonwn side effects. Make sure no other code runs
1208          * meanwhile.
1209          *
1210          * Code below assumes srst:
1211          *
1212          * - Causes power-on-reset (but of what parts of the system?). Bug
1213          * in arm11?
1214          *
1215          * - Messes us TAP state without asserting trst.
1216          *
1217          * - There is another bug in the arm11 core. When you generate an access to
1218          * external logic (for example ddr controller via AHB bus) and that block
1219          * is not configured (perhaps it is still held in reset), that transaction
1220          * will never complete. This will hang arm11 core but it will also hang
1221          * JTAG controller. Nothing, short of srst assertion will bring it out of
1222          * this.
1223          *
1224          * Mysteries:
1225          *
1226          * - What should the PC be after an srst reset when starting in the halted
1227          * state?
1228          */
1229
1230         jtag_add_reset(0, 1);
1231         jtag_add_reset(0, 0);
1232
1233         /* How long do we have to wait? */
1234         jtag_add_sleep(5000);
1235
1236         /* un-mess up TAP state */
1237         jtag_add_tlr();
1238
1239         retval = jtag_execute_queue();
1240         if (retval != ERROR_OK)
1241         {
1242                 return retval;
1243         }
1244
1245         return ERROR_OK;
1246 }
1247
1248 static int arm11_deassert_reset(struct target *target)
1249 {
1250         return ERROR_OK;
1251 }
1252
1253 static int arm11_soft_reset_halt(struct target *target)
1254 {
1255         FNC_INFO_NOTIMPLEMENTED;
1256
1257         return ERROR_OK;
1258 }
1259
1260 /* target register access for gdb */
1261 static int arm11_get_gdb_reg_list(struct target *target,
1262                 struct reg **reg_list[], int *reg_list_size)
1263 {
1264         FNC_INFO;
1265         struct arm11_common *arm11 = target_to_arm11(target);
1266
1267         *reg_list_size  = ARM11_GDB_REGISTER_COUNT;
1268         *reg_list               = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
1269
1270         for (size_t i = 16; i < 24; i++)
1271         {
1272                 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1273         }
1274
1275         (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1276
1277         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1278         {
1279                 if (arm11_reg_defs[i].gdb_num == -1)
1280                         continue;
1281
1282                 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1283         }
1284
1285         return ERROR_OK;
1286 }
1287
1288 /* target memory access
1289  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1290  * count: number of items of <size>
1291  *
1292  * arm11_config_memrw_no_increment - in the future we may want to be able
1293  * to read/write a range of data to a "port". a "port" is an action on
1294  * read memory address for some peripheral.
1295  */
1296 static int arm11_read_memory_inner(struct target *target,
1297                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1298                 bool arm11_config_memrw_no_increment)
1299 {
1300         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1301         int retval;
1302
1303         FNC_INFO;
1304
1305         if (target->state != TARGET_HALTED)
1306         {
1307                 LOG_WARNING("target was not halted");
1308                 return ERROR_TARGET_NOT_HALTED;
1309         }
1310
1311         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1312
1313         struct arm11_common *arm11 = target_to_arm11(target);
1314
1315         retval = arm11_run_instr_data_prepare(arm11);
1316         if (retval != ERROR_OK)
1317                 return retval;
1318
1319         /* MRC p14,0,r0,c0,c5,0 */
1320         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1321         if (retval != ERROR_OK)
1322                 return retval;
1323
1324         switch (size)
1325         {
1326         case 1:
1327                 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1328                 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1329
1330                 for (size_t i = 0; i < count; i++)
1331                 {
1332                         /* ldrb    r1, [r0], #1 */
1333                         /* ldrb    r1, [r0] */
1334                         arm11_run_instr_no_data1(arm11,
1335                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1336
1337                         uint32_t res;
1338                         /* MCR p14,0,R1,c0,c5,0 */
1339                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1340
1341                         *buffer++ = res;
1342                 }
1343
1344                 break;
1345
1346         case 2:
1347                 {
1348                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1349
1350                         for (size_t i = 0; i < count; i++)
1351                         {
1352                                 /* ldrh    r1, [r0], #2 */
1353                                 arm11_run_instr_no_data1(arm11,
1354                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1355
1356                                 uint32_t res;
1357
1358                                 /* MCR p14,0,R1,c0,c5,0 */
1359                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1360
1361                                 uint16_t svalue = res;
1362                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1363                         }
1364
1365                         break;
1366                 }
1367
1368         case 4:
1369                 {
1370                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1371                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1372                 uint32_t *words = (uint32_t *)buffer;
1373
1374                 /* LDC p14,c5,[R0],#4 */
1375                 /* LDC p14,c5,[R0] */
1376                 arm11_run_instr_data_from_core(arm11, instr, words, count);
1377                 break;
1378                 }
1379         }
1380
1381         return arm11_run_instr_data_finish(arm11);
1382 }
1383
1384 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1385 {
1386         return arm11_read_memory_inner(target, address, size, count, buffer, false);
1387 }
1388
1389 /*
1390 * arm11_config_memrw_no_increment - in the future we may want to be able
1391 * to read/write a range of data to a "port". a "port" is an action on
1392 * read memory address for some peripheral.
1393 */
1394 static int arm11_write_memory_inner(struct target *target,
1395                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1396                 bool arm11_config_memrw_no_increment)
1397 {
1398         int retval;
1399         FNC_INFO;
1400
1401         if (target->state != TARGET_HALTED)
1402         {
1403                 LOG_WARNING("target was not halted");
1404                 return ERROR_TARGET_NOT_HALTED;
1405         }
1406
1407         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1408
1409         struct arm11_common *arm11 = target_to_arm11(target);
1410
1411         retval = arm11_run_instr_data_prepare(arm11);
1412         if (retval != ERROR_OK)
1413                 return retval;
1414
1415         /* MRC p14,0,r0,c0,c5,0 */
1416         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1417         if (retval != ERROR_OK)
1418                 return retval;
1419
1420         /* burst writes are not used for single words as those may well be
1421          * reset init script writes.
1422          *
1423          * The other advantage is that as burst writes are default, we'll
1424          * now exercise both burst and non-burst code paths with the
1425          * default settings, increasing code coverage.
1426          */
1427         bool burst = arm11_config_memwrite_burst && (count > 1);
1428
1429         switch (size)
1430         {
1431         case 1:
1432                 {
1433                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1434
1435                         for (size_t i = 0; i < count; i++)
1436                         {
1437                                 /* MRC p14,0,r1,c0,c5,0 */
1438                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1439                                 if (retval != ERROR_OK)
1440                                         return retval;
1441
1442                                 /* strb    r1, [r0], #1 */
1443                                 /* strb    r1, [r0] */
1444                                 retval = arm11_run_instr_no_data1(arm11,
1445                                         !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1446                                 if (retval != ERROR_OK)
1447                                         return retval;
1448                         }
1449
1450                         break;
1451                 }
1452
1453         case 2:
1454                 {
1455                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1456
1457                         for (size_t i = 0; i < count; i++)
1458                         {
1459                                 uint16_t value;
1460                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1461
1462                                 /* MRC p14,0,r1,c0,c5,0 */
1463                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1464                                 if (retval != ERROR_OK)
1465                                         return retval;
1466
1467                                 /* strh    r1, [r0], #2 */
1468                                 /* strh    r1, [r0] */
1469                                 retval = arm11_run_instr_no_data1(arm11,
1470                                         !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1471                                 if (retval != ERROR_OK)
1472                                         return retval;
1473                         }
1474
1475                         break;
1476                 }
1477
1478         case 4: {
1479                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1480
1481                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1482                 uint32_t *words = (uint32_t*)buffer;
1483
1484                 if (!burst)
1485                 {
1486                         /* STC p14,c5,[R0],#4 */
1487                         /* STC p14,c5,[R0]*/
1488                         retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1489                         if (retval != ERROR_OK)
1490                                 return retval;
1491                 }
1492                 else
1493                 {
1494                         /* STC p14,c5,[R0],#4 */
1495                         /* STC p14,c5,[R0]*/
1496                         retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1497                         if (retval != ERROR_OK)
1498                                 return retval;
1499                 }
1500
1501                 break;
1502         }
1503         }
1504
1505         /* r0 verification */
1506         if (!arm11_config_memrw_no_increment)
1507         {
1508                 uint32_t r0;
1509
1510                 /* MCR p14,0,R0,c0,c5,0 */
1511                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1512                 if (retval != ERROR_OK)
1513                         return retval;
1514
1515                 if (address + size * count != r0)
1516                 {
1517                         LOG_ERROR("Data transfer failed. Expected end "
1518                                         "address 0x%08x, got 0x%08x",
1519                                         (unsigned) (address + size * count),
1520                                         (unsigned) r0);
1521
1522                         if (burst)
1523                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1524
1525                         if (arm11_config_memwrite_error_fatal)
1526                                 return ERROR_FAIL;
1527                 }
1528         }
1529
1530         return arm11_run_instr_data_finish(arm11);
1531 }
1532
1533 static int arm11_write_memory(struct target *target,
1534                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1535 {
1536         return arm11_write_memory_inner(target, address, size, count, buffer, false);
1537 }
1538
1539 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1540 static int arm11_bulk_write_memory(struct target *target,
1541                 uint32_t address, uint32_t count, uint8_t *buffer)
1542 {
1543         FNC_INFO;
1544
1545         if (target->state != TARGET_HALTED)
1546         {
1547                 LOG_WARNING("target was not halted");
1548                 return ERROR_TARGET_NOT_HALTED;
1549         }
1550
1551         return arm11_write_memory(target, address, 4, count, buffer);
1552 }
1553
1554 /* target break-/watchpoint control
1555 * rw: 0 = write, 1 = read, 2 = access
1556 */
1557 static int arm11_add_breakpoint(struct target *target,
1558                 struct breakpoint *breakpoint)
1559 {
1560         FNC_INFO;
1561         struct arm11_common *arm11 = target_to_arm11(target);
1562
1563 #if 0
1564         if (breakpoint->type == BKPT_SOFT)
1565         {
1566                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1567                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1568         }
1569 #endif
1570
1571         if (!arm11->free_brps)
1572         {
1573                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1574                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1575         }
1576
1577         if (breakpoint->length != 4)
1578         {
1579                 LOG_DEBUG("only breakpoints of four bytes length supported");
1580                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1581         }
1582
1583         arm11->free_brps--;
1584
1585         return ERROR_OK;
1586 }
1587
1588 static int arm11_remove_breakpoint(struct target *target,
1589                 struct breakpoint *breakpoint)
1590 {
1591         FNC_INFO;
1592         struct arm11_common *arm11 = target_to_arm11(target);
1593
1594         arm11->free_brps++;
1595
1596         return ERROR_OK;
1597 }
1598
1599 static int arm11_add_watchpoint(struct target *target,
1600                 struct watchpoint *watchpoint)
1601 {
1602         FNC_INFO_NOTIMPLEMENTED;
1603
1604         return ERROR_OK;
1605 }
1606
1607 static int arm11_remove_watchpoint(struct target *target,
1608                 struct watchpoint *watchpoint)
1609 {
1610         FNC_INFO_NOTIMPLEMENTED;
1611
1612         return ERROR_OK;
1613 }
1614
1615 // HACKHACKHACK - FIXME mode/state
1616 /* target algorithm support */
1617 static int arm11_run_algorithm(struct target *target,
1618                 int num_mem_params, struct mem_param *mem_params,
1619                 int num_reg_params, struct reg_param *reg_params,
1620                 uint32_t entry_point, uint32_t exit_point,
1621                 int timeout_ms, void *arch_info)
1622 {
1623         struct arm11_common *arm11 = target_to_arm11(target);
1624 //      enum armv4_5_state core_state = arm11->core_state;
1625 //      enum armv4_5_mode core_mode = arm11->core_mode;
1626         uint32_t context[16];
1627         uint32_t cpsr;
1628         int exit_breakpoint_size = 0;
1629         int retval = ERROR_OK;
1630                 LOG_DEBUG("Running algorithm");
1631
1632
1633         if (target->state != TARGET_HALTED)
1634         {
1635                 LOG_WARNING("target not halted");
1636                 return ERROR_TARGET_NOT_HALTED;
1637         }
1638
1639         // FIXME
1640 //      if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1641 //              return ERROR_FAIL;
1642
1643         // Save regs
1644         for (unsigned i = 0; i < 16; i++)
1645         {
1646                 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1647                 LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
1648         }
1649
1650         cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1651         LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1652
1653         for (int i = 0; i < num_mem_params; i++)
1654         {
1655                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1656         }
1657
1658         // Set register parameters
1659         for (int i = 0; i < num_reg_params; i++)
1660         {
1661                 struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1662                 if (!reg)
1663                 {
1664                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1665                         exit(-1);
1666                 }
1667
1668                 if (reg->size != reg_params[i].size)
1669                 {
1670                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1671                         exit(-1);
1672                 }
1673                 arm11_set_reg(reg,reg_params[i].value);
1674 //              printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1675         }
1676
1677         exit_breakpoint_size = 4;
1678
1679 /*      arm11->core_state = arm11_algorithm_info->core_state;
1680         if (arm11->core_state == ARMV4_5_STATE_ARM)
1681                                 exit_breakpoint_size = 4;
1682         else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1683                 exit_breakpoint_size = 2;
1684         else
1685         {
1686                 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1687                 exit(-1);
1688         }
1689 */
1690
1691
1692 /* arm11 at this point only supports ARM not THUMB mode
1693    however if this test needs to be reactivated the current state can be read back
1694    from CPSR */
1695 #if 0
1696         if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1697         {
1698                 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1699                 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1700                 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1701                 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1702         }
1703 #endif
1704
1705         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1706         {
1707                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1708                 retval = ERROR_TARGET_FAILURE;
1709                 goto restore;
1710         }
1711
1712         // no debug, otherwise breakpoint is not set
1713         CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1714
1715         CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1716
1717         if (target->state != TARGET_HALTED)
1718         {
1719                 CHECK_RETVAL(target_halt(target));
1720
1721                 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1722
1723                 retval = ERROR_TARGET_TIMEOUT;
1724
1725                 goto del_breakpoint;
1726         }
1727
1728         if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1729         {
1730                 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1731                         buf_get_u32(arm11->reg_list[15].value, 0, 32));
1732                 retval = ERROR_TARGET_TIMEOUT;
1733                 goto del_breakpoint;
1734         }
1735
1736         for (int i = 0; i < num_mem_params; i++)
1737         {
1738                 if (mem_params[i].direction != PARAM_OUT)
1739                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1740         }
1741
1742         for (int i = 0; i < num_reg_params; i++)
1743         {
1744                 if (reg_params[i].direction != PARAM_OUT)
1745                 {
1746                         struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1747                         if (!reg)
1748                         {
1749                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1750                                 exit(-1);
1751                         }
1752
1753                         if (reg->size != reg_params[i].size)
1754                         {
1755                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1756                                 exit(-1);
1757                         }
1758
1759                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1760                 }
1761         }
1762
1763 del_breakpoint:
1764         breakpoint_remove(target, exit_point);
1765
1766 restore:
1767         // Restore context
1768         for (size_t i = 0; i < 16; i++)
1769         {
1770                 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1771                          arm11->reg_list[i].name, context[i]);
1772                 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1773         }
1774         LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1775         arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1776
1777 //      arm11->core_state = core_state;
1778 //      arm11->core_mode = core_mode;
1779
1780         return retval;
1781 }
1782
1783 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1784 {
1785         FNC_INFO;
1786
1787         NEW(struct arm11_common, arm11, 1);
1788
1789         arm11->target = target;
1790
1791         if (target->tap == NULL)
1792                 return ERROR_FAIL;
1793
1794         if (target->tap->ir_length != 5)
1795         {
1796                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1797                 return ERROR_COMMAND_SYNTAX_ERROR;
1798         }
1799
1800         armv4_5_init_arch_info(target, &arm11->arm);
1801
1802         arm11->jtag_info.tap = target->tap;
1803         arm11->jtag_info.scann_size = 5;
1804         arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1805         /* cur_scan_chain == 0 */
1806         arm11->jtag_info.intest_instr = ARM11_INTEST;
1807
1808         return ERROR_OK;
1809 }
1810
1811 static int arm11_init_target(struct command_context *cmd_ctx,
1812                 struct target *target)
1813 {
1814         /* Initialize anything we can set up without talking to the target */
1815         return arm11_build_reg_cache(target);
1816 }
1817
1818 /* talk to the target and set things up */
1819 static int arm11_examine(struct target *target)
1820 {
1821         int retval;
1822
1823         FNC_INFO;
1824         struct arm11_common *arm11 = target_to_arm11(target);
1825
1826         /* check IDCODE */
1827
1828         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1829
1830         struct scan_field               idcode_field;
1831
1832         arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1833
1834         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1835
1836         /* check DIDR */
1837
1838         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1839
1840         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1841
1842         struct scan_field               chain0_fields[2];
1843
1844         arm11_setup_field(arm11, 32, NULL,      &arm11->didr,           chain0_fields + 0);
1845         arm11_setup_field(arm11,  8, NULL,      &arm11->implementor,    chain0_fields + 1);
1846
1847         arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1848
1849         CHECK_RETVAL(jtag_execute_queue());
1850
1851         switch (arm11->device_id & 0x0FFFF000)
1852         {
1853         case 0x07B36000:        LOG_INFO("found ARM1136"); break;
1854         case 0x07B56000:        LOG_INFO("found ARM1156"); break;
1855         case 0x07B76000:        LOG_INFO("found ARM1176"); break;
1856         default:
1857                 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1858                 return ERROR_FAIL;
1859         }
1860
1861         arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1862
1863         if (arm11->debug_version != ARM11_DEBUG_V6 &&
1864                 arm11->debug_version != ARM11_DEBUG_V61)
1865         {
1866                 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1867                 return ERROR_FAIL;
1868         }
1869
1870         arm11->brp      = ((arm11->didr >> 24) & 0x0F) + 1;
1871         arm11->wrp      = ((arm11->didr >> 28) & 0x0F) + 1;
1872
1873         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1874         arm11->free_brps = arm11->brp;
1875         arm11->free_wrps = arm11->wrp;
1876
1877         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1878                 arm11->device_id,
1879                 (int)(arm11->implementor),
1880                 arm11->didr);
1881
1882         /* as a side-effect this reads DSCR and thus
1883          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1884          * as suggested by the spec.
1885          */
1886
1887         retval = arm11_check_init(arm11, NULL);
1888         if (retval != ERROR_OK)
1889                 return retval;
1890
1891         /* ETM on ARM11 still uses original scanchain 6 access mode */
1892         if (arm11->arm.etm && !target_was_examined(target)) {
1893                 *register_get_last_cache_p(&target->reg_cache) =
1894                         etm_build_reg_cache(target, &arm11->jtag_info,
1895                                         arm11->arm.etm);
1896                 retval = etm_setup(target);
1897         }
1898
1899         target_set_examined(target);
1900
1901         return ERROR_OK;
1902 }
1903
1904
1905 /** Load a register that is marked !valid in the register cache */
1906 static int arm11_get_reg(struct reg *reg)
1907 {
1908         FNC_INFO;
1909
1910         struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
1911
1912         if (target->state != TARGET_HALTED)
1913         {
1914                 LOG_WARNING("target was not halted");
1915                 return ERROR_TARGET_NOT_HALTED;
1916         }
1917
1918         /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1919
1920 #if 0
1921         struct arm11_common *arm11 = target_to_arm11(target);
1922         const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1923 #endif
1924
1925         return ERROR_OK;
1926 }
1927
1928 /** Change a value in the register cache */
1929 static int arm11_set_reg(struct reg *reg, uint8_t *buf)
1930 {
1931         FNC_INFO;
1932
1933         struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
1934         struct arm11_common *arm11 = target_to_arm11(target);
1935 //      const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1936
1937         arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1938         reg->valid      = 1;
1939         reg->dirty      = 1;
1940
1941         return ERROR_OK;
1942 }
1943
1944 static int arm11_build_reg_cache(struct target *target)
1945 {
1946         struct arm11_common *arm11 = target_to_arm11(target);
1947
1948         NEW(struct reg_cache,           cache,                          1);
1949         NEW(struct reg,                         reg_list,                       ARM11_REGCACHE_COUNT);
1950         NEW(struct arm11_reg_state,     arm11_reg_states,       ARM11_REGCACHE_COUNT);
1951
1952         if (arm11_regs_arch_type == -1)
1953                 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1954
1955         register_init_dummy(&arm11_gdb_dummy_fp_reg);
1956         register_init_dummy(&arm11_gdb_dummy_fps_reg);
1957
1958         arm11->reg_list = reg_list;
1959
1960         /* Build the process context cache */
1961         cache->name             = "arm11 registers";
1962         cache->next             = NULL;
1963         cache->reg_list = reg_list;
1964         cache->num_regs = ARM11_REGCACHE_COUNT;
1965
1966         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1967         (*cache_p) = cache;
1968
1969         arm11->core_cache = cache;
1970 //        armv7m->process_context = cache;
1971
1972         size_t i;
1973
1974         /* Not very elegant assertion */
1975         if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1976                 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1977                 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1978         {
1979                 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1980                 exit(-1);
1981         }
1982
1983         for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1984         {
1985                 struct reg *                                            r       = reg_list                      + i;
1986                 const struct arm11_reg_defs *   rd      = arm11_reg_defs        + i;
1987                 struct arm11_reg_state *                        rs      = arm11_reg_states      + i;
1988
1989                 r->name                         = rd->name;
1990                 r->size                         = 32;
1991                 r->value                        = (uint8_t *)(arm11->reg_values + i);
1992                 r->dirty                        = 0;
1993                 r->valid                        = 0;
1994                 r->arch_type            = arm11_regs_arch_type;
1995                 r->arch_info            = rs;
1996
1997                 rs->def_index           = i;
1998                 rs->target                      = target;
1999         }
2000
2001         return ERROR_OK;
2002 }
2003
2004 static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
2005 {
2006         if (argc == 0)
2007         {
2008                 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
2009                 return ERROR_OK;
2010         }
2011
2012         if (argc != 1)
2013                 return ERROR_COMMAND_SYNTAX_ERROR;
2014
2015         switch (args[0][0])
2016         {
2017         case '0':       /* 0 */
2018         case 'f':       /* false */
2019         case 'F':
2020         case 'd':       /* disable */
2021         case 'D':
2022                 *var = false;
2023                 break;
2024
2025         case '1':       /* 1 */
2026         case 't':       /* true */
2027         case 'T':
2028         case 'e':       /* enable */
2029         case 'E':
2030                 *var = true;
2031                 break;
2032         }
2033
2034         LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
2035
2036         return ERROR_OK;
2037 }
2038
2039 #define BOOL_WRAPPER(name, print_name)  \
2040 COMMAND_HANDLER(arm11_handle_bool_##name) \
2041 { \
2042         return CALL_COMMAND_HANDLER(arm11_handle_bool, \
2043                         &arm11_config_##name, print_name); \
2044 }
2045
2046 BOOL_WRAPPER(memwrite_burst,                    "memory write burst mode")
2047 BOOL_WRAPPER(memwrite_error_fatal,              "fatal error mode for memory writes")
2048 BOOL_WRAPPER(step_irq_enable,                   "IRQs while stepping")
2049 BOOL_WRAPPER(hardware_step,                     "hardware single step")
2050
2051 COMMAND_HANDLER(arm11_handle_vcr)
2052 {
2053         switch (argc) {
2054         case 0:
2055                 break;
2056         case 1:
2057                 COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr);
2058                 break;
2059         default:
2060                 return ERROR_COMMAND_SYNTAX_ERROR;
2061         }
2062
2063         LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2064         return ERROR_OK;
2065 }
2066
2067 static const uint32_t arm11_coproc_instruction_limits[] =
2068 {
2069         15,                             /* coprocessor */
2070         7,                              /* opcode 1 */
2071         15,                             /* CRn */
2072         15,                             /* CRm */
2073         7,                              /* opcode 2 */
2074         0xFFFFFFFF,             /* value */
2075 };
2076
2077 static int arm11_mrc_inner(struct target *target, int cpnum,
2078                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
2079                 uint32_t *value, bool read)
2080 {
2081         int retval;
2082         struct arm11_common *arm11 = target_to_arm11(target);
2083
2084         if (target->state != TARGET_HALTED)
2085         {
2086                 LOG_ERROR("Target not halted");
2087                 return ERROR_FAIL;
2088         }
2089
2090         uint32_t instr = 0xEE000010     |
2091                 (cpnum <<  8) |
2092                 (op1 << 21) |
2093                 (CRn << 16) |
2094                 (CRm <<  0) |
2095                 (op2 <<  5);
2096
2097         if (read)
2098                 instr |= 0x00100000;
2099
2100         retval = arm11_run_instr_data_prepare(arm11);
2101         if (retval != ERROR_OK)
2102                 return retval;
2103
2104         if (read)
2105         {
2106                 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value);
2107                 if (retval != ERROR_OK)
2108                         return retval;
2109         }
2110         else
2111         {
2112                 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value);
2113                 if (retval != ERROR_OK)
2114                         return retval;
2115         }
2116
2117         return arm11_run_instr_data_finish(arm11);
2118 }
2119
2120 static int arm11_mrc(struct target *target, int cpnum,
2121                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
2122 {
2123         return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
2124 }
2125
2126 static int arm11_mcr(struct target *target, int cpnum,
2127                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
2128 {
2129         return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
2130 }
2131
2132 static int arm11_register_commands(struct command_context *cmd_ctx)
2133 {
2134         FNC_INFO;
2135
2136         struct command *top_cmd, *mw_cmd;
2137
2138         top_cmd = register_command(cmd_ctx, NULL, "arm11",
2139                         NULL, COMMAND_ANY, NULL);
2140
2141         /* "hardware_step" is only here to check if the default
2142          * simulate + breakpoint implementation is broken.
2143          * TEMPORARY! NOT DOCUMENTED!
2144          */
2145         register_command(cmd_ctx, top_cmd, "hardware_step",
2146                         arm11_handle_bool_hardware_step, COMMAND_ANY,
2147                         "DEBUG ONLY - Hardware single stepping"
2148                                 " (default: disabled)");
2149
2150         mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2151                         NULL, COMMAND_ANY, NULL);
2152         register_command(cmd_ctx, mw_cmd, "burst",
2153                         arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2154                         "Enable/Disable non-standard but fast burst mode"
2155                                 " (default: enabled)");
2156         register_command(cmd_ctx, mw_cmd, "error_fatal",
2157                         arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2158                         "Terminate program if transfer error was found"
2159                                 " (default: enabled)");
2160
2161         register_command(cmd_ctx, top_cmd, "step_irq_enable",
2162                         arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2163                         "Enable interrupts while stepping"
2164                                 " (default: disabled)");
2165         register_command(cmd_ctx, top_cmd, "vcr",
2166                         arm11_handle_vcr, COMMAND_ANY,
2167                         "Control (Interrupt) Vector Catch Register");
2168
2169         return etm_register_commands(cmd_ctx);
2170 }
2171
2172 /** Holds methods for ARM11xx targets. */
2173 struct target_type arm11_target = {
2174         .name =                 "arm11",
2175
2176         .poll =                 arm11_poll,
2177         .arch_state =           arm11_arch_state,
2178
2179         .target_request_data =  arm11_target_request_data,
2180
2181         .halt =                 arm11_halt,
2182         .resume =               arm11_resume,
2183         .step =                 arm11_step,
2184
2185         .assert_reset =         arm11_assert_reset,
2186         .deassert_reset =       arm11_deassert_reset,
2187         .soft_reset_halt =      arm11_soft_reset_halt,
2188
2189         .get_gdb_reg_list =     arm11_get_gdb_reg_list,
2190
2191         .read_memory =          arm11_read_memory,
2192         .write_memory =         arm11_write_memory,
2193
2194         .bulk_write_memory =    arm11_bulk_write_memory,
2195
2196         .checksum_memory =      arm_checksum_memory,
2197         .blank_check_memory =   arm_blank_check_memory,
2198
2199         .add_breakpoint =       arm11_add_breakpoint,
2200         .remove_breakpoint =    arm11_remove_breakpoint,
2201         .add_watchpoint =       arm11_add_watchpoint,
2202         .remove_watchpoint =    arm11_remove_watchpoint,
2203
2204         .run_algorithm =        arm11_run_algorithm,
2205
2206         .register_commands =    arm11_register_commands,
2207         .target_create =        arm11_target_create,
2208         .init_target =          arm11_init_target,
2209         .examine =              arm11_examine,
2210
2211         .mrc =                  arm11_mrc,
2212         .mcr =                  arm11_mcr,
2213 };