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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "arm11.h"
  30 #include "arm11_dbgtap.h"
  31 #include "armv4_5.h"
  32 #include "arm_simulator.h"
  33 #include "time_support.h"
  34 #include "target_type.h"
  35
  36
  37 #if 0
  38 #define _DEBUG_INSTRUCTION_EXECUTION_
  39 #endif
  40
  41 #if 0
  42 #define FNC_INFO        LOG_DEBUG("-")
  43 #else
  44 #define FNC_INFO
  45 #endif
  46
  47 #if 1
  48 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
  49 #else
  50 #define FNC_INFO_NOTIMPLEMENTED
  51 #endif
  52
  53 static bool arm11_config_memwrite_burst = true;
  54 static bool arm11_config_memwrite_error_fatal = true;
  55 static uint32_t arm11_vcr = 0;
  56 static bool arm11_config_step_irq_enable = false;
  57 static bool arm11_config_hardware_step = false;
  58
  59 static int arm11_regs_arch_type = -1;
  60
  61 enum arm11_regtype
  62 {
  63         ARM11_REGISTER_CORE,
  64         ARM11_REGISTER_CPSR,
  65
  66         ARM11_REGISTER_FX,
  67         ARM11_REGISTER_FPS,
  68
  69         ARM11_REGISTER_FIQ,
  70         ARM11_REGISTER_SVC,
  71         ARM11_REGISTER_ABT,
  72         ARM11_REGISTER_IRQ,
  73         ARM11_REGISTER_UND,
  74         ARM11_REGISTER_MON,
  75
  76         ARM11_REGISTER_SPSR_FIQ,
  77         ARM11_REGISTER_SPSR_SVC,
  78         ARM11_REGISTER_SPSR_ABT,
  79         ARM11_REGISTER_SPSR_IRQ,
  80         ARM11_REGISTER_SPSR_UND,
  81         ARM11_REGISTER_SPSR_MON,
  82
  83         /* debug regs */
  84         ARM11_REGISTER_DSCR,
  85         ARM11_REGISTER_WDTR,
  86         ARM11_REGISTER_RDTR,
  87 };
  88
  89
  90 typedef struct arm11_reg_defs_s
  91 {
  92         char *                                  name;
  93         uint32_t                                                num;
  94         int                                             gdb_num;
  95         enum arm11_regtype              type;
  96 } arm11_reg_defs_t;
  97
  98 /* update arm11_regcache_ids when changing this */
  99 static const arm11_reg_defs_t arm11_reg_defs[] =
 100 {
 101         {"r0",  0,      0,      ARM11_REGISTER_CORE},
 102         {"r1",  1,      1,      ARM11_REGISTER_CORE},
 103         {"r2",  2,      2,      ARM11_REGISTER_CORE},
 104         {"r3",  3,      3,      ARM11_REGISTER_CORE},
 105         {"r4",  4,      4,      ARM11_REGISTER_CORE},
 106         {"r5",  5,      5,      ARM11_REGISTER_CORE},
 107         {"r6",  6,      6,      ARM11_REGISTER_CORE},
 108         {"r7",  7,      7,      ARM11_REGISTER_CORE},
 109         {"r8",  8,      8,      ARM11_REGISTER_CORE},
 110         {"r9",  9,      9,      ARM11_REGISTER_CORE},
 111         {"r10", 10,     10,     ARM11_REGISTER_CORE},
 112         {"r11", 11,     11,     ARM11_REGISTER_CORE},
 113         {"r12", 12,     12,     ARM11_REGISTER_CORE},
 114         {"sp",  13,     13,     ARM11_REGISTER_CORE},
 115         {"lr",  14,     14,     ARM11_REGISTER_CORE},
 116         {"pc",  15,     15,     ARM11_REGISTER_CORE},
 117
 118 #if ARM11_REGCACHE_FREGS
 119         {"f0",  0,      16,     ARM11_REGISTER_FX},
 120         {"f1",  1,      17,     ARM11_REGISTER_FX},
 121         {"f2",  2,      18,     ARM11_REGISTER_FX},
 122         {"f3",  3,      19,     ARM11_REGISTER_FX},
 123         {"f4",  4,      20,     ARM11_REGISTER_FX},
 124         {"f5",  5,      21,     ARM11_REGISTER_FX},
 125         {"f6",  6,      22,     ARM11_REGISTER_FX},
 126         {"f7",  7,      23,     ARM11_REGISTER_FX},
 127         {"fps", 0,      24,     ARM11_REGISTER_FPS},
 128 #endif
 129
 130         {"cpsr",        0,      25,     ARM11_REGISTER_CPSR},
 131
 132 #if ARM11_REGCACHE_MODEREGS
 133         {"r8_fiq",      8,      -1,     ARM11_REGISTER_FIQ},
 134         {"r9_fiq",      9,      -1,     ARM11_REGISTER_FIQ},
 135         {"r10_fiq",     10,     -1,     ARM11_REGISTER_FIQ},
 136         {"r11_fiq",     11,     -1,     ARM11_REGISTER_FIQ},
 137         {"r12_fiq",     12,     -1,     ARM11_REGISTER_FIQ},
 138         {"r13_fiq",     13,     -1,     ARM11_REGISTER_FIQ},
 139         {"r14_fiq",     14,     -1,     ARM11_REGISTER_FIQ},
 140         {"spsr_fiq", 0, -1,     ARM11_REGISTER_SPSR_FIQ},
 141
 142         {"r13_svc",     13,     -1,     ARM11_REGISTER_SVC},
 143         {"r14_svc",     14,     -1,     ARM11_REGISTER_SVC},
 144         {"spsr_svc", 0, -1,     ARM11_REGISTER_SPSR_SVC},
 145
 146         {"r13_abt",     13,     -1,     ARM11_REGISTER_ABT},
 147         {"r14_abt",     14,     -1,     ARM11_REGISTER_ABT},
 148         {"spsr_abt", 0, -1,     ARM11_REGISTER_SPSR_ABT},
 149
 150         {"r13_irq",     13,     -1,     ARM11_REGISTER_IRQ},
 151         {"r14_irq",     14,     -1,     ARM11_REGISTER_IRQ},
 152         {"spsr_irq", 0, -1,     ARM11_REGISTER_SPSR_IRQ},
 153
 154         {"r13_und",     13,     -1,     ARM11_REGISTER_UND},
 155         {"r14_und",     14,     -1,     ARM11_REGISTER_UND},
 156         {"spsr_und", 0, -1,     ARM11_REGISTER_SPSR_UND},
 157
 158         /* ARM1176 only */
 159         {"r13_mon",     13,     -1,     ARM11_REGISTER_MON},
 160         {"r14_mon",     14,     -1,     ARM11_REGISTER_MON},
 161         {"spsr_mon", 0, -1,     ARM11_REGISTER_SPSR_MON},
 162 #endif
 163
 164         /* Debug Registers */
 165         {"dscr",        0,      -1,     ARM11_REGISTER_DSCR},
 166         {"wdtr",        0,      -1,     ARM11_REGISTER_WDTR},
 167         {"rdtr",        0,      -1,     ARM11_REGISTER_RDTR},
 168 };
 169
 170 enum arm11_regcache_ids
 171 {
 172         ARM11_RC_R0,
 173         ARM11_RC_RX                     = ARM11_RC_R0,
 174
 175         ARM11_RC_R1,
 176         ARM11_RC_R2,
 177         ARM11_RC_R3,
 178         ARM11_RC_R4,
 179         ARM11_RC_R5,
 180         ARM11_RC_R6,
 181         ARM11_RC_R7,
 182         ARM11_RC_R8,
 183         ARM11_RC_R9,
 184         ARM11_RC_R10,
 185         ARM11_RC_R11,
 186         ARM11_RC_R12,
 187         ARM11_RC_R13,
 188         ARM11_RC_SP                     = ARM11_RC_R13,
 189         ARM11_RC_R14,
 190         ARM11_RC_LR                     = ARM11_RC_R14,
 191         ARM11_RC_R15,
 192         ARM11_RC_PC                     = ARM11_RC_R15,
 193
 194 #if ARM11_REGCACHE_FREGS
 195         ARM11_RC_F0,
 196         ARM11_RC_FX                     = ARM11_RC_F0,
 197         ARM11_RC_F1,
 198         ARM11_RC_F2,
 199         ARM11_RC_F3,
 200         ARM11_RC_F4,
 201         ARM11_RC_F5,
 202         ARM11_RC_F6,
 203         ARM11_RC_F7,
 204         ARM11_RC_FPS,
 205 #endif
 206
 207         ARM11_RC_CPSR,
 208
 209 #if ARM11_REGCACHE_MODEREGS
 210         ARM11_RC_R8_FIQ,
 211         ARM11_RC_R9_FIQ,
 212         ARM11_RC_R10_FIQ,
 213         ARM11_RC_R11_FIQ,
 214         ARM11_RC_R12_FIQ,
 215         ARM11_RC_R13_FIQ,
 216         ARM11_RC_R14_FIQ,
 217         ARM11_RC_SPSR_FIQ,
 218
 219         ARM11_RC_R13_SVC,
 220         ARM11_RC_R14_SVC,
 221         ARM11_RC_SPSR_SVC,
 222
 223         ARM11_RC_R13_ABT,
 224         ARM11_RC_R14_ABT,
 225         ARM11_RC_SPSR_ABT,
 226
 227         ARM11_RC_R13_IRQ,
 228         ARM11_RC_R14_IRQ,
 229         ARM11_RC_SPSR_IRQ,
 230
 231         ARM11_RC_R13_UND,
 232         ARM11_RC_R14_UND,
 233         ARM11_RC_SPSR_UND,
 234
 235         ARM11_RC_R13_MON,
 236         ARM11_RC_R14_MON,
 237         ARM11_RC_SPSR_MON,
 238 #endif
 239
 240         ARM11_RC_DSCR,
 241         ARM11_RC_WDTR,
 242         ARM11_RC_RDTR,
 243
 244         ARM11_RC_MAX,
 245 };
 246
 247 #define ARM11_GDB_REGISTER_COUNT        26
 248
 249 static uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 250
 251 static reg_t arm11_gdb_dummy_fp_reg =
 252 {
 253         "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 254 };
 255
 256 static uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 257
 258 static reg_t arm11_gdb_dummy_fps_reg =
 259 {
 260         "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 261 };
 262
 263
 264 static int arm11_on_enter_debug_state(arm11_common_t *arm11);
 265 static int arm11_step(struct target_s *target, int current,
 266                 uint32_t address, int handle_breakpoints);
 267 /* helpers */
 268 static int arm11_build_reg_cache(target_t *target);
 269 static int arm11_set_reg(reg_t *reg, uint8_t *buf);
 270 static int arm11_get_reg(reg_t *reg);
 271
 272 static void arm11_record_register_history(arm11_common_t * arm11);
 273 static void arm11_dump_reg_changes(arm11_common_t * arm11);
 274
 275
 276 /** Check and if necessary take control of the system
 277  *
 278  * \param arm11         Target state variable.
 279  * \param dscr          If the current DSCR content is
 280  *                                      available a pointer to a word holding the
 281  *                                      DSCR can be passed. Otherwise use NULL.
 282  */
 283 static int arm11_check_init(arm11_common_t *arm11, uint32_t *dscr)
 284 {
 285         FNC_INFO;
 286
 287         uint32_t                        dscr_local_tmp_copy;
 288
 289         if (!dscr)
 290         {
 291                 dscr = &dscr_local_tmp_copy;
 292
 293                 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
 294         }
 295
 296         if (!(*dscr & ARM11_DSCR_MODE_SELECT))
 297         {
 298                 LOG_DEBUG("Bringing target into debug mode");
 299
 300                 *dscr |= ARM11_DSCR_MODE_SELECT;                /* Halt debug-mode */
 301                 arm11_write_DSCR(arm11, *dscr);
 302
 303                 /* add further reset initialization here */
 304
 305                 arm11->simulate_reset_on_next_halt = true;
 306
 307                 if (*dscr & ARM11_DSCR_CORE_HALTED)
 308                 {
 309                         /** \todo TODO: this needs further scrutiny because
 310                           * arm11_on_enter_debug_state() never gets properly called.
 311                           * As a result we don't read the actual register states from
 312                           * the target.
 313                           */
 314
 315                         arm11->target->state    = TARGET_HALTED;
 316                         arm11->target->debug_reason     = arm11_get_DSCR_debug_reason(*dscr);
 317                 }
 318                 else
 319                 {
 320                         arm11->target->state    = TARGET_RUNNING;
 321                         arm11->target->debug_reason     = DBG_REASON_NOTHALTED;
 322                 }
 323
 324                 arm11_sc7_clear_vbw(arm11);
 325         }
 326
 327         return ERROR_OK;
 328 }
 329
 330
 331
 332 #define R(x) \
 333         (arm11->reg_values[ARM11_RC_##x])
 334
 335 /** Save processor state.
 336   *
 337   * This is called when the HALT instruction has succeeded
 338   * or on other occasions that stop the processor.
 339   *
 340   */
 341 static int arm11_on_enter_debug_state(arm11_common_t *arm11)
 342 {
 343         int retval;
 344         FNC_INFO;
 345
 346         for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
 347         {
 348                 arm11->reg_list[i].valid        = 1;
 349                 arm11->reg_list[i].dirty        = 0;
 350         }
 351
 352         /* Save DSCR */
 353         CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
 354
 355         /* Save wDTR */
 356
 357         if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
 358         {
 359                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 360
 361                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 362
 363                 scan_field_t    chain5_fields[3];
 364
 365                 arm11_setup_field(arm11, 32, NULL, &R(WDTR),    chain5_fields + 0);
 366                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
 367                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
 368
 369                 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 370         }
 371         else
 372         {
 373                 arm11->reg_list[ARM11_RC_WDTR].valid    = 0;
 374         }
 375
 376
 377         /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
 378         /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
 379            ARM1136 seems to require this to issue ITR's as well */
 380
 381         uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
 382
 383         /* this executes JTAG queue: */
 384
 385         arm11_write_DSCR(arm11, new_dscr);
 386
 387
 388         /* From the spec:
 389            Before executing any instruction in debug state you have to drain the write buffer.
 390            This ensures that no imprecise Data Aborts can return at a later point:*/
 391
 392         /** \todo TODO: Test drain write buffer. */
 393
 394 #if 0
 395         while (1)
 396         {
 397                 /* MRC p14,0,R0,c5,c10,0 */
 398                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 399
 400                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 401                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 402
 403                 uint32_t dscr = arm11_read_DSCR(arm11);
 404
 405                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 406
 407                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 408                 {
 409                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 410
 411                         dscr = arm11_read_DSCR(arm11);
 412
 413                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 414
 415                         break;
 416                 }
 417         }
 418 #endif
 419
 420         retval = arm11_run_instr_data_prepare(arm11);
 421         if (retval != ERROR_OK)
 422                 return retval;
 423
 424         /* save r0 - r14 */
 425
 426         /** \todo TODO: handle other mode registers */
 427
 428         for (size_t i = 0; i < 15; i++)
 429         {
 430                 /* MCR p14,0,R?,c0,c5,0 */
 431                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
 432                 if (retval != ERROR_OK)
 433                         return retval;
 434         }
 435
 436         /* save rDTR */
 437
 438         /* check rDTRfull in DSCR */
 439
 440         if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
 441         {
 442                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 443                 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
 444                 if (retval != ERROR_OK)
 445                         return retval;
 446         }
 447         else
 448         {
 449                 arm11->reg_list[ARM11_RC_RDTR].valid    = 0;
 450         }
 451
 452         /* save CPSR */
 453
 454         /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
 455         retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
 456         if (retval != ERROR_OK)
 457                 return retval;
 458
 459         /* save PC */
 460
 461         /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
 462         retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
 463         if (retval != ERROR_OK)
 464                 return retval;
 465
 466         /* adjust PC depending on ARM state */
 467
 468         if (R(CPSR) & ARM11_CPSR_J)     /* Java state */
 469         {
 470                 arm11->reg_values[ARM11_RC_PC] -= 0;
 471         }
 472         else if (R(CPSR) & ARM11_CPSR_T)        /* Thumb state */
 473         {
 474                 arm11->reg_values[ARM11_RC_PC] -= 4;
 475         }
 476         else                                    /* ARM state */
 477         {
 478                 arm11->reg_values[ARM11_RC_PC] -= 8;
 479         }
 480
 481         if (arm11->simulate_reset_on_next_halt)
 482         {
 483                 arm11->simulate_reset_on_next_halt = false;
 484
 485                 LOG_DEBUG("Reset c1 Control Register");
 486
 487                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 488
 489                 /* MCR p15,0,R0,c1,c0,0 */
 490                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 491                 if (retval != ERROR_OK)
 492                         return retval;
 493
 494         }
 495
 496         retval = arm11_run_instr_data_finish(arm11);
 497         if (retval != ERROR_OK)
 498                 return retval;
 499
 500         arm11_dump_reg_changes(arm11);
 501
 502         return ERROR_OK;
 503 }
 504
 505 void arm11_dump_reg_changes(arm11_common_t * arm11)
 506 {
 507
 508         if (!(debug_level >= LOG_LVL_DEBUG))
 509         {
 510                 return;
 511         }
 512
 513         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 514         {
 515                 if (!arm11->reg_list[i].valid)
 516                 {
 517                         if (arm11->reg_history[i].valid)
 518                                 LOG_DEBUG("%8s INVALID   (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
 519                 }
 520                 else
 521                 {
 522                         if (arm11->reg_history[i].valid)
 523                         {
 524                                 if (arm11->reg_history[i].value != arm11->reg_values[i])
 525                                         LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
 526                         }
 527                         else
 528                         {
 529                                 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
 530                         }
 531                 }
 532         }
 533 }
 534
 535 /** Restore processor state
 536   *
 537   * This is called in preparation for the RESTART function.
 538   *
 539   */
 540 static int arm11_leave_debug_state(arm11_common_t *arm11)
 541 {
 542         FNC_INFO;
 543         int retval;
 544
 545         retval = arm11_run_instr_data_prepare(arm11);
 546         if (retval != ERROR_OK)
 547                 return retval;
 548
 549         /** \todo TODO: handle other mode registers */
 550
 551         /* restore R1 - R14 */
 552
 553         for (size_t i = 1; i < 15; i++)
 554         {
 555                 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
 556                         continue;
 557
 558                 /* MRC p14,0,r?,c0,c5,0 */
 559                 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
 560
 561                 //      LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
 562         }
 563
 564         retval = arm11_run_instr_data_finish(arm11);
 565         if (retval != ERROR_OK)
 566                 return retval;
 567
 568         /* spec says clear wDTR and rDTR; we assume they are clear as
 569            otherwise our programming would be sloppy */
 570         {
 571                 uint32_t DSCR;
 572
 573                 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
 574
 575                 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 576                 {
 577                         /*
 578                         The wDTR/rDTR two registers that are used to send/receive data to/from
 579                         the core in tandem with corresponding instruction codes that are
 580                         written into the core. The RDTR FULL/WDTR FULL flag indicates that the
 581                         registers hold data that was written by one side (CPU or JTAG) and not
 582                         read out by the other side.
 583                         */
 584                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 585                         return ERROR_FAIL;
 586                 }
 587         }
 588
 589         retval = arm11_run_instr_data_prepare(arm11);
 590         if (retval != ERROR_OK)
 591                 return retval;
 592
 593         /* restore original wDTR */
 594
 595         if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
 596         {
 597                 /* MCR p14,0,R0,c0,c5,0 */
 598                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
 599                 if (retval != ERROR_OK)
 600                         return retval;
 601         }
 602
 603         /* restore CPSR */
 604
 605         /* MSR CPSR,R0*/
 606         retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
 607         if (retval != ERROR_OK)
 608                 return retval;
 609
 610
 611         /* restore PC */
 612
 613         /* MOV PC,R0 */
 614         retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
 615         if (retval != ERROR_OK)
 616                 return retval;
 617
 618
 619         /* restore R0 */
 620
 621         /* MRC p14,0,r0,c0,c5,0 */
 622         arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
 623
 624         retval = arm11_run_instr_data_finish(arm11);
 625         if (retval != ERROR_OK)
 626                 return retval;
 627
 628         /* restore DSCR */
 629
 630         arm11_write_DSCR(arm11, R(DSCR));
 631
 632         /* restore rDTR */
 633
 634         if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
 635         {
 636                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 637
 638                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 639
 640                 scan_field_t    chain5_fields[3];
 641
 642                 uint8_t                 Ready           = 0;    /* ignored */
 643                 uint8_t                 Valid           = 0;    /* ignored */
 644
 645                 arm11_setup_field(arm11, 32, &R(RDTR),  NULL, chain5_fields + 0);
 646                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 647                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 648
 649                 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 650         }
 651
 652         arm11_record_register_history(arm11);
 653
 654         return ERROR_OK;
 655 }
 656
 657 static void arm11_record_register_history(arm11_common_t *arm11)
 658 {
 659         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 660         {
 661                 arm11->reg_history[i].value     = arm11->reg_values[i];
 662                 arm11->reg_history[i].valid     = arm11->reg_list[i].valid;
 663
 664                 arm11->reg_list[i].valid        = 0;
 665                 arm11->reg_list[i].dirty        = 0;
 666         }
 667 }
 668
 669
 670 /* poll current target status */
 671 static int arm11_poll(struct target_s *target)
 672 {
 673         FNC_INFO;
 674         int retval;
 675
 676         arm11_common_t * arm11 = target->arch_info;
 677
 678         uint32_t        dscr;
 679
 680         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 681
 682         LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 683
 684         CHECK_RETVAL(arm11_check_init(arm11, &dscr));
 685
 686         if (dscr & ARM11_DSCR_CORE_HALTED)
 687         {
 688                 if (target->state != TARGET_HALTED)
 689                 {
 690                         enum target_state old_state = target->state;
 691
 692                         LOG_DEBUG("enter TARGET_HALTED");
 693                         target->state                   = TARGET_HALTED;
 694                         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 695                         retval = arm11_on_enter_debug_state(arm11);
 696                         if (retval != ERROR_OK)
 697                                 return retval;
 698
 699                         target_call_event_callbacks(target,
 700                                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
 701                 }
 702         }
 703         else
 704         {
 705                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 706                 {
 707                         LOG_DEBUG("enter TARGET_RUNNING");
 708                         target->state                   = TARGET_RUNNING;
 709                         target->debug_reason    = DBG_REASON_NOTHALTED;
 710                 }
 711         }
 712
 713         return ERROR_OK;
 714 }
 715 /* architecture specific status reply */
 716 static int arm11_arch_state(struct target_s *target)
 717 {
 718         arm11_common_t * arm11 = target->arch_info;
 719
 720         LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 721                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 722                          R(CPSR),
 723                          R(PC));
 724
 725         return ERROR_OK;
 726 }
 727
 728 /* target request support */
 729 static int arm11_target_request_data(struct target_s *target,
 730                 uint32_t size, uint8_t *buffer)
 731 {
 732         FNC_INFO_NOTIMPLEMENTED;
 733
 734         return ERROR_OK;
 735 }
 736
 737 /* target execution control */
 738 static int arm11_halt(struct target_s *target)
 739 {
 740         FNC_INFO;
 741
 742         arm11_common_t * arm11 = target->arch_info;
 743
 744         LOG_DEBUG("target->state: %s",
 745                 target_state_name(target));
 746
 747         if (target->state == TARGET_UNKNOWN)
 748         {
 749                 arm11->simulate_reset_on_next_halt = true;
 750         }
 751
 752         if (target->state == TARGET_HALTED)
 753         {
 754                 LOG_DEBUG("target was already halted");
 755                 return ERROR_OK;
 756         }
 757
 758         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 759
 760         CHECK_RETVAL(jtag_execute_queue());
 761
 762         uint32_t dscr;
 763
 764         int i = 0;
 765         while (1)
 766         {
 767                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 768
 769                 if (dscr & ARM11_DSCR_CORE_HALTED)
 770                         break;
 771
 772
 773                 long long then = 0;
 774                 if (i == 1000)
 775                 {
 776                         then = timeval_ms();
 777                 }
 778                 if (i >= 1000)
 779                 {
 780                         if ((timeval_ms()-then) > 1000)
 781                         {
 782                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 783                                 return ERROR_FAIL;
 784                         }
 785                 }
 786                 i++;
 787         }
 788
 789         arm11_on_enter_debug_state(arm11);
 790
 791         enum target_state old_state     = target->state;
 792
 793         target->state           = TARGET_HALTED;
 794         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 795
 796         CHECK_RETVAL(
 797                 target_call_event_callbacks(target,
 798                         old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 799
 800         return ERROR_OK;
 801 }
 802
 803 static int arm11_resume(struct target_s *target, int current,
 804                 uint32_t address, int handle_breakpoints, int debug_execution)
 805 {
 806         FNC_INFO;
 807
 808         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 809         //      current, address, handle_breakpoints, debug_execution);
 810
 811         arm11_common_t * arm11 = target->arch_info;
 812
 813         LOG_DEBUG("target->state: %s",
 814                 target_state_name(target));
 815
 816
 817         if (target->state != TARGET_HALTED)
 818         {
 819                 LOG_ERROR("Target not halted");
 820                 return ERROR_TARGET_NOT_HALTED;
 821         }
 822
 823         if (!current)
 824                 R(PC) = address;
 825
 826         LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 827
 828         /* clear breakpoints/watchpoints and VCR*/
 829         arm11_sc7_clear_vbw(arm11);
 830
 831         /* Set up breakpoints */
 832         if (!debug_execution)
 833         {
 834                 /* check if one matches PC and step over it if necessary */
 835
 836                 breakpoint_t *  bp;
 837
 838                 for (bp = target->breakpoints; bp; bp = bp->next)
 839                 {
 840                         if (bp->address == R(PC))
 841                         {
 842                                 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 843                                 arm11_step(target, 1, 0, 0);
 844                                 break;
 845                         }
 846                 }
 847
 848                 /* set all breakpoints */
 849
 850                 size_t          brp_num = 0;
 851
 852                 for (bp = target->breakpoints; bp; bp = bp->next)
 853                 {
 854                         arm11_sc7_action_t      brp[2];
 855
 856                         brp[0].write    = 1;
 857                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 858                         brp[0].value    = bp->address;
 859                         brp[1].write    = 1;
 860                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 861                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 862
 863                         arm11_sc7_run(arm11, brp, asizeof(brp));
 864
 865                         LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
 866
 867                         brp_num++;
 868                 }
 869
 870                 arm11_sc7_set_vcr(arm11, arm11_vcr);
 871         }
 872
 873         arm11_leave_debug_state(arm11);
 874
 875         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 876
 877         CHECK_RETVAL(jtag_execute_queue());
 878
 879         int i = 0;
 880         while (1)
 881         {
 882                 uint32_t dscr;
 883
 884                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 885
 886                 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 887
 888                 if (dscr & ARM11_DSCR_CORE_RESTARTED)
 889                         break;
 890
 891
 892                 long long then = 0;
 893                 if (i == 1000)
 894                 {
 895                         then = timeval_ms();
 896                 }
 897                 if (i >= 1000)
 898                 {
 899                         if ((timeval_ms()-then) > 1000)
 900                         {
 901                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 902                                 return ERROR_FAIL;
 903                         }
 904                 }
 905                 i++;
 906         }
 907
 908         if (!debug_execution)
 909         {
 910                 target->state                   = TARGET_RUNNING;
 911                 target->debug_reason    = DBG_REASON_NOTHALTED;
 912
 913                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 914         }
 915         else
 916         {
 917                 target->state                   = TARGET_DEBUG_RUNNING;
 918                 target->debug_reason    = DBG_REASON_NOTHALTED;
 919
 920                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 921         }
 922
 923         return ERROR_OK;
 924 }
 925
 926
 927 static int armv4_5_to_arm11(int reg)
 928 {
 929         if (reg < 16)
 930                 return reg;
 931         switch (reg)
 932         {
 933         case ARMV4_5_CPSR:
 934                 return ARM11_RC_CPSR;
 935         case 16:
 936                 /* FIX!!! handle thumb better! */
 937                 return ARM11_RC_CPSR;
 938         default:
 939                 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
 940                 exit(-1);
 941         }
 942 }
 943
 944
 945 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
 946 {
 947         arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 948
 949         reg=armv4_5_to_arm11(reg);
 950
 951         return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
 952 }
 953
 954 static void arm11_sim_set_reg(struct arm_sim_interface *sim,
 955                 int reg, uint32_t value)
 956 {
 957         arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 958
 959         reg=armv4_5_to_arm11(reg);
 960
 961         buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
 962 }
 963
 964 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
 965                 int pos, int bits)
 966 {
 967         arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 968
 969         return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
 970 }
 971
 972 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
 973 {
 974 //      arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 975
 976         /* FIX!!!! we should implement thumb for arm11 */
 977         return ARMV4_5_STATE_ARM;
 978 }
 979
 980 static void arm11_sim_set_state(struct arm_sim_interface *sim,
 981                 enum armv4_5_state mode)
 982 {
 983 //      arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 984
 985         /* FIX!!!! we should implement thumb for arm11 */
 986         LOG_ERROR("Not implemetned!");
 987 }
 988
 989
 990 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
 991 {
 992         //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 993
 994         /* FIX!!!! we should implement something that returns the current mode here!!! */
 995         return ARMV4_5_MODE_USR;
 996 }
 997
 998 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
 999 {
1000         struct arm_sim_interface sim;
1001
1002         sim.user_data=target->arch_info;
1003         sim.get_reg=&arm11_sim_get_reg;
1004         sim.set_reg=&arm11_sim_set_reg;
1005         sim.get_reg_mode=&arm11_sim_get_reg;
1006         sim.set_reg_mode=&arm11_sim_set_reg;
1007         sim.get_cpsr=&arm11_sim_get_cpsr;
1008         sim.get_mode=&arm11_sim_get_mode;
1009         sim.get_state=&arm11_sim_get_state;
1010         sim.set_state=&arm11_sim_set_state;
1011
1012         return arm_simulate_step_core(target, dry_run_pc, &sim);
1013
1014 }
1015
1016 static int arm11_step(struct target_s *target, int current,
1017                 uint32_t address, int handle_breakpoints)
1018 {
1019         FNC_INFO;
1020
1021         LOG_DEBUG("target->state: %s",
1022                 target_state_name(target));
1023
1024         if (target->state != TARGET_HALTED)
1025         {
1026                 LOG_WARNING("target was not halted");
1027                 return ERROR_TARGET_NOT_HALTED;
1028         }
1029
1030         arm11_common_t * arm11 = target->arch_info;
1031
1032         if (!current)
1033                 R(PC) = address;
1034
1035         LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1036
1037
1038         /** \todo TODO: Thumb not supported here */
1039
1040         uint32_t        next_instruction;
1041
1042         CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1043
1044         /* skip over BKPT */
1045         if ((next_instruction & 0xFFF00070) == 0xe1200070)
1046         {
1047                 R(PC) += 4;
1048                 arm11->reg_list[ARM11_RC_PC].valid = 1;
1049                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1050                 LOG_DEBUG("Skipping BKPT");
1051         }
1052         /* skip over Wait for interrupt / Standby */
1053         /* mcr  15, 0, r?, cr7, cr0, {4} */
1054         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1055         {
1056                 R(PC) += 4;
1057                 arm11->reg_list[ARM11_RC_PC].valid = 1;
1058                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1059                 LOG_DEBUG("Skipping WFI");
1060         }
1061         /* ignore B to self */
1062         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1063         {
1064                 LOG_DEBUG("Not stepping jump to self");
1065         }
1066         else
1067         {
1068                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1069                 * with this. */
1070
1071                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1072                 * the VCR might be something worth looking into. */
1073
1074
1075                 /* Set up breakpoint for stepping */
1076
1077                 arm11_sc7_action_t      brp[2];
1078
1079                 brp[0].write    = 1;
1080                 brp[0].address  = ARM11_SC7_BVR0;
1081                 brp[1].write    = 1;
1082                 brp[1].address  = ARM11_SC7_BCR0;
1083
1084                 if (arm11_config_hardware_step)
1085                 {
1086                         /* hardware single stepping be used if possible or is it better to
1087                          * always use the same code path? Hardware single stepping is not supported
1088                          * on all hardware
1089                          */
1090                          brp[0].value   = R(PC);
1091                          brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1092                 } else
1093                 {
1094                         /* sets a breakpoint on the next PC(calculated by simulation),
1095                          */
1096                         uint32_t next_pc;
1097                         int retval;
1098                         retval = arm11_simulate_step(target, &next_pc);
1099                         if (retval != ERROR_OK)
1100                                 return retval;
1101
1102                         brp[0].value    = next_pc;
1103                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1104                 }
1105
1106                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1107
1108                 /* resume */
1109
1110
1111                 if (arm11_config_step_irq_enable)
1112                         R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;              /* should be redundant */
1113                 else
1114                         R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1115
1116
1117                 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1118
1119                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1120
1121                 CHECK_RETVAL(jtag_execute_queue());
1122
1123                 /* wait for halt */
1124                 int i = 0;
1125                 while (1)
1126                 {
1127                         uint32_t dscr;
1128
1129                         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1130
1131                         LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1132
1133                         if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1134                                 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1135                                 break;
1136
1137                         long long then = 0;
1138                         if (i == 1000)
1139                         {
1140                                 then = timeval_ms();
1141                         }
1142                         if (i >= 1000)
1143                         {
1144                                 if ((timeval_ms()-then) > 1000)
1145                                 {
1146                                         LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1147                                         return ERROR_FAIL;
1148                                 }
1149                         }
1150                         i++;
1151                 }
1152
1153                 /* clear breakpoint */
1154                 arm11_sc7_clear_vbw(arm11);
1155
1156                 /* save state */
1157                 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1158
1159             /* restore default state */
1160                 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1161
1162         }
1163
1164         //        target->state         = TARGET_HALTED;
1165         target->debug_reason    = DBG_REASON_SINGLESTEP;
1166
1167         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1168
1169         return ERROR_OK;
1170 }
1171
1172 static int arm11_assert_reset(target_t *target)
1173 {
1174         FNC_INFO;
1175         int retval;
1176
1177         arm11_common_t * arm11 = target->arch_info;
1178         retval = arm11_check_init(arm11, NULL);
1179         if (retval != ERROR_OK)
1180                 return retval;
1181
1182         target->state = TARGET_UNKNOWN;
1183
1184         /* we would very much like to reset into the halted, state,
1185          * but resetting and halting is second best... */
1186         if (target->reset_halt)
1187         {
1188                 CHECK_RETVAL(target_halt(target));
1189         }
1190
1191
1192         /* srst is funny. We can not do *anything* else while it's asserted
1193          * and it has unkonwn side effects. Make sure no other code runs
1194          * meanwhile.
1195          *
1196          * Code below assumes srst:
1197          *
1198          * - Causes power-on-reset (but of what parts of the system?). Bug
1199          * in arm11?
1200          *
1201          * - Messes us TAP state without asserting trst.
1202          *
1203          * - There is another bug in the arm11 core. When you generate an access to
1204          * external logic (for example ddr controller via AHB bus) and that block
1205          * is not configured (perhaps it is still held in reset), that transaction
1206          * will never complete. This will hang arm11 core but it will also hang
1207          * JTAG controller. Nothing, short of srst assertion will bring it out of
1208          * this.
1209          *
1210          * Mysteries:
1211          *
1212          * - What should the PC be after an srst reset when starting in the halted
1213          * state?
1214          */
1215
1216         jtag_add_reset(0, 1);
1217         jtag_add_reset(0, 0);
1218
1219         /* How long do we have to wait? */
1220         jtag_add_sleep(5000);
1221
1222         /* un-mess up TAP state */
1223         jtag_add_tlr();
1224
1225         retval = jtag_execute_queue();
1226         if (retval != ERROR_OK)
1227         {
1228                 return retval;
1229         }
1230
1231         return ERROR_OK;
1232 }
1233
1234 static int arm11_deassert_reset(target_t *target)
1235 {
1236         return ERROR_OK;
1237 }
1238
1239 static int arm11_soft_reset_halt(struct target_s *target)
1240 {
1241         FNC_INFO_NOTIMPLEMENTED;
1242
1243         return ERROR_OK;
1244 }
1245
1246 /* target register access for gdb */
1247 static int arm11_get_gdb_reg_list(struct target_s *target,
1248                 struct reg_s **reg_list[], int *reg_list_size)
1249 {
1250         FNC_INFO;
1251
1252         arm11_common_t * arm11 = target->arch_info;
1253
1254         *reg_list_size  = ARM11_GDB_REGISTER_COUNT;
1255         *reg_list               = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1256
1257         for (size_t i = 16; i < 24; i++)
1258         {
1259                 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1260         }
1261
1262         (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1263
1264         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1265         {
1266                 if (arm11_reg_defs[i].gdb_num == -1)
1267                         continue;
1268
1269                 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1270         }
1271
1272         return ERROR_OK;
1273 }
1274
1275 /* target memory access
1276  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1277  * count: number of items of <size>
1278  *
1279  * arm11_config_memrw_no_increment - in the future we may want to be able
1280  * to read/write a range of data to a "port". a "port" is an action on
1281  * read memory address for some peripheral.
1282  */
1283 static int arm11_read_memory_inner(struct target_s *target,
1284                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1285                 bool arm11_config_memrw_no_increment)
1286 {
1287         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1288         int retval;
1289
1290         FNC_INFO;
1291
1292         if (target->state != TARGET_HALTED)
1293         {
1294                 LOG_WARNING("target was not halted");
1295                 return ERROR_TARGET_NOT_HALTED;
1296         }
1297
1298         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1299
1300         arm11_common_t * arm11 = target->arch_info;
1301
1302         retval = arm11_run_instr_data_prepare(arm11);
1303         if (retval != ERROR_OK)
1304                 return retval;
1305
1306         /* MRC p14,0,r0,c0,c5,0 */
1307         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1308         if (retval != ERROR_OK)
1309                 return retval;
1310
1311         switch (size)
1312         {
1313         case 1:
1314                 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1315                 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1316
1317                 for (size_t i = 0; i < count; i++)
1318                 {
1319                         /* ldrb    r1, [r0], #1 */
1320                         /* ldrb    r1, [r0] */
1321                         arm11_run_instr_no_data1(arm11,
1322                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1323
1324                         uint32_t res;
1325                         /* MCR p14,0,R1,c0,c5,0 */
1326                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1327
1328                         *buffer++ = res;
1329                 }
1330
1331                 break;
1332
1333         case 2:
1334                 {
1335                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1336
1337                         for (size_t i = 0; i < count; i++)
1338                         {
1339                                 /* ldrh    r1, [r0], #2 */
1340                                 arm11_run_instr_no_data1(arm11,
1341                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1342
1343                                 uint32_t res;
1344
1345                                 /* MCR p14,0,R1,c0,c5,0 */
1346                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1347
1348                                 uint16_t svalue = res;
1349                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1350                         }
1351
1352                         break;
1353                 }
1354
1355         case 4:
1356                 {
1357                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1358                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1359                 uint32_t *words = (uint32_t *)buffer;
1360
1361                 /* LDC p14,c5,[R0],#4 */
1362                 /* LDC p14,c5,[R0] */
1363                 arm11_run_instr_data_from_core(arm11, instr, words, count);
1364                 break;
1365                 }
1366         }
1367
1368         return arm11_run_instr_data_finish(arm11);
1369 }
1370
1371 static int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1372 {
1373         return arm11_read_memory_inner(target, address, size, count, buffer, false);
1374 }
1375
1376 /*
1377 * arm11_config_memrw_no_increment - in the future we may want to be able
1378 * to read/write a range of data to a "port". a "port" is an action on
1379 * read memory address for some peripheral.
1380 */
1381 static int arm11_write_memory_inner(struct target_s *target,
1382                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1383                 bool arm11_config_memrw_no_increment)
1384 {
1385         int retval;
1386         FNC_INFO;
1387
1388         if (target->state != TARGET_HALTED)
1389         {
1390                 LOG_WARNING("target was not halted");
1391                 return ERROR_TARGET_NOT_HALTED;
1392         }
1393
1394         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1395
1396         arm11_common_t * arm11 = target->arch_info;
1397
1398         retval = arm11_run_instr_data_prepare(arm11);
1399         if (retval != ERROR_OK)
1400                 return retval;
1401
1402         /* MRC p14,0,r0,c0,c5,0 */
1403         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1404         if (retval != ERROR_OK)
1405                 return retval;
1406
1407         /* burst writes are not used for single words as those may well be
1408          * reset init script writes.
1409          *
1410          * The other advantage is that as burst writes are default, we'll
1411          * now exercise both burst and non-burst code paths with the
1412          * default settings, increasing code coverage.
1413          */
1414         bool burst = arm11_config_memwrite_burst && (count > 1);
1415
1416         switch (size)
1417         {
1418         case 1:
1419                 {
1420                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1421
1422                         for (size_t i = 0; i < count; i++)
1423                         {
1424                                 /* MRC p14,0,r1,c0,c5,0 */
1425                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1426                                 if (retval != ERROR_OK)
1427                                         return retval;
1428
1429                                 /* strb    r1, [r0], #1 */
1430                                 /* strb    r1, [r0] */
1431                                 retval = arm11_run_instr_no_data1(arm11,
1432                                         !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1433                                 if (retval != ERROR_OK)
1434                                         return retval;
1435                         }
1436
1437                         break;
1438                 }
1439
1440         case 2:
1441                 {
1442                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1443
1444                         for (size_t i = 0; i < count; i++)
1445                         {
1446                                 uint16_t value;
1447                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1448
1449                                 /* MRC p14,0,r1,c0,c5,0 */
1450                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1451                                 if (retval != ERROR_OK)
1452                                         return retval;
1453
1454                                 /* strh    r1, [r0], #2 */
1455                                 /* strh    r1, [r0] */
1456                                 retval = arm11_run_instr_no_data1(arm11,
1457                                         !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1458                                 if (retval != ERROR_OK)
1459                                         return retval;
1460                         }
1461
1462                         break;
1463                 }
1464
1465         case 4: {
1466                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1467
1468                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1469                 uint32_t *words = (uint32_t*)buffer;
1470
1471                 if (!burst)
1472                 {
1473                         /* STC p14,c5,[R0],#4 */
1474                         /* STC p14,c5,[R0]*/
1475                         retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1476                         if (retval != ERROR_OK)
1477                                 return retval;
1478                 }
1479                 else
1480                 {
1481                         /* STC p14,c5,[R0],#4 */
1482                         /* STC p14,c5,[R0]*/
1483                         retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1484                         if (retval != ERROR_OK)
1485                                 return retval;
1486                 }
1487
1488                 break;
1489         }
1490         }
1491
1492         /* r0 verification */
1493         if (!arm11_config_memrw_no_increment)
1494         {
1495                 uint32_t r0;
1496
1497                 /* MCR p14,0,R0,c0,c5,0 */
1498                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1499                 if (retval != ERROR_OK)
1500                         return retval;
1501
1502                 if (address + size * count != r0)
1503                 {
1504                         LOG_ERROR("Data transfer failed. Expected end "
1505                                         "address 0x%08x, got 0x%08x",
1506                                         (unsigned) (address + size * count),
1507                                         (unsigned) r0);
1508
1509                         if (burst)
1510                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1511
1512                         if (arm11_config_memwrite_error_fatal)
1513                                 return ERROR_FAIL;
1514                 }
1515         }
1516
1517         return arm11_run_instr_data_finish(arm11);
1518 }
1519
1520 static int arm11_write_memory(struct target_s *target,
1521                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1522 {
1523         return arm11_write_memory_inner(target, address, size, count, buffer, false);
1524 }
1525
1526 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1527 static int arm11_bulk_write_memory(struct target_s *target,
1528                 uint32_t address, uint32_t count, uint8_t *buffer)
1529 {
1530         FNC_INFO;
1531
1532         if (target->state != TARGET_HALTED)
1533         {
1534                 LOG_WARNING("target was not halted");
1535                 return ERROR_TARGET_NOT_HALTED;
1536         }
1537
1538         return arm11_write_memory(target, address, 4, count, buffer);
1539 }
1540
1541 /* here we have nothing target specific to contribute, so we fail and then the
1542  * fallback code will read data from the target and calculate the CRC on the
1543  * host.
1544  */
1545 static int arm11_checksum_memory(struct target_s *target,
1546                 uint32_t address, uint32_t count, uint32_t* checksum)
1547 {
1548         return ERROR_FAIL;
1549 }
1550
1551 /* target break-/watchpoint control
1552 * rw: 0 = write, 1 = read, 2 = access
1553 */
1554 static int arm11_add_breakpoint(struct target_s *target,
1555                 breakpoint_t *breakpoint)
1556 {
1557         FNC_INFO;
1558
1559         arm11_common_t * arm11 = target->arch_info;
1560
1561 #if 0
1562         if (breakpoint->type == BKPT_SOFT)
1563         {
1564                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1565                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1566         }
1567 #endif
1568
1569         if (!arm11->free_brps)
1570         {
1571                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1572                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1573         }
1574
1575         if (breakpoint->length != 4)
1576         {
1577                 LOG_DEBUG("only breakpoints of four bytes length supported");
1578                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1579         }
1580
1581         arm11->free_brps--;
1582
1583         return ERROR_OK;
1584 }
1585
1586 static int arm11_remove_breakpoint(struct target_s *target,
1587                 breakpoint_t *breakpoint)
1588 {
1589         FNC_INFO;
1590
1591         arm11_common_t * arm11 = target->arch_info;
1592
1593         arm11->free_brps++;
1594
1595         return ERROR_OK;
1596 }
1597
1598 static int arm11_add_watchpoint(struct target_s *target,
1599                 watchpoint_t *watchpoint)
1600 {
1601         FNC_INFO_NOTIMPLEMENTED;
1602
1603         return ERROR_OK;
1604 }
1605
1606 static int arm11_remove_watchpoint(struct target_s *target,
1607                 watchpoint_t *watchpoint)
1608 {
1609         FNC_INFO_NOTIMPLEMENTED;
1610
1611         return ERROR_OK;
1612 }
1613
1614 // HACKHACKHACK - FIXME mode/state
1615 /* target algorithm support */
1616 static int arm11_run_algorithm(struct target_s *target,
1617                 int num_mem_params, mem_param_t *mem_params,
1618                 int num_reg_params, reg_param_t *reg_params,
1619                 uint32_t entry_point, uint32_t exit_point,
1620                 int timeout_ms, void *arch_info)
1621 {
1622                 arm11_common_t *arm11 = target->arch_info;
1623 //      enum armv4_5_state core_state = arm11->core_state;
1624 //      enum armv4_5_mode core_mode = arm11->core_mode;
1625         uint32_t context[16];
1626         uint32_t cpsr;
1627         int exit_breakpoint_size = 0;
1628         int retval = ERROR_OK;
1629                 LOG_DEBUG("Running algorithm");
1630
1631
1632         if (target->state != TARGET_HALTED)
1633         {
1634                 LOG_WARNING("target not halted");
1635                 return ERROR_TARGET_NOT_HALTED;
1636         }
1637
1638         // FIXME
1639 //      if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1640 //              return ERROR_FAIL;
1641
1642         // Save regs
1643         for (unsigned i = 0; i < 16; i++)
1644         {
1645                 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1646                 LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
1647         }
1648
1649         cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1650         LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1651
1652         for (int i = 0; i < num_mem_params; i++)
1653         {
1654                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1655         }
1656
1657         // Set register parameters
1658         for (int i = 0; i < num_reg_params; i++)
1659         {
1660                 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1661                 if (!reg)
1662                 {
1663                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1664                         exit(-1);
1665                 }
1666
1667                 if (reg->size != reg_params[i].size)
1668                 {
1669                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1670                         exit(-1);
1671                 }
1672                 arm11_set_reg(reg,reg_params[i].value);
1673 //              printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1674         }
1675
1676         exit_breakpoint_size = 4;
1677
1678 /*      arm11->core_state = arm11_algorithm_info->core_state;
1679         if (arm11->core_state == ARMV4_5_STATE_ARM)
1680                                 exit_breakpoint_size = 4;
1681         else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1682                 exit_breakpoint_size = 2;
1683         else
1684         {
1685                 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1686                 exit(-1);
1687         }
1688 */
1689
1690
1691 /* arm11 at this point only supports ARM not THUMB mode
1692    however if this test needs to be reactivated the current state can be read back
1693    from CPSR */
1694 #if 0
1695         if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1696         {
1697                 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1698                 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1699                 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1700                 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1701         }
1702 #endif
1703
1704         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1705         {
1706                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1707                 retval = ERROR_TARGET_FAILURE;
1708                 goto restore;
1709         }
1710
1711         // no debug, otherwise breakpoint is not set
1712         CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1713
1714         CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1715
1716         if (target->state != TARGET_HALTED)
1717         {
1718                 CHECK_RETVAL(target_halt(target));
1719
1720                 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1721
1722                 retval = ERROR_TARGET_TIMEOUT;
1723
1724                 goto del_breakpoint;
1725         }
1726
1727         if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1728         {
1729                 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1730                         buf_get_u32(arm11->reg_list[15].value, 0, 32));
1731                 retval = ERROR_TARGET_TIMEOUT;
1732                 goto del_breakpoint;
1733         }
1734
1735         for (int i = 0; i < num_mem_params; i++)
1736         {
1737                 if (mem_params[i].direction != PARAM_OUT)
1738                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1739         }
1740
1741         for (int i = 0; i < num_reg_params; i++)
1742         {
1743                 if (reg_params[i].direction != PARAM_OUT)
1744                 {
1745                         reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1746                         if (!reg)
1747                         {
1748                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1749                                 exit(-1);
1750                         }
1751
1752                         if (reg->size != reg_params[i].size)
1753                         {
1754                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1755                                 exit(-1);
1756                         }
1757
1758                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1759                 }
1760         }
1761
1762 del_breakpoint:
1763         breakpoint_remove(target, exit_point);
1764
1765 restore:
1766         // Restore context
1767         for (size_t i = 0; i < 16; i++)
1768         {
1769                 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1770                          arm11->reg_list[i].name, context[i]);
1771                 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1772         }
1773         LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1774         arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1775
1776 //      arm11->core_state = core_state;
1777 //      arm11->core_mode = core_mode;
1778
1779         return retval;
1780 }
1781
1782 static int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1783 {
1784         FNC_INFO;
1785
1786         NEW(arm11_common_t, arm11, 1);
1787
1788         arm11->target = target;
1789
1790         if (target->tap == NULL)
1791                 return ERROR_FAIL;
1792
1793         if (target->tap->ir_length != 5)
1794         {
1795                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1796                 return ERROR_COMMAND_SYNTAX_ERROR;
1797         }
1798
1799         target->arch_info = arm11;
1800
1801         return ERROR_OK;
1802 }
1803
1804 static int arm11_init_target(struct command_context_s *cmd_ctx,
1805                 struct target_s *target)
1806 {
1807         /* Initialize anything we can set up without talking to the target */
1808         return arm11_build_reg_cache(target);
1809 }
1810
1811 /* talk to the target and set things up */
1812 static int arm11_examine(struct target_s *target)
1813 {
1814         int retval;
1815
1816         FNC_INFO;
1817
1818         arm11_common_t * arm11 = target->arch_info;
1819
1820         /* check IDCODE */
1821
1822         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1823
1824         scan_field_t            idcode_field;
1825
1826         arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1827
1828         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1829
1830         /* check DIDR */
1831
1832         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1833
1834         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1835
1836         scan_field_t            chain0_fields[2];
1837
1838         arm11_setup_field(arm11, 32, NULL,      &arm11->didr,           chain0_fields + 0);
1839         arm11_setup_field(arm11,  8, NULL,      &arm11->implementor,    chain0_fields + 1);
1840
1841         arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1842
1843         CHECK_RETVAL(jtag_execute_queue());
1844
1845         switch (arm11->device_id & 0x0FFFF000)
1846         {
1847         case 0x07B36000:        LOG_INFO("found ARM1136"); break;
1848         case 0x07B56000:        LOG_INFO("found ARM1156"); break;
1849         case 0x07B76000:        LOG_INFO("found ARM1176"); break;
1850         default:
1851         {
1852                 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1853                 return ERROR_FAIL;
1854         }
1855         }
1856
1857         arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1858
1859         if (arm11->debug_version != ARM11_DEBUG_V6 &&
1860                 arm11->debug_version != ARM11_DEBUG_V61)
1861         {
1862                 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1863                 return ERROR_FAIL;
1864         }
1865
1866         arm11->brp      = ((arm11->didr >> 24) & 0x0F) + 1;
1867         arm11->wrp      = ((arm11->didr >> 28) & 0x0F) + 1;
1868
1869         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1870         arm11->free_brps = arm11->brp;
1871         arm11->free_wrps = arm11->wrp;
1872
1873         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1874                 arm11->device_id,
1875                 (int)(arm11->implementor),
1876                 arm11->didr);
1877
1878         /* as a side-effect this reads DSCR and thus
1879          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1880          * as suggested by the spec.
1881          */
1882
1883         retval = arm11_check_init(arm11, NULL);
1884         if (retval != ERROR_OK)
1885                 return retval;
1886
1887         target_set_examined(target);
1888
1889         return ERROR_OK;
1890 }
1891
1892
1893 /** Load a register that is marked !valid in the register cache */
1894 static int arm11_get_reg(reg_t *reg)
1895 {
1896         FNC_INFO;
1897
1898         target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1899
1900         if (target->state != TARGET_HALTED)
1901         {
1902                 LOG_WARNING("target was not halted");
1903                 return ERROR_TARGET_NOT_HALTED;
1904         }
1905
1906         /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1907
1908 #if 0
1909         arm11_common_t *arm11 = target->arch_info;
1910         const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1911 #endif
1912
1913         return ERROR_OK;
1914 }
1915
1916 /** Change a value in the register cache */
1917 static int arm11_set_reg(reg_t *reg, uint8_t *buf)
1918 {
1919         FNC_INFO;
1920
1921         target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1922         arm11_common_t *arm11 = target->arch_info;
1923 //        const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1924
1925         arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1926         reg->valid      = 1;
1927         reg->dirty      = 1;
1928
1929         return ERROR_OK;
1930 }
1931
1932 static int arm11_build_reg_cache(target_t *target)
1933 {
1934         arm11_common_t *arm11 = target->arch_info;
1935
1936         NEW(reg_cache_t,                cache,                          1);
1937         NEW(reg_t,                              reg_list,                       ARM11_REGCACHE_COUNT);
1938         NEW(arm11_reg_state_t,  arm11_reg_states,       ARM11_REGCACHE_COUNT);
1939
1940         if (arm11_regs_arch_type == -1)
1941                 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1942
1943         register_init_dummy(&arm11_gdb_dummy_fp_reg);
1944         register_init_dummy(&arm11_gdb_dummy_fps_reg);
1945
1946         arm11->reg_list = reg_list;
1947
1948         /* Build the process context cache */
1949         cache->name             = "arm11 registers";
1950         cache->next             = NULL;
1951         cache->reg_list = reg_list;
1952         cache->num_regs = ARM11_REGCACHE_COUNT;
1953
1954         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1955         (*cache_p) = cache;
1956
1957         arm11->core_cache = cache;
1958 //        armv7m->process_context = cache;
1959
1960         size_t i;
1961
1962         /* Not very elegant assertion */
1963         if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1964                 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1965                 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1966         {
1967                 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1968                 exit(-1);
1969         }
1970
1971         for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1972         {
1973                 reg_t *                                         r       = reg_list                      + i;
1974                 const arm11_reg_defs_t *        rd      = arm11_reg_defs        + i;
1975                 arm11_reg_state_t *                     rs      = arm11_reg_states      + i;
1976
1977                 r->name                         = rd->name;
1978                 r->size                         = 32;
1979                 r->value                        = (uint8_t *)(arm11->reg_values + i);
1980                 r->dirty                        = 0;
1981                 r->valid                        = 0;
1982                 r->bitfield_desc        = NULL;
1983                 r->num_bitfields        = 0;
1984                 r->arch_type            = arm11_regs_arch_type;
1985                 r->arch_info            = rs;
1986
1987                 rs->def_index           = i;
1988                 rs->target                      = target;
1989         }
1990
1991         return ERROR_OK;
1992 }
1993
1994 static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
1995 {
1996         if (argc == 0)
1997         {
1998                 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1999                 return ERROR_OK;
2000         }
2001
2002         if (argc != 1)
2003                 return ERROR_COMMAND_SYNTAX_ERROR;
2004
2005         switch (args[0][0])
2006         {
2007         case '0':       /* 0 */
2008         case 'f':       /* false */
2009         case 'F':
2010         case 'd':       /* disable */
2011         case 'D':
2012                 *var = false;
2013                 break;
2014
2015         case '1':       /* 1 */
2016         case 't':       /* true */
2017         case 'T':
2018         case 'e':       /* enable */
2019         case 'E':
2020                 *var = true;
2021                 break;
2022         }
2023
2024         LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
2025
2026         return ERROR_OK;
2027 }
2028
2029 #define BOOL_WRAPPER(name, print_name)  \
2030 COMMAND_HANDLER(arm11_handle_bool_##name) \
2031 { \
2032         return CALL_COMMAND_HANDLER(arm11_handle_bool, \
2033                         &arm11_config_##name, print_name); \
2034 }
2035
2036 BOOL_WRAPPER(memwrite_burst,                    "memory write burst mode")
2037 BOOL_WRAPPER(memwrite_error_fatal,              "fatal error mode for memory writes")
2038 BOOL_WRAPPER(step_irq_enable,                   "IRQs while stepping")
2039 BOOL_WRAPPER(hardware_step,                     "hardware single step")
2040
2041 COMMAND_HANDLER(arm11_handle_vcr)
2042 {
2043         switch (argc) {
2044         case 0:
2045                 break;
2046         case 1:
2047                 COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr);
2048                 break;
2049         default:
2050                 return ERROR_COMMAND_SYNTAX_ERROR;
2051         }
2052
2053         LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2054         return ERROR_OK;
2055 }
2056
2057 static const uint32_t arm11_coproc_instruction_limits[] =
2058 {
2059         15,                             /* coprocessor */
2060         7,                              /* opcode 1 */
2061         15,                             /* CRn */
2062         15,                             /* CRm */
2063         7,                              /* opcode 2 */
2064         0xFFFFFFFF,             /* value */
2065 };
2066
2067 static arm11_common_t * arm11_find_target(const char * arg)
2068 {
2069         struct jtag_tap *       tap;
2070         target_t *              t;
2071
2072         tap = jtag_tap_by_string(arg);
2073
2074         if (!tap)
2075                 return 0;
2076
2077         for (t = all_targets; t; t = t->next)
2078         {
2079                 if (t->tap != tap)
2080                         continue;
2081
2082                 /* if (t->type == arm11_target) */
2083                 if (0 == strcmp(target_get_name(t), "arm11"))
2084                         return t->arch_info;
2085         }
2086
2087         return 0;
2088 }
2089
2090 static int arm11_mrc_inner(target_t *target, int cpnum,
2091                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
2092                 uint32_t *value, bool read)
2093 {
2094         int retval;
2095
2096         if (target->state != TARGET_HALTED)
2097         {
2098                 LOG_ERROR("Target not halted");
2099                 return ERROR_FAIL;
2100         }
2101
2102         arm11_common_t * arm11 = target->arch_info;
2103
2104         uint32_t instr = 0xEE000010     |
2105                 (cpnum <<  8) |
2106                 (op1 << 21) |
2107                 (CRn << 16) |
2108                 (CRm <<  0) |
2109                 (op2 <<  5);
2110
2111         if (read)
2112                 instr |= 0x00100000;
2113
2114         retval = arm11_run_instr_data_prepare(arm11);
2115         if (retval != ERROR_OK)
2116                 return retval;
2117
2118         if (read)
2119         {
2120                 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value);
2121                 if (retval != ERROR_OK)
2122                         return retval;
2123         }
2124         else
2125         {
2126                 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value);
2127                 if (retval != ERROR_OK)
2128                         return retval;
2129         }
2130
2131         return arm11_run_instr_data_finish(arm11);
2132 }
2133
2134 static int arm11_mrc(target_t *target, int cpnum,
2135                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
2136 {
2137         return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
2138 }
2139
2140 static int arm11_mcr(target_t *target, int cpnum,
2141                 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
2142 {
2143         return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
2144 }
2145
2146 static COMMAND_HELPER(arm11_handle_etm_read_write, bool read)
2147 {
2148         if (argc != (read ? 2 : 3))
2149         {
2150                 LOG_ERROR("Invalid number of arguments.");
2151                 return ERROR_COMMAND_SYNTAX_ERROR;
2152         }
2153
2154         arm11_common_t * arm11 = arm11_find_target(args[0]);
2155
2156         if (!arm11)
2157         {
2158                 LOG_ERROR("Parameter 1 is not the target name of an ARM11 device.");
2159                 return ERROR_COMMAND_SYNTAX_ERROR;
2160         }
2161
2162         uint32_t address;
2163         COMMAND_PARSE_NUMBER(u32, args[1], address);
2164
2165         if (!read)
2166         {
2167                 uint32_t value;
2168                 COMMAND_PARSE_NUMBER(u32, args[2], value);
2169
2170                 LOG_INFO("ETM write register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
2171                   address, address, value, value);
2172
2173                 CHECK_RETVAL(arm11_write_etm(arm11, address, value));
2174         }
2175         else
2176         {
2177                 uint32_t value;
2178
2179                 CHECK_RETVAL(arm11_read_etm(arm11, address, &value));
2180
2181             LOG_INFO("ETM read register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
2182                   address, address, value, value);
2183         }
2184
2185         return ERROR_OK;
2186 }
2187
2188 COMMAND_HANDLER(arm11_handle_etmr)
2189 {
2190         return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, true);
2191 }
2192
2193 COMMAND_HANDLER(arm11_handle_etmw)
2194 {
2195         return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, false);
2196 }
2197
2198 #define ARM11_HANDLER(x)        .x = arm11_##x
2199
2200 target_type_t arm11_target = {
2201                 .name = "arm11",
2202
2203                 ARM11_HANDLER(poll),
2204                 ARM11_HANDLER(arch_state),
2205
2206                 ARM11_HANDLER(target_request_data),
2207
2208                 ARM11_HANDLER(halt),
2209                 ARM11_HANDLER(resume),
2210                 ARM11_HANDLER(step),
2211
2212                 ARM11_HANDLER(assert_reset),
2213                 ARM11_HANDLER(deassert_reset),
2214                 ARM11_HANDLER(soft_reset_halt),
2215
2216                 ARM11_HANDLER(get_gdb_reg_list),
2217
2218                 ARM11_HANDLER(read_memory),
2219                 ARM11_HANDLER(write_memory),
2220
2221                 ARM11_HANDLER(bulk_write_memory),
2222
2223                 ARM11_HANDLER(checksum_memory),
2224
2225                 ARM11_HANDLER(add_breakpoint),
2226                 ARM11_HANDLER(remove_breakpoint),
2227                 ARM11_HANDLER(add_watchpoint),
2228                 ARM11_HANDLER(remove_watchpoint),
2229
2230                 ARM11_HANDLER(run_algorithm),
2231
2232                 ARM11_HANDLER(register_commands),
2233                 ARM11_HANDLER(target_create),
2234                 ARM11_HANDLER(init_target),
2235                 ARM11_HANDLER(examine),
2236
2237                 ARM11_HANDLER(mrc),
2238                 ARM11_HANDLER(mcr),
2239         };
2240
2241
2242 int arm11_register_commands(struct command_context_s *cmd_ctx)
2243 {
2244         FNC_INFO;
2245
2246         command_t *top_cmd, *mw_cmd;
2247
2248         top_cmd = register_command(cmd_ctx, NULL, "arm11",
2249                         NULL, COMMAND_ANY, NULL);
2250
2251         register_command(cmd_ctx, top_cmd, "etmr",
2252                         arm11_handle_etmr, COMMAND_ANY,
2253                         "Read Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address>");
2254
2255         register_command(cmd_ctx, top_cmd, "etmw",
2256                         arm11_handle_etmw, COMMAND_ANY,
2257                         "Write Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address> <value>");
2258
2259         /* "hardware_step" is only here to check if the default
2260          * simulate + breakpoint implementation is broken.
2261          * TEMPORARY! NOT DOCUMENTED!
2262          */
2263         register_command(cmd_ctx, top_cmd, "hardware_step",
2264                         arm11_handle_bool_hardware_step, COMMAND_ANY,
2265                         "DEBUG ONLY - Hardware single stepping"
2266                                 " (default: disabled)");
2267
2268         mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2269                         NULL, COMMAND_ANY, NULL);
2270         register_command(cmd_ctx, mw_cmd, "burst",
2271                         arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2272                         "Enable/Disable non-standard but fast burst mode"
2273                                 " (default: enabled)");
2274         register_command(cmd_ctx, mw_cmd, "error_fatal",
2275                         arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2276                         "Terminate program if transfer error was found"
2277                                 " (default: enabled)");
2278
2279         register_command(cmd_ctx, top_cmd, "step_irq_enable",
2280                         arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2281                         "Enable interrupts while stepping"
2282                                 " (default: disabled)");
2283         register_command(cmd_ctx, top_cmd, "vcr",
2284                         arm11_handle_vcr, COMMAND_ANY,
2285                         "Control (Interrupt) Vector Catch Register");
2286
2287         return ERROR_OK;
2288 }