2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Øyvind Harboe
9 * oyvind.harboe@zylin.com
11 * Copyright (C) 2018 by Liviu Ionescu
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program. If not, see <http://www.gnu.org/licenses/>.
28 #ifndef OPENOCD_TARGET_ARM_H
29 #define OPENOCD_TARGET_ARM_H
31 #include <helper/command.h>
36 * Holds the interface to ARM cores.
38 * At this writing, only "classic ARM" cores built on the ARMv4 register
39 * and mode model are supported. The Thumb2-only microcontroller profile
40 * support has not yet been integrated, affecting Cortex-M parts.
44 * Indicates what registers are in the ARM state core register set.
46 * - ARM_CORE_TYPE_STD indicates the standard set of 37 registers, seen
47 * on for example ARM7TDMI cores.
48 * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
49 * three more registers are shadowed for "Secure Monitor" mode.
50 * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
51 * which only shadows SP.
54 ARM_CORE_TYPE_STD = -1,
55 ARM_CORE_TYPE_SEC_EXT = 1,
56 ARM_CORE_TYPE_M_PROFILE,
60 * Represent state of an ARM core.
62 * Most numbers match the five low bits of the *PSR registers on
63 * "classic ARM" processors, which build on the ARMv4 processor
64 * modes and register set.
66 * ARM_MODE_ANY is a magic value, often used as a wildcard.
68 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
69 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
80 ARM_MODE_1176_MON = 28,
84 ARM_MODE_USER_THREAD = 1,
98 /* VFPv3 internal register numbers mapping to d0:31 */
135 const char *arm_mode_name(unsigned psr_mode);
136 bool is_arm_mode(unsigned psr_mode);
138 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
147 /** ARM vector floating point enabled, if yes which version. */
148 enum arm_vfp_version {
155 #define ARM_COMMON_MAGIC 0x0A450A45
158 * Represents a generic ARM core, with standard application registers.
160 * There are sixteen application registers (including PC, SP, LR) and a PSR.
161 * Cortex-M series cores do not support as many core states or shadowed
162 * registers as traditional ARM cores, and only support Thumb2 instructions.
166 struct reg_cache *core_cache;
168 /** Handle to the PC; valid in all core modes. */
171 /** Handle to the CPSR/xPSR; valid in all core modes. */
174 /** Handle to the SPSR; valid only in core modes with an SPSR. */
177 /** Support for arm_reg_current() */
180 /** Indicates what registers are in the ARM state core register set. */
181 enum arm_core_type core_type;
183 /** Record the current core mode: SVC, USR, or some other mode. */
184 enum arm_mode core_mode;
186 /** Record the current core state: ARM, Thumb, or otherwise. */
187 enum arm_state core_state;
189 /** Flag reporting unavailability of the BKPT instruction. */
192 /** Flag reporting armv6m based core. */
195 /** Floating point or VFP version, 0 if disabled. */
198 int (*setup_semihosting)(struct target *target, int enable);
200 /** Backpointer to the target. */
201 struct target *target;
203 /** Handle for the debug module, if one is present. */
206 /** Handle for the Embedded Trace Module, if one is present. */
207 struct etm_context *etm;
209 /* FIXME all these methods should take "struct arm *" not target */
211 /** Retrieve all core registers, for display. */
212 int (*full_context)(struct target *target);
214 /** Retrieve a single core register. */
215 int (*read_core_reg)(struct target *target, struct reg *reg,
216 int num, enum arm_mode mode);
217 int (*write_core_reg)(struct target *target, struct reg *reg,
218 int num, enum arm_mode mode, uint8_t *value);
220 /** Read coprocessor register. */
221 int (*mrc)(struct target *target, int cpnum,
222 uint32_t op1, uint32_t op2,
223 uint32_t CRn, uint32_t CRm,
226 /** Write coprocessor register. */
227 int (*mcr)(struct target *target, int cpnum,
228 uint32_t op1, uint32_t op2,
229 uint32_t CRn, uint32_t CRm,
234 /** For targets conforming to ARM Debug Interface v5,
235 * this handle references the Debug Access Port (DAP)
236 * used to make requests to the target.
238 struct adiv5_dap *dap;
241 /** Convert target handle to generic ARM target state handle. */
242 static inline struct arm *target_to_arm(struct target *target)
244 assert(target != NULL);
245 return target->arch_info;
248 static inline bool is_arm(struct arm *arm)
251 return arm->common_magic == ARM_COMMON_MAGIC;
254 struct arm_algorithm {
257 enum arm_mode core_mode;
258 enum arm_state core_state;
264 struct target *target;
269 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
270 struct reg_cache *armv8_build_reg_cache(struct target *target);
272 extern const struct command_registration arm_command_handlers[];
274 int arm_arch_state(struct target *target);
275 const char *arm_get_gdb_arch(struct target *target);
276 int arm_get_gdb_reg_list(struct target *target,
277 struct reg **reg_list[], int *reg_list_size,
278 enum target_register_class reg_class);
279 const char *armv8_get_gdb_arch(struct target *target);
280 int armv8_get_gdb_reg_list(struct target *target,
281 struct reg **reg_list[], int *reg_list_size,
282 enum target_register_class reg_class);
284 int arm_init_arch_info(struct target *target, struct arm *arm);
286 /* REVISIT rename this once it's usable by ARMv7-M */
287 int armv4_5_run_algorithm(struct target *target,
288 int num_mem_params, struct mem_param *mem_params,
289 int num_reg_params, struct reg_param *reg_params,
290 target_addr_t entry_point, target_addr_t exit_point,
291 int timeout_ms, void *arch_info);
292 int armv4_5_run_algorithm_inner(struct target *target,
293 int num_mem_params, struct mem_param *mem_params,
294 int num_reg_params, struct reg_param *reg_params,
295 uint32_t entry_point, uint32_t exit_point,
296 int timeout_ms, void *arch_info,
297 int (*run_it)(struct target *target, uint32_t exit_point,
298 int timeout_ms, void *arch_info));
300 int arm_checksum_memory(struct target *target,
301 target_addr_t address, uint32_t count, uint32_t *checksum);
302 int arm_blank_check_memory(struct target *target,
303 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
305 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
306 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
307 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
309 extern struct reg arm_gdb_dummy_fp_reg;
310 extern struct reg arm_gdb_dummy_fps_reg;
312 #endif /* OPENOCD_TARGET_ARM_H */