2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Øyvind Harboe
9 * oyvind.harboe@zylin.com
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the
23 * Free Software Foundation, Inc.,
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 #include <helper/command.h>
35 * Holds the interface to ARM cores.
37 * At this writing, only "classic ARM" cores built on the ARMv4 register
38 * and mode model are supported. The Thumb2-only microcontroller profile
39 * support has not yet been integrated, affecting Cortex-M parts.
43 * Represent state of an ARM core.
45 * Most numbers match the five low bits of the *PSR registers on
46 * "classic ARM" processors, which build on the ARMv4 processor
47 * modes and register set.
49 * ARM_MODE_ANY is a magic value, often used as a wildcard.
51 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
52 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
72 const char *arm_mode_name(unsigned psr_mode);
73 bool is_arm_mode(unsigned psr_mode);
75 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
83 extern const char *arm_state_strings[];
85 #define ARM_COMMON_MAGIC 0x0A450A45
88 * Represents a generic ARM core, with standard application registers.
90 * There are sixteen application registers (including PC, SP, LR) and a PSR.
91 * Cortex-M series cores do not support as many core states or shadowed
92 * registers as traditional ARM cores, and only support Thumb2 instructions.
96 struct reg_cache *core_cache;
98 /** Handle to the PC; valid in all core modes. */
101 /** Handle to the CPSR; valid in all core modes. */
104 /** Handle to the SPSR; valid only in core modes with an SPSR. */
107 /** Support for arm_reg_current() */
111 * Indicates what registers are in the ARM state core register set.
112 * ARM_MODE_ANY indicates the standard set of 37 registers,
113 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
114 * more registers are shadowed, for "Secure Monitor" mode.
115 * ARM_MODE_THREAD indicates a microcontroller profile core,
116 * which only shadows SP.
118 enum arm_mode core_type;
120 /** Record the current core mode: SVC, USR, or some other mode. */
121 enum arm_mode core_mode;
123 /** Record the current core state: ARM, Thumb, or otherwise. */
124 enum arm_state core_state;
126 /** Flag reporting unavailability of the BKPT instruction. */
129 /** Flag reporting whether semihosting is active. */
132 /** Value to be returned by semihosting SYS_ERRNO request. */
133 int semihosting_errno;
135 /** Backpointer to the target. */
136 struct target *target;
138 /** Handle for the debug module, if one is present. */
141 /** Handle for the Embedded Trace Module, if one is present. */
142 struct etm_context *etm;
144 /* FIXME all these methods should take "struct arm *" not target */
146 /** Retrieve all core registers, for display. */
147 int (*full_context)(struct target *target);
149 /** Retrieve a single core register. */
150 int (*read_core_reg)(struct target *target, struct reg *reg,
151 int num, enum arm_mode mode);
152 int (*write_core_reg)(struct target *target, struct reg *reg,
153 int num, enum arm_mode mode, uint32_t value);
155 /** Read coprocessor register. */
156 int (*mrc)(struct target *target, int cpnum,
157 uint32_t op1, uint32_t op2,
158 uint32_t CRn, uint32_t CRm,
161 /** Write coprocessor register. */
162 int (*mcr)(struct target *target, int cpnum,
163 uint32_t op1, uint32_t op2,
164 uint32_t CRn, uint32_t CRm,
170 /** Convert target handle to generic ARM target state handle. */
171 static inline struct arm *target_to_arm(struct target *target)
173 return target->arch_info;
176 static inline bool is_arm(struct arm *arm)
178 return arm && arm->common_magic == ARM_COMMON_MAGIC;
181 struct arm_algorithm {
184 enum arm_mode core_mode;
185 enum arm_state core_state;
191 struct target *target;
192 struct arm *armv4_5_common;
196 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
198 extern const struct command_registration arm_command_handlers[];
200 int arm_arch_state(struct target *target);
201 int arm_get_gdb_reg_list(struct target *target,
202 struct reg **reg_list[], int *reg_list_size);
204 int arm_init_arch_info(struct target *target, struct arm *arm);
206 /* REVISIT rename this once it's usable by ARMv7-M */
207 int armv4_5_run_algorithm(struct target *target,
208 int num_mem_params, struct mem_param *mem_params,
209 int num_reg_params, struct reg_param *reg_params,
210 uint32_t entry_point, uint32_t exit_point,
211 int timeout_ms, void *arch_info);
212 int armv4_5_run_algorithm_inner(struct target *target,
213 int num_mem_params, struct mem_param *mem_params,
214 int num_reg_params, struct reg_param *reg_params,
215 uint32_t entry_point, uint32_t exit_point,
216 int timeout_ms, void *arch_info,
217 int (*run_it)(struct target *target, uint32_t exit_point,
218 int timeout_ms, void *arch_info));
220 int arm_checksum_memory(struct target *target,
221 uint32_t address, uint32_t count, uint32_t *checksum);
222 int arm_blank_check_memory(struct target *target,
223 uint32_t address, uint32_t count, uint32_t *blank);
225 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
226 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
228 void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
230 extern struct reg arm_gdb_dummy_fp_reg;
231 extern struct reg arm_gdb_dummy_fps_reg;