1 /***************************************************************************
2 * Copyright (C) 2013-2014,2019-2020 Synopsys, Inc. *
3 * Frank Dols <frank.dols@synopsys.com> *
4 * Mischa Jonker <mischa.jonker@synopsys.com> *
5 * Anton Kolesov <anton.kolesov@synopsys.com> *
6 * Evgeniy Didin <didin@synopsys.com> *
8 * SPDX-License-Identifier: GPL-2.0-or-later *
9 ***************************************************************************/
18 * This functions sets instruction register in TAP. TAP end state is always
22 * @param new_instr Instruction to write to instruction register.
24 static void arc_jtag_enque_write_ir(struct arc_jtag *jtag_info, uint32_t
27 uint32_t current_instr;
29 uint8_t instr_buffer[sizeof(uint32_t)];
32 assert(jtag_info->tap);
36 /* Do not set instruction if it is the same as current. */
37 current_instr = buf_get_u32(tap->cur_instr, 0, tap->ir_length);
38 if (current_instr == new_instr)
41 struct scan_field field = {
42 .num_bits = tap->ir_length,
43 .out_value = instr_buffer
45 buf_set_u32(instr_buffer, 0, field.num_bits, new_instr);
47 /* From code in src/jtag/drivers/driver.c it look like that fields are
48 * copied so it is OK that field in this function is allocated in stack and
49 * thus this memory will be repurposed before jtag_execute_queue() will be
51 jtag_add_ir_scan(tap, &field, TAP_IRPAUSE);
55 * Read 4-byte word from data register.
57 * Unlike arc_jtag_write_data, this function returns byte-buffer, caller must
58 * convert this data to required format himself. This is done, because it is
59 * impossible to convert data before jtag_execute_queue() is invoked, so it
60 * cannot be done inside this function, so it has to operate with
61 * byte-buffers. Write function on the other hand can "write-and-forget", data
62 * is converted to byte-buffer before jtag_execute_queue().
65 * @param data Array of bytes to read into.
66 * @param end_state End state after reading.
68 static void arc_jtag_enque_read_dr(struct arc_jtag *jtag_info, uint8_t *data,
69 tap_state_t end_state)
73 assert(jtag_info->tap);
75 struct scan_field field = {
80 jtag_add_dr_scan(jtag_info->tap, 1, &field, end_state);
84 * Write 4-byte word to data register.
87 * @param data 4-byte word to write into data register.
88 * @param end_state End state after writing.
90 static void arc_jtag_enque_write_dr(struct arc_jtag *jtag_info, uint32_t data,
91 tap_state_t end_state)
93 uint8_t out_value[sizeof(uint32_t)];
96 assert(jtag_info->tap);
98 buf_set_u32(out_value, 0, 32, data);
100 struct scan_field field = {
102 .out_value = out_value
105 jtag_add_dr_scan(jtag_info->tap, 1, &field, end_state);
110 * Set transaction in command register. This function sets instruction register
111 * and then transaction register, there is no need to invoke write_ir before
112 * invoking this function.
115 * @param new_trans Transaction to write to transaction command register.
116 * @param end_state End state after writing.
118 static void arc_jtag_enque_set_transaction(struct arc_jtag *jtag_info,
119 uint32_t new_trans, tap_state_t end_state)
121 uint8_t out_value[sizeof(uint32_t)];
124 assert(jtag_info->tap);
126 /* No need to do anything. */
127 if (jtag_info->cur_trans == new_trans)
130 /* Set instruction. We used to call write_ir at upper levels, however
131 * write_ir-write_transaction were constantly in pair, so to avoid code
132 * duplication this function does it self. For this reasons it is "set"
133 * instead of "write". */
134 arc_jtag_enque_write_ir(jtag_info, ARC_TRANSACTION_CMD_REG);
135 buf_set_u32(out_value, 0, ARC_TRANSACTION_CMD_REG_LENGTH, new_trans);
136 struct scan_field field = {
137 .num_bits = ARC_TRANSACTION_CMD_REG_LENGTH,
138 .out_value = out_value
141 jtag_add_dr_scan(jtag_info->tap, 1, &field, end_state);
142 jtag_info->cur_trans = new_trans;
146 * Run reset through transaction set. None of the previous
147 * settings/commands/etc. are used anymore (or no influence).
149 static void arc_jtag_enque_reset_transaction(struct arc_jtag *jtag_info)
151 arc_jtag_enque_set_transaction(jtag_info, ARC_JTAG_CMD_NOP, TAP_IDLE);
154 static void arc_jtag_enque_status_read(struct arc_jtag * const jtag_info,
155 uint8_t * const buffer)
158 assert(jtag_info->tap);
161 /* first writin code(0x8) of jtag status register in IR */
162 arc_jtag_enque_write_ir(jtag_info, ARC_JTAG_STATUS_REG);
163 /* Now reading dr performs jtag status register read */
164 arc_jtag_enque_read_dr(jtag_info, buffer, TAP_IDLE);
167 /* ----- Exported JTAG functions ------------------------------------------- */
169 int arc_jtag_startup(struct arc_jtag *jtag_info)
173 arc_jtag_enque_reset_transaction(jtag_info);
175 return jtag_execute_queue();
178 /** Read STATUS register. */
179 int arc_jtag_status(struct arc_jtag * const jtag_info, uint32_t * const value)
181 uint8_t buffer[sizeof(uint32_t)];
184 assert(jtag_info->tap);
186 /* Fill command queue. */
187 arc_jtag_enque_reset_transaction(jtag_info);
188 arc_jtag_enque_status_read(jtag_info, buffer);
189 arc_jtag_enque_reset_transaction(jtag_info);
192 CHECK_RETVAL(jtag_execute_queue());
195 *value = buf_get_u32(buffer, 0, 32);
199 /* Helper function: Adding read/write register operation to queue */
200 static void arc_jtag_enque_register_rw(struct arc_jtag *jtag_info, uint32_t *addr,
201 uint8_t *read_buffer, const uint32_t *write_buffer, uint32_t count)
205 for (i = 0; i < count; i++) {
206 /* ARC jtag has optimization which is to increment ADDRESS_REG performing
207 * each transaction. Making sequential reads/writes we can set address for
208 * only first register in sequence, and than do read/write in cycle. */
209 if (i == 0 || (addr[i] != addr[i-1] + 1)) {
210 arc_jtag_enque_write_ir(jtag_info, ARC_JTAG_ADDRESS_REG);
211 /* Going to TAP_IDLE state we initiate jtag transaction.
212 * Reading data we must go to TAP_IDLE, because further
213 * the data would be read. In case of write we go to TAP_DRPAUSE,
214 * because we need to write data to Data register first. */
216 arc_jtag_enque_write_dr(jtag_info, addr[i], TAP_DRPAUSE);
218 arc_jtag_enque_write_dr(jtag_info, addr[i], TAP_IDLE);
219 arc_jtag_enque_write_ir(jtag_info, ARC_JTAG_DATA_REG);
222 arc_jtag_enque_write_dr(jtag_info, *(write_buffer + i), TAP_IDLE);
224 arc_jtag_enque_read_dr(jtag_info, read_buffer + i * 4, TAP_IDLE);
226 /* To prevent pollution of next regiter due to optimization it is necessary *
227 * to reset transaction */
228 arc_jtag_enque_reset_transaction(jtag_info);
232 * Write registers. addr is an array of addresses, and those addresses can be
233 * in any order, though it is recommended that they are in sequential order
234 * where possible, as this reduces number of JTAG commands to transfer.
237 * @param type Type of registers to write: core or aux.
238 * @param addr Array of registers numbers.
239 * @param count Amount of registers in arrays.
240 * @param values Array of register values.
242 static int arc_jtag_write_registers(struct arc_jtag *jtag_info, uint32_t type,
243 uint32_t *addr, uint32_t count, const uint32_t *buffer)
245 LOG_DEBUG("Writing to %s registers: addr[0]=0x%" PRIx32 ";count=%" PRIu32
246 ";buffer[0]=0x%08" PRIx32,
247 (type == ARC_JTAG_CORE_REG ? "core" : "aux"), *addr, count, *buffer);
250 LOG_ERROR("Trying to write 0 registers");
254 arc_jtag_enque_reset_transaction(jtag_info);
256 /* What registers are we writing to? */
257 const uint32_t transaction = (type == ARC_JTAG_CORE_REG ?
258 ARC_JTAG_WRITE_TO_CORE_REG : ARC_JTAG_WRITE_TO_AUX_REG);
259 arc_jtag_enque_set_transaction(jtag_info, transaction, TAP_DRPAUSE);
261 arc_jtag_enque_register_rw(jtag_info, addr, NULL, buffer, count);
263 return jtag_execute_queue();
267 * Read registers. addr is an array of addresses, and those addresses can be in
268 * any order, though it is recommended that they are in sequential order where
269 * possible, as this reduces number of JTAG commands to transfer.
272 * @param type Type of registers to read: core or aux.
273 * @param addr Array of registers numbers.
274 * @param count Amount of registers in arrays.
275 * @param values Array of register values.
277 static int arc_jtag_read_registers(struct arc_jtag *jtag_info, uint32_t type,
278 uint32_t *addr, uint32_t count, uint32_t *buffer)
284 assert(jtag_info->tap);
286 LOG_DEBUG("Reading %s registers: addr[0]=0x%" PRIx32 ";count=%" PRIu32,
287 (type == ARC_JTAG_CORE_REG ? "core" : "aux"), *addr, count);
290 LOG_ERROR("Trying to read 0 registers");
294 arc_jtag_enque_reset_transaction(jtag_info);
296 /* What type of registers we are reading? */
297 const uint32_t transaction = (type == ARC_JTAG_CORE_REG ?
298 ARC_JTAG_READ_FROM_CORE_REG : ARC_JTAG_READ_FROM_AUX_REG);
299 arc_jtag_enque_set_transaction(jtag_info, transaction, TAP_DRPAUSE);
301 uint8_t *data_buf = calloc(sizeof(uint8_t), count * 4);
303 arc_jtag_enque_register_rw(jtag_info, addr, data_buf, NULL, count);
305 retval = jtag_execute_queue();
306 if (retval != ERROR_OK) {
307 LOG_ERROR("Failed to execute jtag queue: %d", retval);
312 /* Convert byte-buffers to host /presentation. */
313 for (i = 0; i < count; i++)
314 buffer[i] = buf_get_u32(data_buf + 4 * i, 0, 32);
316 LOG_DEBUG("Read from register: buf[0]=0x%" PRIx32, buffer[0]);
325 /** Wrapper function to ease writing of one core register. */
326 int arc_jtag_write_core_reg_one(struct arc_jtag *jtag_info, uint32_t addr,
329 return arc_jtag_write_core_reg(jtag_info, &addr, 1, &value);
333 * Write core registers. addr is an array of addresses, and those addresses can
334 * be in any order, though it is recommended that they are in sequential order
335 * where possible, as this reduces number of JTAG commands to transfer.
338 * @param addr Array of registers numbers.
339 * @param count Amount of registers in arrays.
340 * @param values Array of register values.
342 int arc_jtag_write_core_reg(struct arc_jtag *jtag_info, uint32_t *addr,
343 uint32_t count, const uint32_t *buffer)
345 return arc_jtag_write_registers(jtag_info, ARC_JTAG_CORE_REG, addr, count,
349 /** Wrapper function to ease reading of one core register. */
350 int arc_jtag_read_core_reg_one(struct arc_jtag *jtag_info, uint32_t addr,
353 return arc_jtag_read_core_reg(jtag_info, &addr, 1, value);
357 * Read core registers. addr is an array of addresses, and those addresses can
358 * be in any order, though it is recommended that they are in sequential order
359 * where possible, as this reduces number of JTAG commands to transfer.
362 * @param addr Array of core register numbers.
363 * @param count Amount of registers in arrays.
364 * @param values Array of register values.
366 int arc_jtag_read_core_reg(struct arc_jtag *jtag_info, uint32_t *addr,
367 uint32_t count, uint32_t *buffer)
369 return arc_jtag_read_registers(jtag_info, ARC_JTAG_CORE_REG, addr, count,
373 /** Wrapper function to ease writing of one AUX register. */
374 int arc_jtag_write_aux_reg_one(struct arc_jtag *jtag_info, uint32_t addr,
377 return arc_jtag_write_aux_reg(jtag_info, &addr, 1, &value);
381 * Write AUX registers. addr is an array of addresses, and those addresses can
382 * be in any order, though it is recommended that they are in sequential order
383 * where possible, as this reduces number of JTAG commands to transfer.
386 * @param addr Array of registers numbers.
387 * @param count Amount of registers in arrays.
388 * @param values Array of register values.
390 int arc_jtag_write_aux_reg(struct arc_jtag *jtag_info, uint32_t *addr,
391 uint32_t count, const uint32_t *buffer)
393 return arc_jtag_write_registers(jtag_info, ARC_JTAG_AUX_REG, addr, count,
397 /** Wrapper function to ease reading of one AUX register. */
398 int arc_jtag_read_aux_reg_one(struct arc_jtag *jtag_info, uint32_t addr,
401 return arc_jtag_read_aux_reg(jtag_info, &addr, 1, value);
405 * Read AUX registers. addr is an array of addresses, and those addresses can
406 * be in any order, though it is recommended that they are in sequential order
407 * where possible, as this reduces number of JTAG commands to transfer.
410 * @param addr Array of AUX register numbers.
411 * @param count Amount of registers in arrays.
412 * @param values Array of register values.
414 int arc_jtag_read_aux_reg(struct arc_jtag *jtag_info, uint32_t *addr,
415 uint32_t count, uint32_t *buffer)
417 return arc_jtag_read_registers(jtag_info, ARC_JTAG_AUX_REG, addr, count,
422 * Write a sequence of 4-byte words into target memory.
424 * We can write only 4byte words via JTAG, so any non-word writes should be
425 * handled at higher levels by read-modify-write.
427 * This function writes directly to the memory, leaving any caches (if there
428 * are any) in inconsistent state. It is responsibility of upper level to
432 * @param addr Address of first word to write into.
433 * @param count Amount of word to write.
434 * @param buffer Array to write into memory.
436 int arc_jtag_write_memory(struct arc_jtag *jtag_info, uint32_t addr,
437 uint32_t count, const uint32_t *buffer)
442 LOG_DEBUG("Writing to memory: addr=0x%08" PRIx32 ";count=%" PRIu32 ";buffer[0]=0x%08" PRIx32,
443 addr, count, *buffer);
445 /* No need to waste time on useless operations. */
449 /* We do not know where we come from. */
450 arc_jtag_enque_reset_transaction(jtag_info);
452 /* We want to write to memory. */
453 arc_jtag_enque_set_transaction(jtag_info, ARC_JTAG_WRITE_TO_MEMORY, TAP_DRPAUSE);
455 /* Set target memory address of the first word. */
456 arc_jtag_enque_write_ir(jtag_info, ARC_JTAG_ADDRESS_REG);
457 arc_jtag_enque_write_dr(jtag_info, addr, TAP_DRPAUSE);
459 /* Start sending words. Address is auto-incremented on 4bytes by HW. */
460 arc_jtag_enque_write_ir(jtag_info, ARC_JTAG_DATA_REG);
463 for (i = 0; i < count; i++)
464 arc_jtag_enque_write_dr(jtag_info, *(buffer + i), TAP_IDLE);
466 return jtag_execute_queue();
470 * Read a sequence of 4-byte words from target memory.
472 * We can read only 4byte words via JTAG.
474 * This function read directly from the memory, so it can read invalid data if
475 * data cache hasn't been flushed before hand. It is responsibility of upper
476 * level to resolve this.
479 * @param addr Address of first word to read from.
480 * @param count Amount of words to read.
481 * @param buffer Array of words to read into.
482 * @param slow_memory Whether this is a slow memory (DDR) or fast (CCM).
484 int arc_jtag_read_memory(struct arc_jtag *jtag_info, uint32_t addr,
485 uint32_t count, uint32_t *buffer, bool slow_memory)
489 int retval = ERROR_OK;
493 assert(jtag_info->tap);
495 LOG_DEBUG("Reading memory: addr=0x%" PRIx32 ";count=%" PRIu32 ";slow=%c",
496 addr, count, slow_memory ? 'Y' : 'N');
501 data_buf = calloc(sizeof(uint8_t), count * 4);
502 arc_jtag_enque_reset_transaction(jtag_info);
504 /* We are reading from memory. */
505 arc_jtag_enque_set_transaction(jtag_info, ARC_JTAG_READ_FROM_MEMORY, TAP_DRPAUSE);
508 for (i = 0; i < count; i++) {
509 /* When several words are read at consequent addresses we can
510 * rely on ARC JTAG auto-incrementing address. That means that
511 * address can be set only once, for a first word. However it
512 * has been noted that at least in some cases when reading from
513 * DDR, JTAG returns 0 instead of a real value. To workaround
514 * this issue we need to do totally non-required address
515 * writes, which however resolve a problem by introducing
516 * delay. See STAR 9000832538... */
517 if (slow_memory || i == 0) {
519 arc_jtag_enque_write_ir(jtag_info, ARC_JTAG_ADDRESS_REG);
520 arc_jtag_enque_write_dr(jtag_info, addr + i * 4, TAP_IDLE);
522 arc_jtag_enque_write_ir(jtag_info, ARC_JTAG_DATA_REG);
524 arc_jtag_enque_read_dr(jtag_info, data_buf + i * 4, TAP_IDLE);
526 retval = jtag_execute_queue();
527 if (retval != ERROR_OK) {
528 LOG_ERROR("Failed to execute jtag queue: %d", retval);
533 /* Convert byte-buffers to host presentation. */
534 for (i = 0; i < count; i++)
535 buffer[i] = buf_get_u32(data_buf + 4*i, 0, 32);