1 /***************************************************************************
2 * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
3 * Frank Dols <frank.dols@synopsys.com> *
4 * Mischa Jonker <mischa.jonker@synopsys.com> *
5 * Anton Kolesov <anton.kolesov@synopsys.com> *
6 * Evgeniy Didin <didin@synopsys.com> *
8 * SPDX-License-Identifier: GPL-2.0-or-later *
9 ***************************************************************************/
11 #ifndef OPENOCD_TARGET_ARC_H
12 #define OPENOCD_TARGET_ARC_H
14 #include <helper/time_support.h>
15 #include <jtag/jtag.h>
17 #include "algorithm.h"
18 #include "breakpoints.h"
19 #include "jtag/interface.h"
22 #include "target_request.h"
23 #include "target_type.h"
24 #include "helper/bits.h"
30 #define ARC_COMMON_MAGIC 0xB32EB324 /* just a unique number */
32 #define AUX_DEBUG_REG 0x5
33 #define AUX_PC_REG 0x6
34 #define AUX_STATUS32_REG 0xA
37 #define SET_CORE_FORCE_HALT BIT(1)
38 #define SET_CORE_HALT_BIT BIT(0) /* STATUS32[0] = H field */
39 #define SET_CORE_ENABLE_INTERRUPTS BIT(31)
40 /* STATUS32[5] or AE bit indicates if the processor is in exception state */
41 #define SET_CORE_AE_BIT BIT(5)
42 /* Single instruction step bit in Debug register */
43 #define SET_CORE_SINGLE_INSTR_STEP BIT(11)
45 #define AUX_STATUS32_REG_HALT_BIT BIT(0)
46 #define AUX_STATUS32_REG_IE_BIT BIT(31) /* STATUS32[31] = IE field */
48 /* Reserved core registers */
49 #define CORE_R61_NUM (61)
50 #define CORE_R62_NUM (62)
52 #define CORE_REG_MAX_NUMBER (63)
54 /* Limit reg_type/reg_type_field name to 20 symbols */
55 #define REG_TYPE_MAX_NAME_LENGTH 20
57 /* ARC 32bits opcodes */
58 #define ARC_SDBBP_32 0x256F003F /* BRK */
60 /* ARC 16bits opcodes */
61 #define ARC_SDBBP_16 0x7FFF /* BRK_S */
64 #define AUX_IC_IVIC_REG 0X10
65 #define IC_IVIC_INVALIDATE 0XFFFFFFFF
67 #define AUX_DC_IVDC_REG 0X47
68 #define DC_IVDC_INVALIDATE BIT(0)
69 #define AUX_DC_CTRL_REG 0X48
70 #define DC_CTRL_IM BIT(6)
72 /* L2 cache registers */
73 #define SLC_AUX_CACHE_CTRL 0x903
74 #define L2_CTRL_IM BIT(6)
75 #define L2_CTRL_BS BIT(8) /* Busy flag */
76 #define SLC_AUX_CACHE_FLUSH 0x904
77 #define L2_FLUSH_FL BIT(0)
78 #define SLC_AUX_CACHE_INV 0x905
79 #define L2_INV_IV BIT(0)
81 struct arc_reg_bitfield {
82 struct reg_data_type_bitfield bitfield;
83 char name[REG_TYPE_MAX_NAME_LENGTH];
85 /* Register data type */
86 struct arc_reg_data_type {
87 struct list_head list;
88 struct reg_data_type data_type;
89 struct reg_data_type_flags data_type_flags;
90 struct reg_data_type_struct data_type_struct;
91 char data_type_id[REG_TYPE_MAX_NAME_LENGTH];
92 struct arc_reg_bitfield *bitfields;
94 struct reg_data_type_struct_field *reg_type_struct_field;
95 struct reg_data_type_flags_field *reg_type_flags_field;
101 /* Standard GDB register types */
102 static const struct reg_data_type standard_gdb_types[] = {
103 { .type = REG_TYPE_INT, .id = "int" },
104 { .type = REG_TYPE_INT8, .id = "int8" },
105 { .type = REG_TYPE_INT16, .id = "int16" },
106 { .type = REG_TYPE_INT32, .id = "int32" },
107 { .type = REG_TYPE_INT64, .id = "int64" },
108 { .type = REG_TYPE_INT128, .id = "int128" },
109 { .type = REG_TYPE_UINT8, .id = "uint8" },
110 { .type = REG_TYPE_UINT16, .id = "uint16" },
111 { .type = REG_TYPE_UINT32, .id = "uint32" },
112 { .type = REG_TYPE_UINT64, .id = "uint64" },
113 { .type = REG_TYPE_UINT128, .id = "uint128" },
114 { .type = REG_TYPE_CODE_PTR, .id = "code_ptr" },
115 { .type = REG_TYPE_DATA_PTR, .id = "data_ptr" },
116 { .type = REG_TYPE_FLOAT, .id = "float" },
117 { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" },
118 { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" },
123 uint32_t common_magic;
125 struct arc_jtag jtag_info;
127 struct reg_cache *core_and_aux_cache;
128 struct reg_cache *bcr_cache;
134 /* If true, then D$ has been already flushed since core has been
137 /* If true, then L2 has been already flushed since core has been
139 bool l2cache_flushed;
140 /* If true, then caches have been already flushed since core has been
142 bool icache_invalidated;
143 bool dcache_invalidated;
144 bool l2cache_invalidated;
146 /* Indicate if cach was built (for deinit function) */
147 bool core_aux_cache_built;
148 bool bcr_cache_built;
149 /* Closely Coupled memory(CCM) regions for performance-critical
150 * code (optional). */
151 uint32_t iccm0_start;
153 uint32_t iccm1_start;
160 /* Register descriptions */
161 struct list_head reg_data_types;
162 struct list_head core_reg_descriptions;
163 struct list_head aux_reg_descriptions;
164 struct list_head bcr_reg_descriptions;
165 unsigned long num_regs;
166 unsigned long num_core_regs;
167 unsigned long num_aux_regs;
168 unsigned long num_bcr_regs;
169 unsigned long last_general_reg;
171 /* PC register location in register cache. */
172 unsigned long pc_index_in_cache;
173 /* DEBUG register location in register cache. */
174 unsigned long debug_index_in_cache;
177 /* Borrowed from nds32.h */
178 #define CHECK_RETVAL(action) \
180 int __retval = (action); \
181 if (__retval != ERROR_OK) { \
182 LOG_DEBUG("error while calling \"%s\"", \
188 #define JIM_CHECK_RETVAL(action) \
190 int __retval = (action); \
191 if (__retval != JIM_OK) { \
192 LOG_DEBUG("error while calling \"%s\"", \
198 static inline struct arc_common *target_to_arc(struct target *target)
200 return target->arch_info;
203 /* ----- Inlined functions ------------------------------------------------- */
206 * Convert data in host endianness to the middle endian. This is required to
207 * write 4-byte instructions.
209 static inline void arc_h_u32_to_me(uint8_t *buf, int val)
211 buf[1] = (uint8_t) (val >> 24);
212 buf[0] = (uint8_t) (val >> 16);
213 buf[3] = (uint8_t) (val >> 8);
214 buf[2] = (uint8_t) (val >> 0);
218 * Convert data in middle endian to host endian. This is required to read 32-bit
219 * instruction from little endian ARCs.
221 static inline uint32_t arc_me_to_h_u32(const uint8_t *buf)
223 return (uint32_t)(buf[2] | buf[3] << 8 | buf[0] << 16 | buf[1] << 24);
227 /* ARC Register description */
228 struct arc_reg_desc {
230 struct target *target;
235 /* Actual place of storing reg_value */
236 uint8_t reg_value[4];
238 /* Actual place of storing register feature */
239 struct reg_feature feature;
241 /* GDB XML feature */
242 char *gdb_xml_feature;
244 /* Is this a register in g/G-packet? */
247 /* Architectural number: core reg num or AUX reg num */
250 /* Core or AUX register? */
253 /* Build configuration register? */
257 struct reg_data_type *data_type;
259 struct list_head list;
263 #define ERROR_ARC_REGISTER_NOT_FOUND (-700)
264 #define ERROR_ARC_REGISTER_FIELD_NOT_FOUND (-701)
265 #define ERROR_ARC_REGISTER_IS_NOT_STRUCT (-702)
266 #define ERROR_ARC_FIELD_IS_NOT_BITFIELD (-703)
267 #define ERROR_ARC_REGTYPE_NOT_FOUND (-704)
269 void free_reg_desc(struct arc_reg_desc *r);
272 void arc_reg_data_type_add(struct target *target,
273 struct arc_reg_data_type *data_type);
275 int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
276 const char * const type_name, const size_t type_name_len);
278 struct reg *arc_reg_get_by_name(struct reg_cache *first,
279 const char *name, bool search_all);
281 int arc_reg_get_field(struct target *target, const char *reg_name,
282 const char *field_name, uint32_t *value_ptr);
284 int arc_cache_flush(struct target *target);
285 int arc_cache_invalidate(struct target *target);
287 #endif /* OPENOCD_TARGET_ARC_H */