Introduce ARCv2 architecture related code
[fw/openocd] / src / target / arc.h
1 /***************************************************************************
2  *   Copyright (C) 2013-2015,2019-2020 Synopsys, Inc.                      *
3  *   Frank Dols <frank.dols@synopsys.com>                                  *
4  *   Mischa Jonker <mischa.jonker@synopsys.com>                            *
5  *   Anton Kolesov <anton.kolesov@synopsys.com>                            *
6  *   Evgeniy Didin <didin@synopsys.com>                                    *
7  *                                                                         *
8  *   SPDX-License-Identifier: GPL-2.0-or-later                             *
9  ***************************************************************************/
10
11 #ifndef OPENOCD_TARGET_ARC_H
12 #define OPENOCD_TARGET_ARC_H
13
14 #include <helper/time_support.h>
15 #include <jtag/jtag.h>
16
17 #include "algorithm.h"
18 #include "breakpoints.h"
19 #include "jtag/interface.h"
20 #include "register.h"
21 #include "target.h"
22 #include "target_request.h"
23 #include "target_type.h"
24 #include "helper/bits.h"
25
26 #include "arc_jtag.h"
27 #include "arc_cmd.h"
28 #include "arc_mem.h"
29
30 #define ARC_COMMON_MAGIC        0xB32EB324  /* just a unique number */
31
32 #define AUX_DEBUG_REG                   0x5
33 #define AUX_PC_REG                      0x6
34 #define AUX_STATUS32_REG                0xA
35
36 #define SET_CORE_FORCE_HALT             BIT(1)
37 #define SET_CORE_HALT_BIT               BIT(0)      /* STATUS32[0] = H field */
38 #define SET_CORE_ENABLE_INTERRUPTS                      BIT(31)
39
40 #define AUX_STATUS32_REG_HALT_BIT       BIT(0)
41 #define AUX_STATUS32_REG_IE_BIT         BIT(31)    /* STATUS32[31] = IE field */
42
43 /* Reserved core registers */
44 #define CORE_R61_NUM                    (61)
45 #define CORE_R62_NUM                    (62)
46
47 #define CORE_REG_MAX_NUMBER             (63)
48
49 /* Limit reg_type/reg_type_field  name to 20 symbols */
50 #define REG_TYPE_MAX_NAME_LENGTH        20
51
52 struct arc_reg_bitfield {
53         struct reg_data_type_bitfield bitfield;
54         char name[REG_TYPE_MAX_NAME_LENGTH];
55 };
56 /* Register data type */
57 struct arc_reg_data_type {
58         struct list_head list;
59         struct reg_data_type data_type;
60         struct reg_data_type_flags data_type_flags;
61         struct reg_data_type_struct data_type_struct;
62         char data_type_id[REG_TYPE_MAX_NAME_LENGTH];
63         struct arc_reg_bitfield *bitfields;
64 };
65
66
67
68 /* Standard GDB register types */
69 static const struct reg_data_type standard_gdb_types[] = {
70         { .type = REG_TYPE_INT,         .id = "int" },
71         { .type = REG_TYPE_INT8,        .id = "int8" },
72         { .type = REG_TYPE_INT16,       .id = "int16" },
73         { .type = REG_TYPE_INT32,       .id = "int32" },
74         { .type = REG_TYPE_INT64,       .id = "int64" },
75         { .type = REG_TYPE_INT128,      .id = "int128" },
76         { .type = REG_TYPE_UINT8,       .id = "uint8" },
77         { .type = REG_TYPE_UINT16,      .id = "uint16" },
78         { .type = REG_TYPE_UINT32,      .id = "uint32" },
79         { .type = REG_TYPE_UINT64,      .id = "uint64" },
80         { .type = REG_TYPE_UINT128,     .id = "uint128" },
81         { .type = REG_TYPE_CODE_PTR,    .id = "code_ptr" },
82         { .type = REG_TYPE_DATA_PTR,    .id = "data_ptr" },
83         { .type = REG_TYPE_FLOAT,       .id = "float" },
84         { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" },
85         { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" },
86 };
87
88
89 struct arc_common {
90         uint32_t common_magic;
91
92         struct arc_jtag jtag_info;
93
94         struct reg_cache *core_and_aux_cache;
95         struct reg_cache *bcr_cache;
96
97         /* Indicate if cach was built (for deinit function) */
98         bool core_aux_cache_built;
99         bool bcr_cache_built;
100         /* Closely Coupled memory(CCM) regions for performance-critical
101          * code (optional). */
102         uint32_t iccm0_start;
103         uint32_t iccm0_end;
104         uint32_t iccm1_start;
105         uint32_t iccm1_end;
106         uint32_t dccm_start;
107         uint32_t dccm_end;
108
109         int irq_state;
110
111         /* Register descriptions */
112         struct list_head reg_data_types;
113         struct list_head core_reg_descriptions;
114         struct list_head aux_reg_descriptions;
115         struct list_head bcr_reg_descriptions;
116         unsigned long num_regs;
117         unsigned long num_core_regs;
118         unsigned long num_aux_regs;
119         unsigned long num_bcr_regs;
120         unsigned long last_general_reg;
121
122         /* PC register location in register cache. */
123         unsigned long pc_index_in_cache;
124         /* DEBUG register location in register cache. */
125         unsigned long debug_index_in_cache;
126 };
127
128 /* Borrowed from nds32.h */
129 #define CHECK_RETVAL(action)                    \
130         do {                                    \
131                 int __retval = (action);        \
132                 if (__retval != ERROR_OK) {     \
133                         LOG_DEBUG("error while calling \"%s\"", \
134                                 # action);     \
135                         return __retval;        \
136                 }                               \
137         } while (0)
138
139 #define JIM_CHECK_RETVAL(action)                \
140         do {                                    \
141                 int __retval = (action);        \
142                 if (__retval != JIM_OK) {       \
143                         LOG_DEBUG("error while calling \"%s\"", \
144                                 # action);     \
145                         return __retval;        \
146                 }                               \
147         } while (0)
148
149 static inline struct arc_common *target_to_arc(struct target *target)
150 {
151         return target->arch_info;
152 }
153
154
155 /* ARC Register description */
156 struct arc_reg_desc {
157
158         struct target *target;
159
160         /* Register name */
161         char *name;
162
163         /* Actual place of storing reg_value */
164         uint8_t reg_value[4];
165
166         /* Actual place of storing register feature */
167         struct reg_feature feature;
168
169         /* GDB XML feature */
170         char *gdb_xml_feature;
171
172         /* Is this a register in g/G-packet? */
173         bool is_general;
174
175         /* Architectural number: core reg num or AUX reg num */
176         uint32_t arch_num;
177
178         /* Core or AUX register? */
179         bool is_core;
180
181         /* Build configuration register? */
182         bool is_bcr;
183
184         /* Data type */
185         struct reg_data_type *data_type;
186
187         struct list_head list;
188 };
189
190 /* Error codes */
191 #define ERROR_ARC_REGISTER_NOT_FOUND       (-700)
192 #define ERROR_ARC_REGISTER_FIELD_NOT_FOUND (-701)
193 #define ERROR_ARC_REGISTER_IS_NOT_STRUCT   (-702)
194 #define ERROR_ARC_FIELD_IS_NOT_BITFIELD    (-703)
195 #define ERROR_ARC_REGTYPE_NOT_FOUND        (-704)
196
197 void free_reg_desc(struct arc_reg_desc *r);
198
199
200 void arc_reg_data_type_add(struct target *target,
201                 struct arc_reg_data_type *data_type);
202
203 int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
204                 const char * const type_name, const size_t type_name_len);
205
206 struct reg *arc_reg_get_by_name(struct reg_cache *first,
207                                         const char *name, bool search_all);
208
209 int arc_reg_get_field(struct target *target, const char *reg_name,
210                 const char *field_name, uint32_t *value_ptr);
211
212 #endif /* OPENOCD_TARGET_ARC_H */