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   1 /***************************************************************************
   2  *   Copyright (C) 2013-2015,2019-2020 Synopsys, Inc.                      *
   3  *   Frank Dols <frank.dols@synopsys.com>                                  *
   4  *   Mischa Jonker <mischa.jonker@synopsys.com>                            *
   5  *   Anton Kolesov <anton.kolesov@synopsys.com>                            *
   6  *   Evgeniy Didin <didin@synopsys.com>                                    *
   7  *                                                                         *
   8  *   SPDX-License-Identifier: GPL-2.0-or-later                             *
   9  ***************************************************************************/
  10
  11
  12 #ifdef HAVE_CONFIG_H
  13 #include "config.h"
  14 #endif
  15
  16 #include "arc.h"
  17
  18
  19
  20 /*
  21  * ARC architecture specific details.
  22  *
  23  * ARC has two types of registers:
  24  *  1) core registers(e.g. r0,r1..) [is_core = true]
  25  *  2) Auxiliary registers [is_core = false]..
  26  *
  27  * Auxiliary registers at the same time can be divided into
  28  * read-only BCR(build configuration regs, e.g. isa_config, mpu_build) and
  29  * R/RW non-BCR ("control" register, e.g. pc, status32_t, debug).
  30  *
  31  * The way of accessing to Core and AUX registers differs on Jtag level.
  32  * BCR/non-BCR describes if the register is immutable and that reading
  33  * unexisting register is safe RAZ, rather then an error.
  34  * Note, core registers cannot be BCR.
  35  *
  36  * In arc/cpu/ tcl files all registers are defined as core, non-BCR aux
  37  * and BCR aux, in "add-reg" command they are passed to three lists
  38  * respectively:  core_reg_descriptions, aux_reg_descriptions,
  39  * bcr_reg_descriptions.
  40  *
  41  * Due to the specifics of accessing to BCR/non-BCR registers there are two
  42  * register caches:
  43  *  1) core_and_aux_cache - includes registers described in
  44  *     core_reg_descriptions and aux_reg_descriptions lists.
  45  *     Used during save/restore context step.
  46  *  2) bcr_cache - includes registers described bcr_reg_descriptions.
  47  *     Currently used internally during configure step.
  48  */
  49
  50
  51 static int arc_remove_watchpoint(struct target *target,
  52         struct watchpoint *watchpoint);
  53
  54 void arc_reg_data_type_add(struct target *target,
  55                 struct arc_reg_data_type *data_type)
  56 {
  57         LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id);
  58         struct arc_common *arc = target_to_arc(target);
  59         assert(arc);
  60
  61         list_add_tail(&data_type->list, &arc->reg_data_types);
  62 }
  63
  64 /**
  65  * Private implementation of register_get_by_name() for ARC that
  66  * doesn't skip not [yet] existing registers. Used in many places
  67  * for iteration through registers and even for marking required registers as
  68  * existing.
  69  */
  70 struct reg *arc_reg_get_by_name(struct reg_cache *first,
  71                 const char *name, bool search_all)
  72 {
  73         unsigned int i;
  74         struct reg_cache *cache = first;
  75
  76         while (cache) {
  77                 for (i = 0; i < cache->num_regs; i++) {
  78                         if (!strcmp(cache->reg_list[i].name, name))
  79                                 return &(cache->reg_list[i]);
  80                 }
  81
  82                 if (search_all)
  83                         cache = cache->next;
  84                 else
  85                         break;
  86         }
  87
  88         return NULL;
  89 }
  90
  91 /**
  92  * Reset internal states of caches. Must be called when entering debugging.
  93  *
  94  * @param target Target for which to reset caches states.
  95  */
  96 int arc_reset_caches_states(struct target *target)
  97 {
  98         struct arc_common *arc = target_to_arc(target);
  99
 100         LOG_DEBUG("Resetting internal variables of caches states");
 101
 102         /* Reset caches states. */
 103         arc->dcache_flushed = false;
 104         arc->l2cache_flushed = false;
 105         arc->icache_invalidated = false;
 106         arc->dcache_invalidated = false;
 107         arc->l2cache_invalidated = false;
 108
 109         return ERROR_OK;
 110 }
 111
 112 /* Initialize arc_common structure, which passes to openocd target instance */
 113 static int arc_init_arch_info(struct target *target, struct arc_common *arc,
 114         struct jtag_tap *tap)
 115 {
 116         arc->common_magic = ARC_COMMON_MAGIC;
 117         target->arch_info = arc;
 118
 119         arc->jtag_info.tap = tap;
 120
 121         /* The only allowed ir_length is 4 for ARC jtag. */
 122         if (tap->ir_length != 4) {
 123                 LOG_ERROR("ARC jtag instruction length should be equal to 4");
 124                 return ERROR_FAIL;
 125         }
 126
 127         /* On most ARC targets there is a dcache, so we enable its flushing
 128          * by default. If there no dcache, there will be no error, just a slight
 129          * performance penalty from unnecessary JTAG operations. */
 130         arc->has_dcache = true;
 131         arc->has_icache = true;
 132         /* L2$ is not available in a target by default. */
 133         arc->has_l2cache = false;
 134         arc_reset_caches_states(target);
 135
 136         /* Add standard GDB data types */
 137         INIT_LIST_HEAD(&arc->reg_data_types);
 138         struct arc_reg_data_type *std_types = calloc(ARRAY_SIZE(standard_gdb_types),
 139                 sizeof(*std_types));
 140
 141         if (!std_types) {
 142                 LOG_ERROR("Unable to allocate memory");
 143                 return ERROR_FAIL;
 144         }
 145
 146         for (unsigned int i = 0; i < ARRAY_SIZE(standard_gdb_types); i++) {
 147                 std_types[i].data_type.type = standard_gdb_types[i].type;
 148                 std_types[i].data_type.id = standard_gdb_types[i].id;
 149                 arc_reg_data_type_add(target, &(std_types[i]));
 150         }
 151
 152         /* Fields related to target descriptions */
 153         INIT_LIST_HEAD(&arc->core_reg_descriptions);
 154         INIT_LIST_HEAD(&arc->aux_reg_descriptions);
 155         INIT_LIST_HEAD(&arc->bcr_reg_descriptions);
 156         arc->num_regs = 0;
 157         arc->num_core_regs = 0;
 158         arc->num_aux_regs = 0;
 159         arc->num_bcr_regs = 0;
 160         arc->last_general_reg = ULONG_MAX;
 161         arc->pc_index_in_cache = ULONG_MAX;
 162         arc->debug_index_in_cache = ULONG_MAX;
 163
 164         return ERROR_OK;
 165 }
 166
 167 int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
 168                 const char * const type_name, const size_t type_name_len)
 169 {
 170         assert(target);
 171         assert(arc_reg);
 172
 173         struct arc_common *arc = target_to_arc(target);
 174         assert(arc);
 175
 176         /* Find register type */
 177         {
 178                 struct arc_reg_data_type *type;
 179                 list_for_each_entry(type, &arc->reg_data_types, list)
 180                         if (!strncmp(type->data_type.id, type_name, type_name_len)) {
 181                                 arc_reg->data_type = &(type->data_type);
 182                                 break;
 183                         }
 184
 185                 if (!arc_reg->data_type)
 186                         return ERROR_ARC_REGTYPE_NOT_FOUND;
 187         }
 188
 189         if (arc_reg->is_core) {
 190                 list_add_tail(&arc_reg->list, &arc->core_reg_descriptions);
 191                 arc->num_core_regs += 1;
 192         } else if (arc_reg->is_bcr) {
 193                 list_add_tail(&arc_reg->list, &arc->bcr_reg_descriptions);
 194                 arc->num_bcr_regs += 1;
 195         } else {
 196                 list_add_tail(&arc_reg->list, &arc->aux_reg_descriptions);
 197                 arc->num_aux_regs += 1;
 198         }
 199         arc->num_regs += 1;
 200
 201         LOG_DEBUG(
 202                         "added register {name=%s, num=0x%" PRIx32 ", type=%s%s%s%s}",
 203                         arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id,
 204                         arc_reg->is_core ? ", core" : "",  arc_reg->is_bcr ? ", bcr" : "",
 205                         arc_reg->is_general ? ", general" : ""
 206                 );
 207
 208         return ERROR_OK;
 209 }
 210
 211 /* Reading core or aux register */
 212 static int arc_get_register(struct reg *reg)
 213 {
 214         assert(reg);
 215
 216         struct arc_reg_desc *desc = reg->arch_info;
 217         struct target *target = desc->target;
 218         struct arc_common *arc = target_to_arc(target);
 219
 220         uint32_t value;
 221
 222         if (reg->valid) {
 223                 LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
 224                                 reg->number, desc->name, target_buffer_get_u32(target, reg->value));
 225                 return ERROR_OK;
 226         }
 227
 228         if (desc->is_core) {
 229                 /* Accessing to R61/R62 registers causes Jtag hang */
 230                 if (desc->arch_num == CORE_R61_NUM || desc->arch_num == CORE_R62_NUM) {
 231                         LOG_ERROR("It is forbidden to read core registers 61 and 62.");
 232                         return ERROR_FAIL;
 233                 }
 234                 CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, desc->arch_num,
 235                                         &value));
 236         } else {
 237                 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, desc->arch_num,
 238                         &value));
 239         }
 240
 241         target_buffer_set_u32(target, reg->value, value);
 242
 243         /* If target is unhalted all register reads should be uncached. */
 244         if (target->state == TARGET_HALTED)
 245                 reg->valid = true;
 246         else
 247                 reg->valid = false;
 248
 249         reg->dirty = false;
 250
 251         LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
 252                         reg->number, desc->name, value);
 253
 254
 255         return ERROR_OK;
 256 }
 257
 258 /* Writing core or aux register */
 259 static int arc_set_register(struct reg *reg, uint8_t *buf)
 260 {
 261         struct arc_reg_desc *desc = reg->arch_info;
 262         struct target *target = desc->target;
 263         uint32_t value = target_buffer_get_u32(target, buf);
 264         /* Unlike "get" function "set" is supported only if target
 265         * is in halt mode. Async writes are not supported yet. */
 266         if (target->state != TARGET_HALTED)
 267                 return ERROR_TARGET_NOT_HALTED;
 268
 269         /* Accessing to R61/R62 registers causes Jtag hang */
 270         if (desc->is_core && (desc->arch_num == CORE_R61_NUM ||
 271                         desc->arch_num == CORE_R62_NUM)) {
 272                 LOG_ERROR("It is forbidden to write core registers 61 and 62.");
 273                 return ERROR_FAIL;
 274         }
 275         target_buffer_set_u32(target, reg->value, value);
 276
 277         LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
 278                         reg->number, desc->name, value);
 279
 280         reg->valid = true;
 281         reg->dirty = true;
 282
 283         return ERROR_OK;
 284 }
 285
 286 const struct reg_arch_type arc_reg_type = {
 287         .get = arc_get_register,
 288         .set = arc_set_register,
 289 };
 290
 291 /* GDB register groups. For now we support only general and "empty" */
 292 static const char * const reg_group_general = "general";
 293 static const char * const reg_group_other = "";
 294
 295 /* Common code to initialize `struct reg` for different registers: core, aux, bcr. */
 296 static int arc_init_reg(struct target *target, struct reg *reg,
 297                         struct arc_reg_desc *reg_desc, unsigned long number)
 298 {
 299         assert(target);
 300         assert(reg);
 301         assert(reg_desc);
 302
 303         struct arc_common *arc = target_to_arc(target);
 304
 305         /* Initialize struct reg */
 306         reg->name = reg_desc->name;
 307         reg->size = 32; /* All register in ARC are 32-bit */
 308         reg->value = reg_desc->reg_value;
 309         reg->type = &arc_reg_type;
 310         reg->arch_info = reg_desc;
 311         reg->caller_save = true; /* @todo should be configurable. */
 312         reg->reg_data_type = reg_desc->data_type;
 313         reg->feature = &reg_desc->feature;
 314
 315         reg->feature->name = reg_desc->gdb_xml_feature;
 316
 317         /* reg->number is used by OpenOCD as value for @regnum. Thus when setting
 318          * value of a register GDB will use it as a number of register in
 319          * P-packet. OpenOCD gdbserver will then use number of register in
 320          * P-packet as an array index in the reg_list returned by
 321          * arc_regs_get_gdb_reg_list. So to ensure that registers are assigned
 322          * correctly it would be required to either sort registers in
 323          * arc_regs_get_gdb_reg_list or to assign numbers sequentially here and
 324          * according to how registers will be sorted in
 325          * arc_regs_get_gdb_reg_list. Second options is much more simpler. */
 326         reg->number = number;
 327
 328         if (reg_desc->is_general) {
 329                 arc->last_general_reg = reg->number;
 330                 reg->group = reg_group_general;
 331         } else {
 332                 reg->group = reg_group_other;
 333         }
 334
 335         return ERROR_OK;
 336 }
 337
 338 /* Building aux/core reg_cache */
 339 static int arc_build_reg_cache(struct target *target)
 340 {
 341         unsigned long i = 0;
 342         struct arc_reg_desc *reg_desc;
 343         /* get pointers to arch-specific information */
 344         struct arc_common *arc = target_to_arc(target);
 345         const unsigned long num_regs = arc->num_core_regs + arc->num_aux_regs;
 346         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 347         struct reg_cache *cache = calloc(1, sizeof(*cache));
 348         struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
 349
 350         if (!cache || !reg_list)  {
 351                 LOG_ERROR("Not enough memory");
 352                 goto fail;
 353         }
 354
 355         /* Build the process context cache */
 356         cache->name = "arc registers";
 357         cache->next = NULL;
 358         cache->reg_list = reg_list;
 359         cache->num_regs = num_regs;
 360         arc->core_and_aux_cache = cache;
 361         (*cache_p) = cache;
 362
 363         if (list_empty(&arc->core_reg_descriptions)) {
 364                 LOG_ERROR("No core registers were defined");
 365                 goto fail;
 366         }
 367
 368         list_for_each_entry(reg_desc, &arc->core_reg_descriptions, list) {
 369                 CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
 370
 371                 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
 372                         reg_list[i].name, reg_list[i].group,
 373                         reg_list[i].feature->name);
 374
 375                 i += 1;
 376         }
 377
 378         if (list_empty(&arc->aux_reg_descriptions)) {
 379                 LOG_ERROR("No aux registers were defined");
 380                 goto fail;
 381         }
 382
 383         list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
 384                  CHECK_RETVAL(arc_init_reg(target, &reg_list[i],  reg_desc, i));
 385
 386                 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
 387                         reg_list[i].name, reg_list[i].group,
 388                         reg_list[i].feature->name);
 389
 390                 /* PC and DEBUG are essential so we search for them. */
 391                 if (!strcmp("pc", reg_desc->name)) {
 392                         if (arc->pc_index_in_cache != ULONG_MAX) {
 393                                 LOG_ERROR("Double definition of PC in configuration");
 394                                 goto fail;
 395                         }
 396                         arc->pc_index_in_cache = i;
 397                 } else if (!strcmp("debug", reg_desc->name)) {
 398                         if (arc->debug_index_in_cache != ULONG_MAX) {
 399                                 LOG_ERROR("Double definition of DEBUG in configuration");
 400                                 goto fail;
 401                         }
 402                         arc->debug_index_in_cache = i;
 403                 }
 404                 i += 1;
 405         }
 406
 407         if (arc->pc_index_in_cache == ULONG_MAX
 408                         || arc->debug_index_in_cache == ULONG_MAX) {
 409                 LOG_ERROR("`pc' and `debug' registers must be present in target description.");
 410                 goto fail;
 411         }
 412
 413         assert(i == (arc->num_core_regs + arc->num_aux_regs));
 414
 415         arc->core_aux_cache_built = true;
 416
 417         return ERROR_OK;
 418
 419 fail:
 420         free(cache);
 421         free(reg_list);
 422
 423         return ERROR_FAIL;
 424 }
 425
 426 /* Build bcr reg_cache.
 427  * This function must be called only after arc_build_reg_cache */
 428 static int arc_build_bcr_reg_cache(struct target *target)
 429 {
 430         /* get pointers to arch-specific information */
 431         struct arc_common *arc = target_to_arc(target);
 432         const unsigned long num_regs = arc->num_bcr_regs;
 433         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 434         struct reg_cache *cache = malloc(sizeof(*cache));
 435         struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
 436
 437         struct arc_reg_desc *reg_desc;
 438         unsigned long i = 0;
 439         unsigned long gdb_regnum = arc->core_and_aux_cache->num_regs;
 440
 441         if (!cache || !reg_list)  {
 442                 LOG_ERROR("Unable to allocate memory");
 443                 goto fail;
 444         }
 445
 446         /* Build the process context cache */
 447         cache->name = "arc.bcr";
 448         cache->next = NULL;
 449         cache->reg_list = reg_list;
 450         cache->num_regs = num_regs;
 451         arc->bcr_cache = cache;
 452         (*cache_p) = cache;
 453
 454         if (list_empty(&arc->bcr_reg_descriptions)) {
 455                 LOG_ERROR("No BCR registers are defined");
 456                 goto fail;
 457         }
 458
 459         list_for_each_entry(reg_desc, &arc->bcr_reg_descriptions, list) {
 460                  CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, gdb_regnum));
 461                 /* BCRs always semantically, they are just read-as-zero, if there is
 462                  * not real register. */
 463                 reg_list[i].exist = true;
 464
 465                 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
 466                         reg_list[i].name, reg_list[i].group,
 467                         reg_list[i].feature->name);
 468                 i += 1;
 469                 gdb_regnum += 1;
 470         }
 471
 472         assert(i == arc->num_bcr_regs);
 473
 474         arc->bcr_cache_built = true;
 475
 476
 477         return ERROR_OK;
 478 fail:
 479         free(cache);
 480         free(reg_list);
 481
 482         return ERROR_FAIL;
 483 }
 484
 485
 486 static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 487         int *reg_list_size, enum target_register_class reg_class)
 488 {
 489         assert(target->reg_cache);
 490         struct arc_common *arc = target_to_arc(target);
 491
 492         /* get pointers to arch-specific information storage */
 493         *reg_list_size = arc->num_regs;
 494         *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
 495
 496         if (!*reg_list) {
 497                 LOG_ERROR("Unable to allocate memory");
 498                 return ERROR_FAIL;
 499         }
 500
 501         /* OpenOCD gdb_server API seems to be inconsistent here: when it generates
 502          * XML tdesc it filters out !exist registers, however when creating a
 503          * g-packet it doesn't do so. REG_CLASS_ALL is used in first case, and
 504          * REG_CLASS_GENERAL used in the latter one. Due to this we had to filter
 505          * out !exist register for "general", but not for "all". Attempts to filter out
 506          * !exist for "all" as well will cause a failed check in OpenOCD GDB
 507          * server. */
 508         if (reg_class == REG_CLASS_ALL) {
 509                 unsigned long i = 0;
 510                 struct reg_cache *reg_cache = target->reg_cache;
 511                 while (reg_cache) {
 512                         for (unsigned j = 0; j < reg_cache->num_regs; j++, i++)
 513                                 (*reg_list)[i] =  &reg_cache->reg_list[j];
 514                         reg_cache = reg_cache->next;
 515                 }
 516                 assert(i == arc->num_regs);
 517                 LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size);
 518         } else {
 519                 unsigned long i = 0;
 520                 unsigned long gdb_reg_number = 0;
 521                 struct reg_cache *reg_cache = target->reg_cache;
 522                 while (reg_cache) {
 523                         for (unsigned j = 0;
 524                                  j < reg_cache->num_regs && gdb_reg_number <= arc->last_general_reg;
 525                                  j++) {
 526                                 if (reg_cache->reg_list[j].exist) {
 527                                         (*reg_list)[i] =  &reg_cache->reg_list[j];
 528                                         i++;
 529                                 }
 530                                 gdb_reg_number += 1;
 531                         }
 532                         reg_cache = reg_cache->next;
 533                 }
 534                 *reg_list_size = i;
 535                 LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
 536         }
 537
 538         return ERROR_OK;
 539 }
 540
 541 /* Reading field of struct_type register */
 542 int arc_reg_get_field(struct target *target, const char *reg_name,
 543                 const char *field_name, uint32_t *value_ptr)
 544 {
 545         struct reg_data_type_struct_field *field;
 546
 547         LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
 548
 549         /* Get register */
 550         struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
 551
 552         if (!reg) {
 553                 LOG_ERROR("Requested register `%s' doesn't exist.", reg_name);
 554                 return ERROR_ARC_REGISTER_NOT_FOUND;
 555         }
 556
 557         if (reg->reg_data_type->type != REG_TYPE_ARCH_DEFINED
 558             || reg->reg_data_type->type_class != REG_TYPE_CLASS_STRUCT)
 559                 return ERROR_ARC_REGISTER_IS_NOT_STRUCT;
 560
 561         /* Get field in a register */
 562         struct reg_data_type_struct *reg_struct =
 563                 reg->reg_data_type->reg_type_struct;
 564         for (field = reg_struct->fields;
 565              field;
 566              field = field->next) {
 567                 if (!strcmp(field->name, field_name))
 568                         break;
 569         }
 570
 571         if (!field)
 572                 return ERROR_ARC_REGISTER_FIELD_NOT_FOUND;
 573
 574         if (!field->use_bitfields)
 575                 return ERROR_ARC_FIELD_IS_NOT_BITFIELD;
 576
 577         if (!reg->valid)
 578                 CHECK_RETVAL(reg->type->get(reg));
 579
 580         /* First do endianness-safe read of register value
 581          * then convert it to binary buffer for further
 582          * field extraction */
 583
 584         *value_ptr = buf_get_u32(reg->value, field->bitfield->start,
 585                 field->bitfield->end - field->bitfield->start + 1);
 586
 587         return ERROR_OK;
 588 }
 589
 590 static int arc_get_register_value(struct target *target, const char *reg_name,
 591                 uint32_t *value_ptr)
 592 {
 593         LOG_DEBUG("reg_name=%s", reg_name);
 594
 595         struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
 596
 597         if (!reg)
 598                 return ERROR_ARC_REGISTER_NOT_FOUND;
 599
 600         if (!reg->valid)
 601                 CHECK_RETVAL(reg->type->get(reg));
 602
 603         *value_ptr = target_buffer_get_u32(target, reg->value);
 604
 605         return ERROR_OK;
 606 }
 607
 608 static int arc_set_register_value(struct target *target, const char *reg_name,
 609                 uint32_t value)
 610 {
 611         LOG_DEBUG("reg_name=%s value=0x%08" PRIx32, reg_name, value);
 612
 613         if (!(target && reg_name)) {
 614                 LOG_ERROR("Arguments cannot be NULL.");
 615                 return ERROR_FAIL;
 616         }
 617
 618         struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
 619
 620         if (!reg)
 621                 return ERROR_ARC_REGISTER_NOT_FOUND;
 622
 623         uint8_t value_buf[4];
 624         buf_set_u32(value_buf, 0, 32, value);
 625         CHECK_RETVAL(reg->type->set(reg, value_buf));
 626
 627         return ERROR_OK;
 628 }
 629
 630 /* Configure DCCM's */
 631 static int arc_configure_dccm(struct target  *target)
 632 {
 633         struct arc_common *arc = target_to_arc(target);
 634
 635         uint32_t dccm_build_version, dccm_build_size0, dccm_build_size1;
 636         CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "version",
 637                 &dccm_build_version));
 638         CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size0",
 639                 &dccm_build_size0));
 640         CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size1",
 641                 &dccm_build_size1));
 642         /* There is no yet support of configurable number of cycles,
 643          * So there is no difference between v3 and v4 */
 644         if ((dccm_build_version == 3 || dccm_build_version == 4) && dccm_build_size0 > 0) {
 645                 CHECK_RETVAL(arc_get_register_value(target, "aux_dccm", &(arc->dccm_start)));
 646                 uint32_t dccm_size = 0x100;
 647                 dccm_size <<= dccm_build_size0;
 648                 if (dccm_build_size0 == 0xF)
 649                         dccm_size <<= dccm_build_size1;
 650                 arc->dccm_end = arc->dccm_start + dccm_size;
 651                 LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
 652                                 arc->dccm_start, arc->dccm_end);
 653
 654         }
 655         return ERROR_OK;
 656 }
 657
 658
 659 /* Configure ICCM's */
 660
 661 static int arc_configure_iccm(struct target  *target)
 662 {
 663         struct arc_common *arc = target_to_arc(target);
 664
 665         /* ICCM0 */
 666         uint32_t iccm_build_version, iccm_build_size00, iccm_build_size01;
 667         uint32_t aux_iccm = 0;
 668         CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "version",
 669                 &iccm_build_version));
 670         CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size0",
 671                 &iccm_build_size00));
 672         CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size1",
 673                 &iccm_build_size01));
 674         if (iccm_build_version == 4 && iccm_build_size00 > 0) {
 675                 CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
 676                 uint32_t iccm0_size = 0x100;
 677                 iccm0_size <<= iccm_build_size00;
 678                 if (iccm_build_size00 == 0xF)
 679                         iccm0_size <<= iccm_build_size01;
 680                 /* iccm0 start is located in highest 4 bits of aux_iccm */
 681                 arc->iccm0_start = aux_iccm & 0xF0000000;
 682                 arc->iccm0_end = arc->iccm0_start + iccm0_size;
 683                 LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
 684                                 arc->iccm0_start, arc->iccm0_end);
 685         }
 686
 687         /* ICCM1 */
 688         uint32_t iccm_build_size10, iccm_build_size11;
 689         CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size0",
 690                 &iccm_build_size10));
 691         CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size1",
 692                 &iccm_build_size11));
 693         if (iccm_build_version == 4 && iccm_build_size10 > 0) {
 694                 /* Use value read for ICCM0 */
 695                 if (!aux_iccm)
 696                         CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
 697                 uint32_t iccm1_size = 0x100;
 698                 iccm1_size <<= iccm_build_size10;
 699                 if (iccm_build_size10 == 0xF)
 700                         iccm1_size <<= iccm_build_size11;
 701                 arc->iccm1_start = aux_iccm & 0x0F000000;
 702                 arc->iccm1_end = arc->iccm1_start + iccm1_size;
 703                 LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
 704                                 arc->iccm1_start, arc->iccm1_end);
 705         }
 706         return ERROR_OK;
 707 }
 708
 709 /* Configure some core features, depending on BCRs. */
 710 static int arc_configure(struct target *target)
 711 {
 712         LOG_DEBUG("Configuring ARC ICCM and DCCM");
 713
 714         /* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
 715         if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
 716             arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
 717                                 CHECK_RETVAL(arc_configure_dccm(target));
 718
 719         /* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
 720         if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) &&
 721             arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
 722                                 CHECK_RETVAL(arc_configure_iccm(target));
 723
 724         return ERROR_OK;
 725 }
 726
 727 /* arc_examine is function, which is used for all arc targets*/
 728 static int arc_examine(struct target *target)
 729 {
 730         uint32_t status;
 731         struct arc_common *arc = target_to_arc(target);
 732
 733         CHECK_RETVAL(arc_jtag_startup(&arc->jtag_info));
 734
 735         if (!target_was_examined(target)) {
 736                 CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
 737                 if (status & ARC_JTAG_STAT_RU)
 738                         target->state = TARGET_RUNNING;
 739                 else
 740                         target->state = TARGET_HALTED;
 741
 742                 /* Read BCRs and configure optional registers. */
 743                 CHECK_RETVAL(arc_configure(target));
 744
 745                 target_set_examined(target);
 746         }
 747
 748         return ERROR_OK;
 749 }
 750
 751 static int arc_halt(struct target *target)
 752 {
 753         uint32_t value, irq_state;
 754         struct arc_common *arc = target_to_arc(target);
 755
 756         LOG_DEBUG("target->state: %s", target_state_name(target));
 757
 758         if (target->state == TARGET_HALTED) {
 759                 LOG_DEBUG("target was already halted");
 760                 return ERROR_OK;
 761         }
 762
 763         if (target->state == TARGET_UNKNOWN)
 764                 LOG_WARNING("target was in unknown state when halt was requested");
 765
 766         if (target->state == TARGET_RESET) {
 767                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 768                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 769                         return ERROR_TARGET_FAILURE;
 770                 } else {
 771                         target->debug_reason = DBG_REASON_DBGRQ;
 772                 }
 773         }
 774
 775         /* Break (stop) processor.
 776          * Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally.
 777          * We do not use here arc_get/set_core_reg functions here because they imply
 778          * that the processor is already halted. */
 779         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, &value));
 780         value |= SET_CORE_FORCE_HALT; /* set the HALT bit */
 781         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value));
 782         alive_sleep(1);
 783
 784         /* Save current IRQ state */
 785         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &irq_state));
 786
 787         if (irq_state & AUX_STATUS32_REG_IE_BIT)
 788                 arc->irq_state = 1;
 789         else
 790                 arc->irq_state = 0;
 791
 792         /* update state and notify gdb*/
 793         target->state = TARGET_HALTED;
 794         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 795
 796         /* some more debug information */
 797         if (debug_level >= LOG_LVL_DEBUG) {
 798                 LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
 799                 CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
 800                 LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
 801         }
 802
 803         return ERROR_OK;
 804 }
 805
 806 /**
 807  * Read registers that are used in GDB g-packet. We don't read them one-by-one,
 808  * but do that in one batch operation to improve speed. Calls to JTAG layer are
 809  * expensive so it is better to make one big call that reads all necessary
 810  * registers, instead of many calls, one for one register.
 811  */
 812 static int arc_save_context(struct target *target)
 813 {
 814         int retval = ERROR_OK;
 815         unsigned int i;
 816         struct arc_common *arc = target_to_arc(target);
 817         struct reg *reg_list = arc->core_and_aux_cache->reg_list;
 818
 819         LOG_DEBUG("Saving aux and core registers values");
 820         assert(reg_list);
 821
 822         /* It is assumed that there is at least one AUX register in the list, for
 823          * example PC. */
 824         const uint32_t core_regs_size = arc->num_core_regs * sizeof(uint32_t);
 825         /* last_general_reg is inclusive number. To get count of registers it is
 826          * required to do +1. */
 827         const uint32_t regs_to_scan =
 828                 MIN(arc->last_general_reg + 1, arc->num_regs);
 829         const uint32_t aux_regs_size = arc->num_aux_regs * sizeof(uint32_t);
 830         uint32_t *core_values = malloc(core_regs_size);
 831         uint32_t *aux_values = malloc(aux_regs_size);
 832         uint32_t *core_addrs = malloc(core_regs_size);
 833         uint32_t *aux_addrs = malloc(aux_regs_size);
 834         unsigned int core_cnt = 0;
 835         unsigned int aux_cnt = 0;
 836
 837         if (!core_values || !core_addrs || !aux_values || !aux_addrs)  {
 838                 LOG_ERROR("Unable to allocate memory");
 839                 retval = ERROR_FAIL;
 840                 goto exit;
 841         }
 842
 843         memset(core_values, 0xff, core_regs_size);
 844         memset(core_addrs, 0xff, core_regs_size);
 845         memset(aux_values, 0xff, aux_regs_size);
 846         memset(aux_addrs, 0xff, aux_regs_size);
 847
 848         for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) {
 849                 struct reg *reg = &(reg_list[i]);
 850                 struct arc_reg_desc *arc_reg = reg->arch_info;
 851                 if (!reg->valid && reg->exist) {
 852                         core_addrs[core_cnt] = arc_reg->arch_num;
 853                         core_cnt += 1;
 854                 }
 855         }
 856
 857         for (i = arc->num_core_regs; i < regs_to_scan; i++) {
 858                 struct reg *reg = &(reg_list[i]);
 859                 struct arc_reg_desc *arc_reg = reg->arch_info;
 860                 if (!reg->valid && reg->exist) {
 861                         aux_addrs[aux_cnt] = arc_reg->arch_num;
 862                         aux_cnt += 1;
 863                 }
 864         }
 865
 866         /* Read data from target. */
 867         if (core_cnt > 0) {
 868                 retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
 869                 if (ERROR_OK != retval) {
 870                         LOG_ERROR("Attempt to read core registers failed.");
 871                         retval = ERROR_FAIL;
 872                         goto exit;
 873                 }
 874         }
 875         if (aux_cnt > 0) {
 876                 retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
 877                 if (ERROR_OK != retval) {
 878                         LOG_ERROR("Attempt to read aux registers failed.");
 879                         retval = ERROR_FAIL;
 880                         goto exit;
 881                 }
 882         }
 883
 884         /* Parse core regs */
 885         core_cnt = 0;
 886         for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) {
 887                 struct reg *reg = &(reg_list[i]);
 888                 struct arc_reg_desc *arc_reg = reg->arch_info;
 889                 if (!reg->valid && reg->exist) {
 890                         target_buffer_set_u32(target, reg->value, core_values[core_cnt]);
 891                         core_cnt += 1;
 892                         reg->valid = true;
 893                         reg->dirty = false;
 894                         LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
 895                                 i, arc_reg->name, core_values[core_cnt]);
 896                 }
 897         }
 898
 899         /* Parse aux regs */
 900         aux_cnt = 0;
 901         for (i = arc->num_core_regs; i < regs_to_scan; i++) {
 902                 struct reg *reg = &(reg_list[i]);
 903                 struct arc_reg_desc *arc_reg = reg->arch_info;
 904                 if (!reg->valid && reg->exist) {
 905                         target_buffer_set_u32(target, reg->value, aux_values[aux_cnt]);
 906                         aux_cnt += 1;
 907                         reg->valid = true;
 908                         reg->dirty = false;
 909                         LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
 910                                 i, arc_reg->name, aux_values[aux_cnt]);
 911                 }
 912         }
 913
 914 exit:
 915         free(core_values);
 916         free(core_addrs);
 917         free(aux_values);
 918         free(aux_addrs);
 919
 920         return retval;
 921 }
 922
 923 /**
 924  * Finds an actionpoint that triggered last actionpoint event, as specified by
 925  * DEBUG.ASR.
 926  *
 927  * @param actionpoint Pointer to be set to last active actionpoint. Pointer
 928  *                    will be set to NULL if DEBUG.AH is 0.
 929  */
 930 static int get_current_actionpoint(struct target *target,
 931                 struct arc_actionpoint **actionpoint)
 932 {
 933         assert(target != NULL);
 934         assert(actionpoint != NULL);
 935
 936         uint32_t debug_ah;
 937         /* Check if actionpoint caused halt */
 938         CHECK_RETVAL(arc_reg_get_field(target, "debug", "ah",
 939                                 &debug_ah));
 940
 941         if (debug_ah) {
 942                 struct arc_common *arc = target_to_arc(target);
 943                 unsigned int ap;
 944                 uint32_t debug_asr;
 945                 CHECK_RETVAL(arc_reg_get_field(target, "debug",
 946                                         "asr", &debug_asr));
 947
 948                 for (ap = 0; debug_asr > 1; debug_asr >>= 1)
 949                         ap += 1;
 950
 951                 assert(ap < arc->actionpoints_num);
 952
 953                 *actionpoint = &(arc->actionpoints_list[ap]);
 954         } else {
 955                 *actionpoint = NULL;
 956         }
 957
 958         return ERROR_OK;
 959 }
 960
 961 static int arc_examine_debug_reason(struct target *target)
 962 {
 963         uint32_t debug_bh;
 964
 965         /* Only check for reason if don't know it already. */
 966         /* BTW After singlestep at this point core is not marked as halted, so
 967          * reading from memory to get current instruction wouldn't work anyway.  */
 968         if (target->debug_reason == DBG_REASON_DBGRQ ||
 969             target->debug_reason == DBG_REASON_SINGLESTEP) {
 970                 return ERROR_OK;
 971         }
 972
 973         CHECK_RETVAL(arc_reg_get_field(target, "debug", "bh",
 974                                 &debug_bh));
 975
 976         if (debug_bh) {
 977                 /* DEBUG.BH is set if core halted due to BRK instruction.  */
 978                 target->debug_reason = DBG_REASON_BREAKPOINT;
 979         } else {
 980                 struct arc_actionpoint *actionpoint = NULL;
 981                 CHECK_RETVAL(get_current_actionpoint(target, &actionpoint));
 982
 983                 if (actionpoint != NULL) {
 984                         if (!actionpoint->used)
 985                                 LOG_WARNING("Target halted by an unused actionpoint.");
 986
 987                         if (actionpoint->type == ARC_AP_BREAKPOINT)
 988                                 target->debug_reason = DBG_REASON_BREAKPOINT;
 989                         else if (actionpoint->type == ARC_AP_WATCHPOINT)
 990                                 target->debug_reason = DBG_REASON_WATCHPOINT;
 991                         else
 992                                 LOG_WARNING("Unknown type of actionpoint.");
 993                 }
 994         }
 995
 996         return ERROR_OK;
 997 }
 998
 999 static int arc_debug_entry(struct target *target)
1000 {
1001         CHECK_RETVAL(arc_save_context(target));
1002
1003         /* TODO: reset internal indicators of caches states, otherwise D$/I$
1004          * will not be flushed/invalidated when required. */
1005         CHECK_RETVAL(arc_reset_caches_states(target));
1006         CHECK_RETVAL(arc_examine_debug_reason(target));
1007
1008         return ERROR_OK;
1009 }
1010
1011 static int arc_poll(struct target *target)
1012 {
1013         uint32_t status, value;
1014         struct arc_common *arc = target_to_arc(target);
1015
1016         /* gdb calls continuously through this arc_poll() function  */
1017         CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
1018
1019         /* check for processor halted */
1020         if (status & ARC_JTAG_STAT_RU) {
1021                 if (target->state != TARGET_RUNNING) {
1022                         LOG_WARNING("target is still running!");
1023                         target->state = TARGET_RUNNING;
1024                 }
1025                 return ERROR_OK;
1026         }
1027         /* In some cases JTAG status register indicates that
1028          *  processor is in halt mode, but processor is still running.
1029          *  We check halt bit of AUX STATUS32 register for setting correct state. */
1030         if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
1031                 CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
1032                 if (value & AUX_STATUS32_REG_HALT_BIT) {
1033                         LOG_DEBUG("ARC core in halt or reset state.");
1034                         /* Save context if target was not in reset state */
1035                         if (target->state == TARGET_RUNNING)
1036                                 CHECK_RETVAL(arc_debug_entry(target));
1037                         target->state = TARGET_HALTED;
1038                         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1039                 } else {
1040                 LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
1041                                                 "target is still running");
1042                 }
1043
1044         } else if (target->state == TARGET_DEBUG_RUNNING) {
1045
1046                 target->state = TARGET_HALTED;
1047                 LOG_DEBUG("ARC core is in debug running mode");
1048
1049                 CHECK_RETVAL(arc_debug_entry(target));
1050
1051                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED));
1052         }
1053
1054         return ERROR_OK;
1055 }
1056
1057 static int arc_assert_reset(struct target *target)
1058 {
1059         struct arc_common *arc = target_to_arc(target);
1060         enum reset_types jtag_reset_config = jtag_get_reset_config();
1061         bool srst_asserted = false;
1062
1063         LOG_DEBUG("target->state: %s", target_state_name(target));
1064
1065         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1066                 /* allow scripts to override the reset event */
1067
1068                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1069                 register_cache_invalidate(arc->core_and_aux_cache);
1070                  /* An ARC target might be in halt state after reset, so
1071                  * if script requested processor to resume, then it must
1072                  * be manually started to ensure that this request
1073                  * is satisfied. */
1074                 if (target->state == TARGET_HALTED && !target->reset_halt) {
1075                         /* Resume the target and continue from the current
1076                          * PC register value. */
1077                         LOG_DEBUG("Starting CPU execution after reset");
1078                         CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
1079                 }
1080                 target->state = TARGET_RESET;
1081
1082                 return ERROR_OK;
1083         }
1084
1085         /* some cores support connecting while srst is asserted
1086          * use that mode if it has been configured */
1087         if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
1088                         (jtag_reset_config & RESET_SRST_NO_GATING)) {
1089                 jtag_add_reset(0, 1);
1090                 srst_asserted = true;
1091         }
1092
1093         if (jtag_reset_config & RESET_HAS_SRST) {
1094                 /* should issue a srst only, but we may have to assert trst as well */
1095                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1096                         jtag_add_reset(1, 1);
1097                 else if (!srst_asserted)
1098                         jtag_add_reset(0, 1);
1099         }
1100
1101         target->state = TARGET_RESET;
1102         jtag_add_sleep(50000);
1103
1104         register_cache_invalidate(arc->core_and_aux_cache);
1105
1106         if (target->reset_halt)
1107                 CHECK_RETVAL(target_halt(target));
1108
1109         return ERROR_OK;
1110 }
1111
1112 static int arc_deassert_reset(struct target *target)
1113 {
1114         LOG_DEBUG("target->state: %s", target_state_name(target));
1115
1116         /* deassert reset lines */
1117         jtag_add_reset(0, 0);
1118
1119         return ERROR_OK;
1120 }
1121
1122 static int arc_arch_state(struct target *target)
1123 {
1124         uint32_t pc_value;
1125
1126         if (debug_level < LOG_LVL_DEBUG)
1127                 return ERROR_OK;
1128
1129         CHECK_RETVAL(arc_get_register_value(target, "pc", &pc_value));
1130
1131         LOG_DEBUG("target state: %s;  PC at: 0x%08" PRIx32,
1132                 target_state_name(target),
1133                 pc_value);
1134
1135         return ERROR_OK;
1136 }
1137
1138 /**
1139  * See arc_save_context() for reason why we want to dump all regs at once.
1140  * This however means that if there are dependencies between registers they
1141  * will not be observable until target will be resumed.
1142  */
1143 static int arc_restore_context(struct target *target)
1144 {
1145         int retval = ERROR_OK;
1146         unsigned int i;
1147         struct arc_common *arc = target_to_arc(target);
1148         struct reg *reg_list = arc->core_and_aux_cache->reg_list;
1149
1150         LOG_DEBUG("Restoring registers values");
1151         assert(reg_list);
1152
1153         const uint32_t core_regs_size = arc->num_core_regs  * sizeof(uint32_t);
1154         const uint32_t aux_regs_size =  arc->num_aux_regs * sizeof(uint32_t);
1155         uint32_t *core_values = malloc(core_regs_size);
1156         uint32_t *aux_values = malloc(aux_regs_size);
1157         uint32_t *core_addrs = malloc(core_regs_size);
1158         uint32_t *aux_addrs = malloc(aux_regs_size);
1159         unsigned int core_cnt = 0;
1160         unsigned int aux_cnt = 0;
1161
1162         if (!core_values || !core_addrs || !aux_values || !aux_addrs)  {
1163                 LOG_ERROR("Unable to allocate memory");
1164                 retval = ERROR_FAIL;
1165                 goto exit;
1166         }
1167
1168         memset(core_values, 0xff, core_regs_size);
1169         memset(core_addrs, 0xff, core_regs_size);
1170         memset(aux_values, 0xff, aux_regs_size);
1171         memset(aux_addrs, 0xff, aux_regs_size);
1172
1173         for (i = 0; i < arc->num_core_regs; i++) {
1174                 struct reg *reg = &(reg_list[i]);
1175                 struct arc_reg_desc *arc_reg = reg->arch_info;
1176                 if (reg->valid && reg->exist && reg->dirty) {
1177                         LOG_DEBUG("Will write regnum=%u", i);
1178                         core_addrs[core_cnt] = arc_reg->arch_num;
1179                         core_values[core_cnt] = target_buffer_get_u32(target, reg->value);
1180                         core_cnt += 1;
1181                 }
1182         }
1183
1184         for (i = 0; i < arc->num_aux_regs; i++) {
1185                 struct reg *reg = &(reg_list[arc->num_core_regs + i]);
1186                 struct arc_reg_desc *arc_reg = reg->arch_info;
1187                 if (reg->valid && reg->exist && reg->dirty) {
1188                         LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i);
1189                         aux_addrs[aux_cnt] = arc_reg->arch_num;
1190                         aux_values[aux_cnt] = target_buffer_get_u32(target, reg->value);
1191                         aux_cnt += 1;
1192                 }
1193         }
1194
1195         /* Write data to target.
1196          * Check before write, if aux and core count is greater than 0. */
1197         if (core_cnt > 0) {
1198                 retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
1199                 if (ERROR_OK != retval) {
1200                         LOG_ERROR("Attempt to write to core registers failed.");
1201                         retval = ERROR_FAIL;
1202                         goto exit;
1203                 }
1204         }
1205
1206         if (aux_cnt > 0) {
1207                 retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
1208                 if (ERROR_OK != retval) {
1209                         LOG_ERROR("Attempt to write to aux registers failed.");
1210                         retval = ERROR_FAIL;
1211                         goto exit;
1212                 }
1213         }
1214
1215 exit:
1216         free(core_values);
1217         free(core_addrs);
1218         free(aux_values);
1219         free(aux_addrs);
1220
1221         return retval;
1222 }
1223
1224 static int arc_enable_interrupts(struct target *target, int enable)
1225 {
1226         uint32_t value;
1227
1228         struct arc_common *arc = target_to_arc(target);
1229
1230         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
1231
1232         if (enable) {
1233                 /* enable interrupts */
1234                 value |= SET_CORE_ENABLE_INTERRUPTS;
1235                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1236                 LOG_DEBUG("interrupts enabled");
1237         } else {
1238                 /* disable interrupts */
1239                 value &= ~SET_CORE_ENABLE_INTERRUPTS;
1240                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1241                 LOG_DEBUG("interrupts disabled");
1242         }
1243
1244         return ERROR_OK;
1245 }
1246
1247 static int arc_resume(struct target *target, int current, target_addr_t address,
1248         int handle_breakpoints, int debug_execution)
1249 {
1250         struct arc_common *arc = target_to_arc(target);
1251         uint32_t resume_pc = 0;
1252         uint32_t value;
1253         struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache];
1254
1255         LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints(not supported yet):%i,"
1256                 " debug_execution:%i", current, address, handle_breakpoints, debug_execution);
1257
1258         /* We need to reset ARC cache variables so caches
1259          * would be invalidated and actual data
1260          * would be fetched from memory. */
1261         CHECK_RETVAL(arc_reset_caches_states(target));
1262
1263         if (target->state != TARGET_HALTED) {
1264                 LOG_WARNING("target not halted");
1265                 return ERROR_TARGET_NOT_HALTED;
1266         }
1267
1268         /* current = 1: continue on current PC, otherwise continue at <address> */
1269         if (!current) {
1270                 target_buffer_set_u32(target, pc->value, address);
1271                 pc->dirty = 1;
1272                 pc->valid = 1;
1273                 LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
1274         }
1275
1276         if (!current)
1277                 resume_pc = address;
1278         else
1279                 resume_pc = target_buffer_get_u32(target, pc->value);
1280
1281         CHECK_RETVAL(arc_restore_context(target));
1282
1283         LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
1284                 resume_pc, pc->dirty, pc->valid);
1285
1286         /* check if GDB tells to set our PC where to continue from */
1287         if ((pc->valid == 1) && (resume_pc == target_buffer_get_u32(target, pc->value))) {
1288                 value = target_buffer_get_u32(target, pc->value);
1289                 LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
1290                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
1291         }
1292
1293         /* Restore IRQ state if not in debug_execution*/
1294         if (!debug_execution)
1295                 CHECK_RETVAL(arc_enable_interrupts(target, arc->irq_state));
1296         else
1297                 CHECK_RETVAL(arc_enable_interrupts(target, !debug_execution));
1298
1299         target->debug_reason = DBG_REASON_NOTHALTED;
1300
1301         /* ready to get us going again */
1302         target->state = TARGET_RUNNING;
1303         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
1304         value &= ~SET_CORE_HALT_BIT;        /* clear the HALT bit */
1305         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1306         LOG_DEBUG("Core started to run");
1307
1308         /* registers are now invalid */
1309         register_cache_invalidate(arc->core_and_aux_cache);
1310
1311         if (!debug_execution) {
1312                 target->state = TARGET_RUNNING;
1313                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
1314                 LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc);
1315         } else {
1316                 target->state = TARGET_DEBUG_RUNNING;
1317                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED));
1318                 LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc);
1319         }
1320
1321         return ERROR_OK;
1322 }
1323
1324 static int arc_init_target(struct command_context *cmd_ctx, struct target *target)
1325 {
1326         CHECK_RETVAL(arc_build_reg_cache(target));
1327         CHECK_RETVAL(arc_build_bcr_reg_cache(target));
1328         target->debug_reason = DBG_REASON_DBGRQ;
1329         return ERROR_OK;
1330 }
1331
1332 static void arc_free_reg_cache(struct reg_cache *cache)
1333 {
1334         free(cache->reg_list);
1335         free(cache);
1336 }
1337
1338 static void arc_deinit_target(struct target *target)
1339 {
1340         struct arc_common *arc = target_to_arc(target);
1341
1342         LOG_DEBUG("deinitialization of target");
1343         if (arc->core_aux_cache_built)
1344                 arc_free_reg_cache(arc->core_and_aux_cache);
1345         if (arc->bcr_cache_built)
1346                 arc_free_reg_cache(arc->bcr_cache);
1347
1348         struct arc_reg_data_type *type, *n;
1349         struct arc_reg_desc *desc, *k;
1350
1351         /* Free arc-specific reg_data_types allocations*/
1352         list_for_each_entry_safe_reverse(type, n, &arc->reg_data_types, list) {
1353                 if (type->data_type.type_class == REG_TYPE_CLASS_STRUCT) {
1354                         free(type->reg_type_struct_field);
1355                         free(type->bitfields);
1356                         free(type);
1357                 }       else if (type->data_type.type_class == REG_TYPE_CLASS_FLAGS) {
1358                         free(type->reg_type_flags_field);
1359                         free(type->bitfields);
1360                         free(type);
1361                 }
1362         }
1363
1364         /* Free standard_gdb_types reg_data_types allocations */
1365         type = list_first_entry(&arc->reg_data_types, struct arc_reg_data_type, list);
1366         free(type);
1367
1368         list_for_each_entry_safe(desc, k, &arc->aux_reg_descriptions, list)
1369                 free_reg_desc(desc);
1370
1371         list_for_each_entry_safe(desc, k, &arc->core_reg_descriptions, list)
1372                 free_reg_desc(desc);
1373
1374         list_for_each_entry_safe(desc, k, &arc->bcr_reg_descriptions, list)
1375                 free_reg_desc(desc);
1376
1377         free(arc->actionpoints_list);
1378         free(arc);
1379 }
1380
1381
1382 static int arc_target_create(struct target *target, Jim_Interp *interp)
1383 {
1384         struct arc_common *arc = calloc(1, sizeof(*arc));
1385
1386         if (!arc) {
1387                 LOG_ERROR("Unable to allocate memory");
1388                 return ERROR_FAIL;
1389         }
1390
1391         LOG_DEBUG("Entering");
1392         CHECK_RETVAL(arc_init_arch_info(target, arc, target->tap));
1393
1394         return ERROR_OK;
1395 }
1396
1397 /**
1398  * Write 4-byte instruction to memory. This is like target_write_u32, however
1399  * in case of little endian ARC instructions are in middle endian format, not
1400  * little endian, so different type of conversion should be done.
1401  * Middle endian: instruction "aabbccdd", stored as "bbaaddcc"
1402  */
1403 int arc_write_instruction_u32(struct target *target, uint32_t address,
1404         uint32_t instr)
1405 {
1406         uint8_t value_buf[4];
1407         if (!target_was_examined(target)) {
1408                 LOG_ERROR("Target not examined yet");
1409                 return ERROR_FAIL;
1410         }
1411
1412         LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
1413                 instr);
1414
1415         if (target->endianness == TARGET_LITTLE_ENDIAN)
1416                 arc_h_u32_to_me(value_buf, instr);
1417         else
1418                 h_u32_to_be(value_buf, instr);
1419
1420         CHECK_RETVAL(target_write_buffer(target, address, 4, value_buf));
1421
1422         return ERROR_OK;
1423 }
1424
1425 /**
1426  * Read 32-bit instruction from memory. It is like target_read_u32, however in
1427  * case of little endian ARC instructions are in middle endian format, so
1428  * different type of conversion should be done.
1429  */
1430 int arc_read_instruction_u32(struct target *target, uint32_t address,
1431                 uint32_t *value)
1432 {
1433         uint8_t value_buf[4];
1434
1435         if (!target_was_examined(target)) {
1436                 LOG_ERROR("Target not examined yet");
1437                 return ERROR_FAIL;
1438         }
1439
1440         *value = 0;
1441         CHECK_RETVAL(target_read_buffer(target, address, 4, value_buf));
1442
1443         if (target->endianness == TARGET_LITTLE_ENDIAN)
1444                 *value = arc_me_to_h_u32(value_buf);
1445         else
1446                 *value = be_to_h_u32(value_buf);
1447
1448         LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
1449                 *value);
1450
1451         return ERROR_OK;
1452 }
1453
1454 /* Actionpoint mechanism allows to setup HW breakpoints
1455  * and watchpoints. Each actionpoint is controlled by
1456  * 3 aux registers: Actionpoint(AP) match mask(AP_AMM), AP match value(AP_AMV)
1457  * and AP control(AC).
1458  * This function is for setting/unsetting actionpoints:
1459  * at - actionpoint target: trigger on mem/reg access
1460  * tt - transaction type : trigger on r/w. */
1461 static int arc_configure_actionpoint(struct target *target, uint32_t ap_num,
1462         uint32_t match_value, uint32_t control_tt, uint32_t control_at)
1463 {
1464         struct arc_common *arc = target_to_arc(target);
1465
1466         if (control_tt != AP_AC_TT_DISABLE) {
1467
1468                 if (arc->actionpoints_num_avail < 1) {
1469                         LOG_ERROR("No free actionpoints, maximim amount is %u",
1470                                         arc->actionpoints_num);
1471                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1472                 }
1473
1474                 /* Names of register to set - 24 chars should be enough. Looks a little
1475                  * bit out-of-place for C code, but makes it aligned to the bigger
1476                  * concept of "ARC registers are defined in TCL" as far as possible.
1477                  */
1478                 char ap_amv_reg_name[24], ap_amm_reg_name[24], ap_ac_reg_name[24];
1479                 snprintf(ap_amv_reg_name, 24, "ap_amv%" PRIu32, ap_num);
1480                 snprintf(ap_amm_reg_name, 24, "ap_amm%" PRIu32, ap_num);
1481                 snprintf(ap_ac_reg_name, 24, "ap_ac%" PRIu32, ap_num);
1482                 CHECK_RETVAL(arc_set_register_value(target, ap_amv_reg_name,
1483                                          match_value));
1484                 CHECK_RETVAL(arc_set_register_value(target, ap_amm_reg_name, 0));
1485                 CHECK_RETVAL(arc_set_register_value(target, ap_ac_reg_name,
1486                                          control_tt | control_at));
1487                 arc->actionpoints_num_avail--;
1488         } else {
1489                 char ap_ac_reg_name[24];
1490                 snprintf(ap_ac_reg_name, 24, "ap_ac%" PRIu32, ap_num);
1491                 CHECK_RETVAL(arc_set_register_value(target, ap_ac_reg_name,
1492                                          AP_AC_TT_DISABLE));
1493                 arc->actionpoints_num_avail++;
1494         }
1495
1496         return ERROR_OK;
1497 }
1498
1499 static int arc_set_breakpoint(struct target *target,
1500                 struct breakpoint *breakpoint)
1501 {
1502         if (breakpoint->set) {
1503                 LOG_WARNING("breakpoint already set");
1504                 return ERROR_OK;
1505         }
1506
1507         if (breakpoint->type == BKPT_SOFT) {
1508                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
1509
1510                 if (breakpoint->length == 4) {
1511                         uint32_t verify = 0xffffffff;
1512
1513                         CHECK_RETVAL(target_read_buffer(target, breakpoint->address, breakpoint->length,
1514                                         breakpoint->orig_instr));
1515
1516                         CHECK_RETVAL(arc_write_instruction_u32(target, breakpoint->address,
1517                                         ARC_SDBBP_32));
1518
1519                         CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &verify));
1520
1521                         if (verify != ARC_SDBBP_32) {
1522                                 LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
1523                                                 " - check that memory is read/writable", breakpoint->address);
1524                                 return ERROR_FAIL;
1525                         }
1526                 } else if (breakpoint->length == 2) {
1527                         uint16_t verify = 0xffff;
1528
1529                         CHECK_RETVAL(target_read_buffer(target, breakpoint->address, breakpoint->length,
1530                                         breakpoint->orig_instr));
1531                         CHECK_RETVAL(target_write_u16(target, breakpoint->address, ARC_SDBBP_16));
1532
1533                         CHECK_RETVAL(target_read_u16(target, breakpoint->address, &verify));
1534                         if (verify != ARC_SDBBP_16) {
1535                                 LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
1536                                                 " - check that memory is read/writable", breakpoint->address);
1537                                 return ERROR_FAIL;
1538                         }
1539                 } else {
1540                         LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1541                         return ERROR_COMMAND_ARGUMENT_INVALID;
1542                 }
1543
1544                 breakpoint->set = 64; /* Any nice value but 0 */
1545         } else if (breakpoint->type == BKPT_HARD) {
1546                 struct arc_common *arc = target_to_arc(target);
1547                 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1548                 unsigned int bp_num;
1549
1550                 for (bp_num = 0; bp_num < arc->actionpoints_num; bp_num++) {
1551                         if (!ap_list[bp_num].used)
1552                                 break;
1553                 }
1554
1555                 if (bp_num >= arc->actionpoints_num) {
1556                         LOG_ERROR("No free actionpoints, maximum amount is %u",
1557                                         arc->actionpoints_num);
1558                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1559                 }
1560
1561                 int retval = arc_configure_actionpoint(target, bp_num,
1562                                 breakpoint->address, AP_AC_TT_READWRITE, AP_AC_AT_INST_ADDR);
1563
1564                 if (retval == ERROR_OK) {
1565                         breakpoint->set = bp_num + 1;
1566                         ap_list[bp_num].used = 1;
1567                         ap_list[bp_num].bp_value = breakpoint->address;
1568                         ap_list[bp_num].type = ARC_AP_BREAKPOINT;
1569
1570                         LOG_DEBUG("bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
1571                                         breakpoint->unique_id, bp_num, ap_list[bp_num].bp_value);
1572                 }
1573
1574         } else {
1575                 LOG_DEBUG("ERROR: setting unknown breakpoint type");
1576                 return ERROR_FAIL;
1577         }
1578
1579         /* core instruction cache is now invalid. */
1580         CHECK_RETVAL(arc_cache_invalidate(target));
1581
1582         return ERROR_OK;
1583 }
1584
1585 static int arc_unset_breakpoint(struct target *target,
1586                 struct breakpoint *breakpoint)
1587 {
1588         int retval = ERROR_OK;
1589
1590         if (!breakpoint->set) {
1591                 LOG_WARNING("breakpoint not set");
1592                 return ERROR_OK;
1593         }
1594
1595         if (breakpoint->type == BKPT_SOFT) {
1596                 /* restore original instruction (kept in target endianness) */
1597                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
1598                 if (breakpoint->length == 4) {
1599                         uint32_t current_instr;
1600
1601                         /* check that user program has not modified breakpoint instruction */
1602                         CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &current_instr));
1603
1604                         if (current_instr == ARC_SDBBP_32) {
1605                                 retval = target_write_buffer(target, breakpoint->address,
1606                                         breakpoint->length, breakpoint->orig_instr);
1607                                 if (retval != ERROR_OK)
1608                                         return retval;
1609                         } else {
1610                                 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1611                                         " has been overwritten outside of debugger."
1612                                         "Expected: @0x%x, got: @0x%" PRIx32,
1613                                         breakpoint->address, ARC_SDBBP_32, current_instr);
1614                         }
1615                 } else if (breakpoint->length == 2) {
1616                         uint16_t current_instr;
1617
1618                         /* check that user program has not modified breakpoint instruction */
1619                         CHECK_RETVAL(target_read_u16(target, breakpoint->address, &current_instr));
1620                         if (current_instr == ARC_SDBBP_16) {
1621                                 retval = target_write_buffer(target, breakpoint->address,
1622                                         breakpoint->length, breakpoint->orig_instr);
1623                                 if (retval != ERROR_OK)
1624                                         return retval;
1625                         } else {
1626                                 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1627                                         " has been overwritten outside of debugger. "
1628                                         "Expected: 0x%04x, got: 0x%04" PRIx16,
1629                                         breakpoint->address, ARC_SDBBP_16, current_instr);
1630                         }
1631                 } else {
1632                         LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1633                         return ERROR_COMMAND_ARGUMENT_INVALID;
1634                 }
1635                 breakpoint->set = 0;
1636
1637         }       else if (breakpoint->type == BKPT_HARD) {
1638                 struct arc_common *arc = target_to_arc(target);
1639                 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1640                 unsigned int bp_num = breakpoint->set - 1;
1641
1642                 if ((breakpoint->set == 0) || (bp_num >= arc->actionpoints_num)) {
1643                         LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
1644                                           bp_num, breakpoint->unique_id);
1645                         return ERROR_OK;
1646                 }
1647
1648                 retval = arc_configure_actionpoint(target, bp_num,
1649                                                 breakpoint->address, AP_AC_TT_DISABLE, AP_AC_AT_INST_ADDR);
1650
1651                 if (retval == ERROR_OK) {
1652                         breakpoint->set = 0;
1653                         ap_list[bp_num].used = 0;
1654                         ap_list[bp_num].bp_value = 0;
1655
1656                         LOG_DEBUG("bpid: %" PRIu32 " - released actionpoint ID: %i",
1657                                         breakpoint->unique_id, bp_num);
1658                 }
1659         } else {
1660                         LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
1661                         return ERROR_FAIL;
1662         }
1663
1664         /* core instruction cache is now invalid. */
1665         CHECK_RETVAL(arc_cache_invalidate(target));
1666
1667         return retval;
1668 }
1669
1670
1671 static int arc_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1672 {
1673         if (target->state == TARGET_HALTED) {
1674                 return arc_set_breakpoint(target, breakpoint);
1675
1676         } else {
1677                 LOG_WARNING(" > core was not halted, please try again.");
1678                 return ERROR_TARGET_NOT_HALTED;
1679         }
1680 }
1681
1682 static int arc_remove_breakpoint(struct target *target,
1683         struct breakpoint *breakpoint)
1684 {
1685         if (target->state == TARGET_HALTED) {
1686                 if (breakpoint->set)
1687                         CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
1688         } else {
1689                 LOG_WARNING("target not halted");
1690                 return ERROR_TARGET_NOT_HALTED;
1691         }
1692
1693         return ERROR_OK;
1694 }
1695
1696 void arc_reset_actionpoints(struct target *target)
1697 {
1698         struct arc_common *arc = target_to_arc(target);
1699         struct arc_actionpoint *ap_list = arc->actionpoints_list;
1700         struct breakpoint *next_b;
1701         struct watchpoint *next_w;
1702
1703         while (target->breakpoints) {
1704                 next_b = target->breakpoints->next;
1705                 arc_remove_breakpoint(target, target->breakpoints);
1706                 free(target->breakpoints->orig_instr);
1707                 free(target->breakpoints);
1708                 target->breakpoints = next_b;
1709         }
1710         while (target->watchpoints) {
1711                 next_w = target->watchpoints->next;
1712                 arc_remove_watchpoint(target, target->watchpoints);
1713                 free(target->watchpoints);
1714                 target->watchpoints = next_w;
1715         }
1716         for (unsigned int i = 0; i < arc->actionpoints_num; i++) {
1717                 if ((ap_list[i].used) && (ap_list[i].reg_address))
1718                         arc_remove_auxreg_actionpoint(target, ap_list[i].reg_address);
1719         }
1720 }
1721
1722 int arc_set_actionpoints_num(struct target *target, uint32_t ap_num)
1723 {
1724         LOG_DEBUG("target=%s actionpoints=%" PRIu32, target_name(target), ap_num);
1725         struct arc_common *arc = target_to_arc(target);
1726
1727         /* Make sure that there are no enabled actionpoints in target. */
1728         arc_reset_actionpoints(target);
1729
1730         /* Assume that all points have been removed from target.  */
1731         free(arc->actionpoints_list);
1732
1733         arc->actionpoints_num_avail = ap_num;
1734         arc->actionpoints_num = ap_num;
1735         /* calloc can be safely called when ncount == 0.  */
1736         arc->actionpoints_list = calloc(ap_num, sizeof(struct arc_actionpoint));
1737
1738         if (!arc->actionpoints_list) {
1739                 LOG_ERROR("Unable to allocate memory");
1740                 return ERROR_FAIL;
1741         }
1742         return ERROR_OK;
1743 }
1744
1745
1746 int arc_add_auxreg_actionpoint(struct target *target,
1747         uint32_t auxreg_addr, uint32_t transaction)
1748 {
1749         unsigned int ap_num = 0;
1750         int retval = ERROR_OK;
1751
1752         if (target->state != TARGET_HALTED)
1753                 return ERROR_TARGET_NOT_HALTED;
1754
1755         struct arc_common *arc = target_to_arc(target);
1756         struct arc_actionpoint *ap_list = arc->actionpoints_list;
1757
1758         while (ap_list[ap_num].used)
1759                 ap_num++;
1760
1761         if (ap_num >= arc->actionpoints_num) {
1762                 LOG_ERROR("No actionpoint free, maximum amount is %u",
1763                                 arc->actionpoints_num);
1764                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1765         }
1766
1767         retval =  arc_configure_actionpoint(target, ap_num,
1768                         auxreg_addr, transaction, AP_AC_AT_AUXREG_ADDR);
1769
1770         if (retval == ERROR_OK) {
1771                 ap_list[ap_num].used = 1;
1772                 ap_list[ap_num].reg_address = auxreg_addr;
1773         }
1774
1775         return retval;
1776 }
1777
1778 int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr)
1779 {
1780         int retval = ERROR_OK;
1781         bool ap_found = false;
1782         unsigned int ap_num = 0;
1783
1784         if (target->state != TARGET_HALTED)
1785                 return ERROR_TARGET_NOT_HALTED;
1786
1787         struct arc_common *arc = target_to_arc(target);
1788         struct arc_actionpoint *ap_list = arc->actionpoints_list;
1789
1790         while ((ap_list[ap_num].used) && (ap_num < arc->actionpoints_num)) {
1791                 if (ap_list[ap_num].reg_address == auxreg_addr) {
1792                         ap_found = true;
1793                         break;
1794                 }
1795                 ap_num++;
1796         }
1797
1798         if (ap_found) {
1799                 retval =  arc_configure_actionpoint(target, ap_num,
1800                                 auxreg_addr, AP_AC_TT_DISABLE, AP_AC_AT_AUXREG_ADDR);
1801
1802                 if (retval == ERROR_OK) {
1803                         ap_list[ap_num].used = 0;
1804                         ap_list[ap_num].bp_value = 0;
1805                 }
1806         } else {
1807                 LOG_ERROR("Register actionpoint not found");
1808         }
1809         return retval;
1810 }
1811
1812
1813 static int arc_set_watchpoint(struct target *target,
1814                 struct watchpoint *watchpoint)
1815 {
1816         unsigned int wp_num;
1817         struct arc_common *arc = target_to_arc(target);
1818         struct arc_actionpoint *ap_list = arc->actionpoints_list;
1819
1820         if (watchpoint->set) {
1821                 LOG_WARNING("watchpoint already set");
1822                 return ERROR_OK;
1823         }
1824
1825         for (wp_num = 0; wp_num < arc->actionpoints_num; wp_num++) {
1826                 if (!ap_list[wp_num].used)
1827                         break;
1828         }
1829
1830         if (wp_num >= arc->actionpoints_num) {
1831                 LOG_ERROR("No free actionpoints, maximum amount is %u",
1832                                 arc->actionpoints_num);
1833                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1834         }
1835
1836         if (watchpoint->length != 4) {
1837                 LOG_ERROR("Only watchpoints of length 4 are supported");
1838                 return ERROR_TARGET_UNALIGNED_ACCESS;
1839         }
1840
1841         int enable = AP_AC_TT_DISABLE;
1842         switch (watchpoint->rw) {
1843                 case WPT_READ:
1844                         enable = AP_AC_TT_READ;
1845                         break;
1846                 case WPT_WRITE:
1847                         enable = AP_AC_TT_WRITE;
1848                         break;
1849                 case WPT_ACCESS:
1850                         enable = AP_AC_TT_READWRITE;
1851                         break;
1852                 default:
1853                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
1854                         return ERROR_FAIL;
1855         }
1856
1857         int retval =  arc_configure_actionpoint(target, wp_num,
1858                                         watchpoint->address, enable, AP_AC_AT_MEMORY_ADDR);
1859
1860         if (retval == ERROR_OK) {
1861                 watchpoint->set = wp_num + 1;
1862                 ap_list[wp_num].used = 1;
1863                 ap_list[wp_num].bp_value = watchpoint->address;
1864                 ap_list[wp_num].type = ARC_AP_WATCHPOINT;
1865
1866                 LOG_DEBUG("wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
1867                                 watchpoint->unique_id, wp_num, ap_list[wp_num].bp_value);
1868         }
1869
1870         return retval;
1871 }
1872
1873 static int arc_unset_watchpoint(struct target *target,
1874                 struct watchpoint *watchpoint)
1875 {
1876         /* get pointers to arch-specific information */
1877         struct arc_common *arc = target_to_arc(target);
1878         struct arc_actionpoint *ap_list = arc->actionpoints_list;
1879
1880         if (!watchpoint->set) {
1881                 LOG_WARNING("watchpoint not set");
1882                 return ERROR_OK;
1883         }
1884
1885         unsigned int wp_num = watchpoint->set - 1;
1886         if ((watchpoint->set == 0) || (wp_num >= arc->actionpoints_num)) {
1887                 LOG_DEBUG("Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
1888                                 wp_num, watchpoint->unique_id);
1889                 return ERROR_OK;
1890         }
1891
1892         int retval =  arc_configure_actionpoint(target, wp_num,
1893                                 watchpoint->address, AP_AC_TT_DISABLE, AP_AC_AT_MEMORY_ADDR);
1894
1895         if (retval == ERROR_OK) {
1896                 watchpoint->set = 0;
1897                 ap_list[wp_num].used = 0;
1898                 ap_list[wp_num].bp_value = 0;
1899
1900                 LOG_DEBUG("wpid: %" PRIu32 " - releasing actionpoint ID: %u",
1901                                 watchpoint->unique_id, wp_num);
1902         }
1903
1904         return retval;
1905 }
1906
1907 static int arc_add_watchpoint(struct target *target,
1908         struct watchpoint *watchpoint)
1909 {
1910         if (target->state != TARGET_HALTED) {
1911                 LOG_WARNING("target not halted");
1912                 return ERROR_TARGET_NOT_HALTED;
1913         }
1914
1915         CHECK_RETVAL(arc_set_watchpoint(target, watchpoint));
1916
1917         return ERROR_OK;
1918 }
1919
1920 static int arc_remove_watchpoint(struct target *target,
1921         struct watchpoint *watchpoint)
1922 {
1923         if (target->state != TARGET_HALTED) {
1924                 LOG_WARNING("target not halted");
1925                 return ERROR_TARGET_NOT_HALTED;
1926         }
1927
1928         if (watchpoint->set)
1929                 CHECK_RETVAL(arc_unset_watchpoint(target, watchpoint));
1930
1931         return ERROR_OK;
1932 }
1933
1934 static int arc_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1935 {
1936         assert(target);
1937         assert(hit_watchpoint);
1938
1939         struct arc_actionpoint *actionpoint = NULL;
1940         CHECK_RETVAL(get_current_actionpoint(target, &actionpoint));
1941
1942         if (actionpoint != NULL) {
1943                 if (!actionpoint->used)
1944                         LOG_WARNING("Target halted by unused actionpoint.");
1945
1946                 /* If this check fails - that is some sort of an error in OpenOCD. */
1947                 if (actionpoint->type != ARC_AP_WATCHPOINT)
1948                         LOG_WARNING("Target halted by breakpoint, but is treated as a watchpoint.");
1949
1950                 for (struct watchpoint *watchpoint = target->watchpoints;
1951                                 watchpoint != NULL;
1952                                 watchpoint = watchpoint->next) {
1953                         if (actionpoint->bp_value == watchpoint->address) {
1954                                 *hit_watchpoint = watchpoint;
1955                                 LOG_DEBUG("Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %i",
1956                                                         watchpoint->unique_id, watchpoint->set - 1);
1957                                 return ERROR_OK;
1958                         }
1959                 }
1960         }
1961
1962         return ERROR_FAIL;
1963 }
1964
1965 /* Helper function which switches core to single_step mode by
1966  * doing aux r/w operations.  */
1967 int arc_config_step(struct target *target, int enable_step)
1968 {
1969         uint32_t value;
1970
1971         struct arc_common *arc = target_to_arc(target);
1972
1973         /* enable core debug step mode */
1974         if (enable_step) {
1975                 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
1976                         &value));
1977                 value &= ~SET_CORE_AE_BIT; /* clear the AE bit */
1978                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
1979                         value));
1980                 LOG_DEBUG(" [status32:0x%08" PRIx32 "]", value);
1981
1982                 /* Doing read-modify-write, because DEBUG might contain manually set
1983                  * bits like UB or ED, which should be preserved.  */
1984                 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info,
1985                                         AUX_DEBUG_REG, &value));
1986                 value |= SET_CORE_SINGLE_INSTR_STEP; /* set the IS bit */
1987                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
1988                         value));
1989                 LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
1990
1991         } else {        /* disable core debug step mode */
1992                 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
1993                         &value));
1994                 value &= ~SET_CORE_SINGLE_INSTR_STEP; /* clear the IS bit */
1995                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
1996                         value));
1997                 LOG_DEBUG("core debug step mode disabled");
1998         }
1999
2000         return ERROR_OK;
2001 }
2002
2003 int arc_step(struct target *target, int current, target_addr_t address,
2004         int handle_breakpoints)
2005 {
2006         /* get pointers to arch-specific information */
2007         struct arc_common *arc = target_to_arc(target);
2008         struct breakpoint *breakpoint = NULL;
2009         struct reg *pc = &(arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache]);
2010
2011         if (target->state != TARGET_HALTED) {
2012                 LOG_WARNING("target not halted");
2013                 return ERROR_TARGET_NOT_HALTED;
2014         }
2015
2016         /* current = 1: continue on current pc, otherwise continue at <address> */
2017         if (!current) {
2018                 buf_set_u32(pc->value, 0, 32, address);
2019                 pc->dirty = 1;
2020                 pc->valid = 1;
2021         }
2022
2023         LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32,
2024                 buf_get_u32(pc->value, 0, 32));
2025
2026         /* the front-end may request us not to handle breakpoints */
2027         if (handle_breakpoints) {
2028                 breakpoint = breakpoint_find(target, buf_get_u32(pc->value, 0, 32));
2029                 if (breakpoint)
2030                         CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
2031         }
2032
2033         /* restore context */
2034         CHECK_RETVAL(arc_restore_context(target));
2035
2036         target->debug_reason = DBG_REASON_SINGLESTEP;
2037
2038         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
2039
2040         /* disable interrupts while stepping */
2041         CHECK_RETVAL(arc_enable_interrupts(target, 0));
2042
2043         /* do a single step */
2044         CHECK_RETVAL(arc_config_step(target, 1));
2045
2046         /* make sure we done our step */
2047         alive_sleep(1);
2048
2049         /* registers are now invalid */
2050         register_cache_invalidate(arc->core_and_aux_cache);
2051
2052         if (breakpoint)
2053                 CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
2054
2055         LOG_DEBUG("target stepped ");
2056
2057         target->state = TARGET_HALTED;
2058
2059         /* Saving context */
2060         CHECK_RETVAL(arc_debug_entry(target));
2061         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
2062
2063         return ERROR_OK;
2064 }
2065
2066
2067 /* This function invalidates icache. */
2068 static int arc_icache_invalidate(struct target *target)
2069 {
2070         uint32_t value;
2071
2072         struct arc_common *arc = target_to_arc(target);
2073
2074         /* Don't waste time if already done. */
2075         if (!arc->has_icache || arc->icache_invalidated)
2076             return ERROR_OK;
2077
2078         LOG_DEBUG("Invalidating I$.");
2079
2080         value = IC_IVIC_INVALIDATE;     /* invalidate I$ */
2081         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value));
2082
2083         arc->icache_invalidated = true;
2084
2085         return ERROR_OK;
2086 }
2087
2088 /* This function invalidates dcache */
2089 static int arc_dcache_invalidate(struct target *target)
2090 {
2091         uint32_t value, dc_ctrl_value;
2092
2093         struct arc_common *arc = target_to_arc(target);
2094
2095         if (!arc->has_dcache || arc->dcache_invalidated)
2096             return ERROR_OK;
2097
2098         LOG_DEBUG("Invalidating D$.");
2099
2100         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value));
2101         dc_ctrl_value = value;
2102         value &= ~DC_CTRL_IM;
2103
2104         /* set DC_CTRL invalidate mode to invalidate-only (no flushing!!) */
2105         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
2106         value = DC_IVDC_INVALIDATE;     /* invalidate D$ */
2107         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
2108
2109         /* restore DC_CTRL invalidate mode */
2110         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
2111
2112         arc->dcache_invalidated = true;
2113
2114         return ERROR_OK;
2115 }
2116
2117 /* This function invalidates l2 cache. */
2118 static int arc_l2cache_invalidate(struct target *target)
2119 {
2120         uint32_t value, slc_ctrl_value;
2121
2122         struct arc_common *arc = target_to_arc(target);
2123
2124         if (!arc->has_l2cache || arc->l2cache_invalidated)
2125             return ERROR_OK;
2126
2127         LOG_DEBUG("Invalidating L2$.");
2128
2129         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
2130         slc_ctrl_value = value;
2131         value &= ~L2_CTRL_IM;
2132
2133         /* set L2_CTRL invalidate mode to invalidate-only (no flushing!!) */
2134         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, value));
2135         /* invalidate L2$ */
2136         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_INV, L2_INV_IV));
2137
2138         /* Wait until invalidate operation ends */
2139         do {
2140             LOG_DEBUG("Waiting for invalidation end.");
2141             CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
2142         } while (value & L2_CTRL_BS);
2143
2144         /* restore L2_CTRL invalidate mode */
2145         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, slc_ctrl_value));
2146
2147         arc->l2cache_invalidated = true;
2148
2149         return ERROR_OK;
2150 }
2151
2152
2153 int arc_cache_invalidate(struct target *target)
2154 {
2155         CHECK_RETVAL(arc_icache_invalidate(target));
2156         CHECK_RETVAL(arc_dcache_invalidate(target));
2157         CHECK_RETVAL(arc_l2cache_invalidate(target));
2158
2159         return ERROR_OK;
2160 }
2161
2162 /* Flush data cache. This function is cheap to call and return quickly if D$
2163  * already has been flushed since target had been halted. JTAG debugger reads
2164  * values directly from memory, bypassing cache, so if there are unflushed
2165  * lines debugger will read invalid values, which will cause a lot of troubles.
2166  * */
2167 int arc_dcache_flush(struct target *target)
2168 {
2169         uint32_t value, dc_ctrl_value;
2170         bool has_to_set_dc_ctrl_im;
2171
2172         struct arc_common *arc = target_to_arc(target);
2173
2174         /* Don't waste time if already done. */
2175         if (!arc->has_dcache || arc->dcache_flushed)
2176             return ERROR_OK;
2177
2178         LOG_DEBUG("Flushing D$.");
2179
2180         /* Store current value of DC_CTRL */
2181         CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value));
2182
2183         /* Set DC_CTRL invalidate mode to flush (if not already set) */
2184         has_to_set_dc_ctrl_im = (dc_ctrl_value & DC_CTRL_IM) == 0;
2185         if (has_to_set_dc_ctrl_im) {
2186                 value = dc_ctrl_value | DC_CTRL_IM;
2187                 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
2188         }
2189
2190         /* Flush D$ */
2191         value = DC_IVDC_INVALIDATE;
2192         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
2193
2194         /* Restore DC_CTRL invalidate mode (even of flush failed) */
2195         if (has_to_set_dc_ctrl_im)
2196             CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
2197
2198         arc->dcache_flushed = true;
2199
2200         return ERROR_OK;
2201 }
2202
2203 /* This function flushes l2cache. */
2204 static int arc_l2cache_flush(struct target *target)
2205 {
2206         uint32_t value;
2207
2208         struct arc_common *arc = target_to_arc(target);
2209
2210         /* Don't waste time if already done. */
2211         if (!arc->has_l2cache || arc->l2cache_flushed)
2212             return ERROR_OK;
2213
2214         LOG_DEBUG("Flushing L2$.");
2215
2216         /* Flush L2 cache */
2217         CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL));
2218
2219         /* Wait until flush operation ends */
2220         do {
2221             LOG_DEBUG("Waiting for flushing end.");
2222             CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
2223         } while (value & L2_CTRL_BS);
2224
2225         arc->l2cache_flushed = true;
2226
2227         return ERROR_OK;
2228 }
2229
2230 int arc_cache_flush(struct target *target)
2231 {
2232         CHECK_RETVAL(arc_dcache_flush(target));
2233         CHECK_RETVAL(arc_l2cache_flush(target));
2234
2235         return ERROR_OK;
2236 }
2237
2238 /* ARC v2 target */
2239 struct target_type arcv2_target = {
2240         .name = "arcv2",
2241
2242         .poll = arc_poll,
2243
2244         .arch_state = arc_arch_state,
2245
2246         /* TODO That seems like something similar to metaware hostlink, so perhaps
2247          * we can exploit this in the future. */
2248         .target_request_data = NULL,
2249
2250         .halt = arc_halt,
2251         .resume = arc_resume,
2252         .step = arc_step,
2253
2254         .assert_reset = arc_assert_reset,
2255         .deassert_reset = arc_deassert_reset,
2256
2257         /* TODO Implement soft_reset_halt */
2258         .soft_reset_halt = NULL,
2259
2260         .get_gdb_reg_list = arc_get_gdb_reg_list,
2261
2262         .read_memory = arc_mem_read,
2263         .write_memory = arc_mem_write,
2264         .checksum_memory = NULL,
2265         .blank_check_memory = NULL,
2266
2267         .add_breakpoint = arc_add_breakpoint,
2268         .add_context_breakpoint = NULL,
2269         .add_hybrid_breakpoint = NULL,
2270         .remove_breakpoint = arc_remove_breakpoint,
2271         .add_watchpoint = arc_add_watchpoint,
2272         .remove_watchpoint = arc_remove_watchpoint,
2273         .hit_watchpoint = arc_hit_watchpoint,
2274
2275         .run_algorithm = NULL,
2276         .start_algorithm = NULL,
2277         .wait_algorithm = NULL,
2278
2279         .commands = arc_monitor_command_handlers,
2280
2281         .target_create = arc_target_create,
2282         .init_target = arc_init_target,
2283         .deinit_target = arc_deinit_target,
2284         .examine = arc_examine,
2285
2286         .virt2phys = NULL,
2287         .read_phys_memory = NULL,
2288         .write_phys_memory = NULL,
2289         .mmu = NULL,
2290 };