1 /***************************************************************************
2 * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
3 * Frank Dols <frank.dols@synopsys.com> *
4 * Mischa Jonker <mischa.jonker@synopsys.com> *
5 * Anton Kolesov <anton.kolesov@synopsys.com> *
6 * Evgeniy Didin <didin@synopsys.com> *
8 * SPDX-License-Identifier: GPL-2.0-or-later *
9 ***************************************************************************/
21 * ARC architecture specific details.
23 * ARC has two types of registers:
24 * 1) core registers(e.g. r0,r1..) [is_core = true]
25 * 2) Auxiliary registers [is_core = false]..
27 * Auxiliary registers at the same time can be divided into
28 * read-only BCR(build configuration regs, e.g. isa_config, mpu_build) and
29 * R/RW non-BCR ("control" register, e.g. pc, status32_t, debug).
31 * The way of accessing to Core and AUX registers differs on Jtag level.
32 * BCR/non-BCR describes if the register is immutable and that reading
33 * unexisting register is safe RAZ, rather then an error.
34 * Note, core registers cannot be BCR.
36 * In arc/cpu/ tcl files all regiters are defined as core, non-BCR aux
37 * and BCR aux, in "add-reg" command they are passed to three lists
38 * respectively: core_reg_descriptions, aux_reg_descriptions,
39 * bcr_reg_descriptions.
41 * Due to the specifics of accessing to BCR/non-BCR registers there are two
43 * 1) core_and_aux_cache - includes registers described in
44 * core_reg_descriptions and aux_reg_descriptions lists.
45 * Used during save/restore context step.
46 * 2) bcr_cache - includes registers described bcr_reg_descriptions.
47 * Currently used internally during configure step.
52 void arc_reg_data_type_add(struct target *target,
53 struct arc_reg_data_type *data_type)
55 LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id);
56 struct arc_common *arc = target_to_arc(target);
59 list_add_tail(&data_type->list, &arc->reg_data_types);
63 * Private implementation of register_get_by_name() for ARC that
64 * doesn't skip not [yet] existing registers. Used in many places
65 * for iteration through registers and even for marking required registers as
68 struct reg *arc_reg_get_by_name(struct reg_cache *first,
69 const char *name, bool search_all)
72 struct reg_cache *cache = first;
75 for (i = 0; i < cache->num_regs; i++) {
76 if (!strcmp(cache->reg_list[i].name, name))
77 return &(cache->reg_list[i]);
90 * Reset internal states of caches. Must be called when entering debugging.
92 * @param target Target for which to reset caches states.
94 int arc_reset_caches_states(struct target *target)
96 struct arc_common *arc = target_to_arc(target);
98 LOG_DEBUG("Resetting internal variables of caches states");
100 /* Reset caches states. */
101 arc->dcache_flushed = false;
102 arc->l2cache_flushed = false;
103 arc->icache_invalidated = false;
104 arc->dcache_invalidated = false;
105 arc->l2cache_invalidated = false;
110 /* Initialize arc_common structure, which passes to openocd target instance */
111 static int arc_init_arch_info(struct target *target, struct arc_common *arc,
112 struct jtag_tap *tap)
114 arc->common_magic = ARC_COMMON_MAGIC;
115 target->arch_info = arc;
117 arc->jtag_info.tap = tap;
119 /* The only allowed ir_length is 4 for ARC jtag. */
120 if (tap->ir_length != 4) {
121 LOG_ERROR("ARC jtag instruction length should be equal to 4");
125 /* On most ARC targets there is a dcache, so we enable its flushing
126 * by default. If there no dcache, there will be no error, just a slight
127 * performance penalty from unnecessary JTAG operations. */
128 arc->has_dcache = true;
129 arc->has_icache = true;
130 /* L2$ is not available in a target by default. */
131 arc->has_l2cache = false;
132 arc_reset_caches_states(target);
134 /* Add standard GDB data types */
135 INIT_LIST_HEAD(&arc->reg_data_types);
136 struct arc_reg_data_type *std_types = calloc(ARRAY_SIZE(standard_gdb_types),
140 LOG_ERROR("Unable to allocate memory");
144 for (unsigned int i = 0; i < ARRAY_SIZE(standard_gdb_types); i++) {
145 std_types[i].data_type.type = standard_gdb_types[i].type;
146 std_types[i].data_type.id = standard_gdb_types[i].id;
147 arc_reg_data_type_add(target, &(std_types[i]));
150 /* Fields related to target descriptions */
151 INIT_LIST_HEAD(&arc->core_reg_descriptions);
152 INIT_LIST_HEAD(&arc->aux_reg_descriptions);
153 INIT_LIST_HEAD(&arc->bcr_reg_descriptions);
155 arc->num_core_regs = 0;
156 arc->num_aux_regs = 0;
157 arc->num_bcr_regs = 0;
158 arc->last_general_reg = ULONG_MAX;
159 arc->pc_index_in_cache = ULONG_MAX;
160 arc->debug_index_in_cache = ULONG_MAX;
165 int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
166 const char * const type_name, const size_t type_name_len)
171 struct arc_common *arc = target_to_arc(target);
174 /* Find register type */
176 struct arc_reg_data_type *type;
177 list_for_each_entry(type, &arc->reg_data_types, list)
178 if (!strncmp(type->data_type.id, type_name, type_name_len)) {
179 arc_reg->data_type = &(type->data_type);
183 if (!arc_reg->data_type)
184 return ERROR_ARC_REGTYPE_NOT_FOUND;
187 if (arc_reg->is_core) {
188 list_add_tail(&arc_reg->list, &arc->core_reg_descriptions);
189 arc->num_core_regs += 1;
190 } else if (arc_reg->is_bcr) {
191 list_add_tail(&arc_reg->list, &arc->bcr_reg_descriptions);
192 arc->num_bcr_regs += 1;
194 list_add_tail(&arc_reg->list, &arc->aux_reg_descriptions);
195 arc->num_aux_regs += 1;
200 "added register {name=%s, num=0x%x, type=%s%s%s%s}",
201 arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id,
202 arc_reg->is_core ? ", core" : "", arc_reg->is_bcr ? ", bcr" : "",
203 arc_reg->is_general ? ", general" : ""
209 /* Reading core or aux register */
210 static int arc_get_register(struct reg *reg)
214 struct arc_reg_desc *desc = reg->arch_info;
215 struct target *target = desc->target;
216 struct arc_common *arc = target_to_arc(target);
221 LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
222 reg->number, desc->name, target_buffer_get_u32(target, reg->value));
227 /* Accessing to R61/R62 registers causes Jtag hang */
228 if (desc->arch_num == CORE_R61_NUM || desc->arch_num == CORE_R62_NUM) {
229 LOG_ERROR("It is forbidden to read core registers 61 and 62.");
232 CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, desc->arch_num,
235 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, desc->arch_num,
239 target_buffer_set_u32(target, reg->value, value);
241 /* If target is unhalted all register reads should be uncached. */
242 if (target->state == TARGET_HALTED)
249 LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
250 reg->number , desc->name, value);
256 /* Writing core or aux register */
257 static int arc_set_register(struct reg *reg, uint8_t *buf)
259 struct arc_reg_desc *desc = reg->arch_info;
260 struct target *target = desc->target;
261 uint32_t value = target_buffer_get_u32(target, buf);
262 /* Unlike "get" function "set" is supported only if target
263 * is in halt mode. Async writes are not supported yet. */
264 if (target->state != TARGET_HALTED)
265 return ERROR_TARGET_NOT_HALTED;
267 /* Accessing to R61/R62 registers causes Jtag hang */
268 if (desc->is_core && (desc->arch_num == CORE_R61_NUM ||
269 desc->arch_num == CORE_R62_NUM)) {
270 LOG_ERROR("It is forbidden to write core registers 61 and 62.");
273 target_buffer_set_u32(target, reg->value, value);
275 LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
276 reg->number, desc->name, value);
284 const struct reg_arch_type arc_reg_type = {
285 .get = arc_get_register,
286 .set = arc_set_register,
289 /* GDB register groups. For now we suport only general and "empty" */
290 static const char * const reg_group_general = "general";
291 static const char * const reg_group_other = "";
293 /* Common code to initialize `struct reg` for different registers: core, aux, bcr. */
294 static int arc_init_reg(struct target *target, struct reg *reg,
295 struct arc_reg_desc *reg_desc, unsigned long number)
301 struct arc_common *arc = target_to_arc(target);
303 /* Initialize struct reg */
304 reg->name = reg_desc->name;
305 reg->size = 32; /* All register in ARC are 32-bit */
306 reg->value = ®_desc->reg_value;
307 reg->type = &arc_reg_type;
308 reg->arch_info = reg_desc;
309 reg->caller_save = true; /* @todo should be configurable. */
310 reg->reg_data_type = reg_desc->data_type;
311 reg->feature = ®_desc->feature;
313 reg->feature->name = reg_desc->gdb_xml_feature;
315 /* reg->number is used by OpenOCD as value for @regnum. Thus when setting
316 * value of a register GDB will use it as a number of register in
317 * P-packet. OpenOCD gdbserver will then use number of register in
318 * P-packet as an array index in the reg_list returned by
319 * arc_regs_get_gdb_reg_list. So to ensure that registers are assigned
320 * correctly it would be required to either sort registers in
321 * arc_regs_get_gdb_reg_list or to assign numbers sequentially here and
322 * according to how registers will be sorted in
323 * arc_regs_get_gdb_reg_list. Second options is much more simpler. */
324 reg->number = number;
326 if (reg_desc->is_general) {
327 arc->last_general_reg = reg->number;
328 reg->group = reg_group_general;
330 reg->group = reg_group_other;
336 /* Building aux/core reg_cache */
337 static int arc_build_reg_cache(struct target *target)
340 struct arc_reg_desc *reg_desc;
341 /* get pointers to arch-specific information */
342 struct arc_common *arc = target_to_arc(target);
343 const unsigned long num_regs = arc->num_core_regs + arc->num_aux_regs;
344 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
345 struct reg_cache *cache = calloc(1, sizeof(*cache));
346 struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
348 if (!cache || !reg_list) {
349 LOG_ERROR("Not enough memory");
353 /* Build the process context cache */
354 cache->name = "arc registers";
356 cache->reg_list = reg_list;
357 cache->num_regs = num_regs;
358 arc->core_and_aux_cache = cache;
361 if (list_empty(&arc->core_reg_descriptions)) {
362 LOG_ERROR("No core registers were defined");
366 list_for_each_entry(reg_desc, &arc->core_reg_descriptions, list) {
367 CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i));
369 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
370 reg_list[i].name, reg_list[i].group,
371 reg_list[i].feature->name);
376 if (list_empty(&arc->aux_reg_descriptions)) {
377 LOG_ERROR("No aux registers were defined");
381 list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
382 CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i));
384 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
385 reg_list[i].name, reg_list[i].group,
386 reg_list[i].feature->name);
388 /* PC and DEBUG are essential so we search for them. */
389 if (!strcmp("pc", reg_desc->name)) {
390 if (arc->pc_index_in_cache != ULONG_MAX) {
391 LOG_ERROR("Double definition of PC in configuration");
394 arc->pc_index_in_cache = i;
395 } else if (!strcmp("debug", reg_desc->name)) {
396 if (arc->debug_index_in_cache != ULONG_MAX) {
397 LOG_ERROR("Double definition of DEBUG in configuration");
400 arc->debug_index_in_cache = i;
405 if (arc->pc_index_in_cache == ULONG_MAX
406 || arc->debug_index_in_cache == ULONG_MAX) {
407 LOG_ERROR("`pc' and `debug' registers must be present in target description.");
411 assert(i == (arc->num_core_regs + arc->num_aux_regs));
413 arc->core_aux_cache_built = true;
424 /* Build bcr reg_cache.
425 * This function must be called only after arc_build_reg_cache */
426 static int arc_build_bcr_reg_cache(struct target *target)
428 /* get pointers to arch-specific information */
429 struct arc_common *arc = target_to_arc(target);
430 const unsigned long num_regs = arc->num_bcr_regs;
431 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
432 struct reg_cache *cache = malloc(sizeof(*cache));
433 struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
435 struct arc_reg_desc *reg_desc;
437 unsigned long gdb_regnum = arc->core_and_aux_cache->num_regs;
439 if (!cache || !reg_list) {
440 LOG_ERROR("Unable to allocate memory");
444 /* Build the process context cache */
445 cache->name = "arc.bcr";
447 cache->reg_list = reg_list;
448 cache->num_regs = num_regs;
449 arc->bcr_cache = cache;
452 if (list_empty(&arc->bcr_reg_descriptions)) {
453 LOG_ERROR("No BCR registers are defined");
457 list_for_each_entry(reg_desc, &arc->bcr_reg_descriptions, list) {
458 CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, gdb_regnum));
459 /* BCRs always semantically, they are just read-as-zero, if there is
460 * not real register. */
461 reg_list[i].exist = true;
463 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
464 reg_list[i].name, reg_list[i].group,
465 reg_list[i].feature->name);
470 assert(i == arc->num_bcr_regs);
472 arc->bcr_cache_built = true;
484 static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
485 int *reg_list_size, enum target_register_class reg_class)
487 assert(target->reg_cache);
488 struct arc_common *arc = target_to_arc(target);
490 /* get pointers to arch-specific information storage */
491 *reg_list_size = arc->num_regs;
492 *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
495 LOG_ERROR("Unable to allocate memory");
499 /* OpenOCD gdb_server API seems to be inconsistent here: when it generates
500 * XML tdesc it filters out !exist registers, however when creating a
501 * g-packet it doesn't do so. REG_CLASS_ALL is used in first case, and
502 * REG_CLASS_GENERAL used in the latter one. Due to this we had to filter
503 * out !exist register for "general", but not for "all". Attempts to filter out
504 * !exist for "all" as well will cause a failed check in OpenOCD GDB
506 if (reg_class == REG_CLASS_ALL) {
508 struct reg_cache *reg_cache = target->reg_cache;
510 for (unsigned j = 0; j < reg_cache->num_regs; j++, i++)
511 (*reg_list)[i] = ®_cache->reg_list[j];
512 reg_cache = reg_cache->next;
514 assert(i == arc->num_regs);
515 LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size);
518 unsigned long gdb_reg_number = 0;
519 struct reg_cache *reg_cache = target->reg_cache;
522 j < reg_cache->num_regs && gdb_reg_number <= arc->last_general_reg;
524 if (reg_cache->reg_list[j].exist) {
525 (*reg_list)[i] = ®_cache->reg_list[j];
530 reg_cache = reg_cache->next;
533 LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
539 /* Reading field of struct_type register */
540 int arc_reg_get_field(struct target *target, const char *reg_name,
541 const char *field_name, uint32_t *value_ptr)
543 struct reg_data_type_struct_field *field;
545 LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
548 struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
551 LOG_ERROR("Requested register `%s' doens't exist.", reg_name);
552 return ERROR_ARC_REGISTER_NOT_FOUND;
555 if (reg->reg_data_type->type != REG_TYPE_ARCH_DEFINED
556 || reg->reg_data_type->type_class != REG_TYPE_CLASS_STRUCT)
557 return ERROR_ARC_REGISTER_IS_NOT_STRUCT;
559 /* Get field in a register */
560 struct reg_data_type_struct *reg_struct =
561 reg->reg_data_type->reg_type_struct;
562 for (field = reg_struct->fields;
564 field = field->next) {
565 if (!strcmp(field->name, field_name))
570 return ERROR_ARC_REGISTER_FIELD_NOT_FOUND;
572 if (!field->use_bitfields)
573 return ERROR_ARC_FIELD_IS_NOT_BITFIELD;
576 CHECK_RETVAL(reg->type->get(reg));
578 /* First do endiannes-safe read of register value
579 * then convert it to binary buffer for further
580 * field extraction */
582 *value_ptr = buf_get_u32(reg->value, field->bitfield->start,
583 field->bitfield->end - field->bitfield->start + 1);
588 static int arc_get_register_value(struct target *target, const char *reg_name,
591 LOG_DEBUG("reg_name=%s", reg_name);
593 struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
596 return ERROR_ARC_REGISTER_NOT_FOUND;
599 CHECK_RETVAL(reg->type->get(reg));
601 *value_ptr = target_buffer_get_u32(target, reg->value);
607 /* Configure DCCM's */
608 static int arc_configure_dccm(struct target *target)
610 struct arc_common *arc = target_to_arc(target);
612 uint32_t dccm_build_version, dccm_build_size0, dccm_build_size1;
613 CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "version",
614 &dccm_build_version));
615 CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size0",
617 CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size1",
619 /* There is no yet support of configurable number of cycles,
620 * So there is no difference between v3 and v4 */
621 if ((dccm_build_version == 3 || dccm_build_version == 4) && dccm_build_size0 > 0) {
622 CHECK_RETVAL(arc_get_register_value(target, "aux_dccm", &(arc->dccm_start)));
623 uint32_t dccm_size = 0x100;
624 dccm_size <<= dccm_build_size0;
625 if (dccm_build_size0 == 0xF)
626 dccm_size <<= dccm_build_size1;
627 arc->dccm_end = arc->dccm_start + dccm_size;
628 LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
629 arc->dccm_start, arc->dccm_end);
636 /* Configure ICCM's */
638 static int arc_configure_iccm(struct target *target)
640 struct arc_common *arc = target_to_arc(target);
643 uint32_t iccm_build_version, iccm_build_size00, iccm_build_size01;
644 uint32_t aux_iccm = 0;
645 CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "version",
646 &iccm_build_version));
647 CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size0",
648 &iccm_build_size00));
649 CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size1",
650 &iccm_build_size01));
651 if (iccm_build_version == 4 && iccm_build_size00 > 0) {
652 CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
653 uint32_t iccm0_size = 0x100;
654 iccm0_size <<= iccm_build_size00;
655 if (iccm_build_size00 == 0xF)
656 iccm0_size <<= iccm_build_size01;
657 /* iccm0 start is located in highest 4 bits of aux_iccm */
658 arc->iccm0_start = aux_iccm & 0xF0000000;
659 arc->iccm0_end = arc->iccm0_start + iccm0_size;
660 LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
661 arc->iccm0_start, arc->iccm0_end);
665 uint32_t iccm_build_size10, iccm_build_size11;
666 CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size0",
667 &iccm_build_size10));
668 CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size1",
669 &iccm_build_size11));
670 if (iccm_build_version == 4 && iccm_build_size10 > 0) {
671 /* Use value read for ICCM0 */
673 CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
674 uint32_t iccm1_size = 0x100;
675 iccm1_size <<= iccm_build_size10;
676 if (iccm_build_size10 == 0xF)
677 iccm1_size <<= iccm_build_size11;
678 arc->iccm1_start = aux_iccm & 0x0F000000;
679 arc->iccm1_end = arc->iccm1_start + iccm1_size;
680 LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
681 arc->iccm1_start, arc->iccm1_end);
686 /* Configure some core features, depending on BCRs. */
687 static int arc_configure(struct target *target)
689 LOG_DEBUG("Configuring ARC ICCM and DCCM");
691 /* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
692 if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
693 arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
694 CHECK_RETVAL(arc_configure_dccm(target));
696 /* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
697 if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) &&
698 arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
699 CHECK_RETVAL(arc_configure_iccm(target));
704 /* arc_examine is function, which is used for all arc targets*/
705 static int arc_examine(struct target *target)
708 struct arc_common *arc = target_to_arc(target);
710 CHECK_RETVAL(arc_jtag_startup(&arc->jtag_info));
712 if (!target_was_examined(target)) {
713 CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
714 if (status & ARC_JTAG_STAT_RU)
715 target->state = TARGET_RUNNING;
717 target->state = TARGET_HALTED;
719 /* Read BCRs and configure optional registers. */
720 CHECK_RETVAL(arc_configure(target));
722 target_set_examined(target);
728 static int arc_halt(struct target *target)
730 uint32_t value, irq_state;
731 struct arc_common *arc = target_to_arc(target);
733 LOG_DEBUG("target->state: %s", target_state_name(target));
735 if (target->state == TARGET_HALTED) {
736 LOG_DEBUG("target was already halted");
740 if (target->state == TARGET_UNKNOWN)
741 LOG_WARNING("target was in unknown state when halt was requested");
743 if (target->state == TARGET_RESET) {
744 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
745 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
746 return ERROR_TARGET_FAILURE;
748 target->debug_reason = DBG_REASON_DBGRQ;
752 /* Break (stop) processor.
753 * Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally.
754 * We do not use here arc_get/set_core_reg functions here because they imply
755 * that the processor is already halted. */
756 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, &value));
757 value |= SET_CORE_FORCE_HALT; /* set the HALT bit */
758 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value));
761 /* Save current IRQ state */
762 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &irq_state));
764 if (irq_state & AUX_STATUS32_REG_IE_BIT)
769 /* update state and notify gdb*/
770 target->state = TARGET_HALTED;
771 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
773 /* some more debug information */
774 if (debug_level >= LOG_LVL_DEBUG) {
775 LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
776 CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
777 LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
784 * Read registers that are used in GDB g-packet. We don't read them one-by-one,
785 * but do that in one batch operation to improve speed. Calls to JTAG layer are
786 * expensive so it is better to make one big call that reads all necessary
787 * registers, instead of many calls, one for one register.
789 static int arc_save_context(struct target *target)
791 int retval = ERROR_OK;
793 struct arc_common *arc = target_to_arc(target);
794 struct reg *reg_list = arc->core_and_aux_cache->reg_list;
796 LOG_DEBUG("Saving aux and core registers values");
799 /* It is assumed that there is at least one AUX register in the list, for
801 const uint32_t core_regs_size = arc->num_core_regs * sizeof(uint32_t);
802 /* last_general_reg is inclusive number. To get count of registers it is
803 * required to do +1. */
804 const uint32_t regs_to_scan =
805 MIN(arc->last_general_reg + 1, arc->num_regs);
806 const uint32_t aux_regs_size = arc->num_aux_regs * sizeof(uint32_t);
807 uint32_t *core_values = malloc(core_regs_size);
808 uint32_t *aux_values = malloc(aux_regs_size);
809 uint32_t *core_addrs = malloc(core_regs_size);
810 uint32_t *aux_addrs = malloc(aux_regs_size);
811 unsigned int core_cnt = 0;
812 unsigned int aux_cnt = 0;
814 if (!core_values || !core_addrs || !aux_values || !aux_addrs) {
815 LOG_ERROR("Unable to allocate memory");
820 memset(core_values, 0xff, core_regs_size);
821 memset(core_addrs, 0xff, core_regs_size);
822 memset(aux_values, 0xff, aux_regs_size);
823 memset(aux_addrs, 0xff, aux_regs_size);
825 for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) {
826 struct reg *reg = &(reg_list[i]);
827 struct arc_reg_desc *arc_reg = reg->arch_info;
828 if (!reg->valid && reg->exist) {
829 core_addrs[core_cnt] = arc_reg->arch_num;
834 for (i = arc->num_core_regs; i < regs_to_scan; i++) {
835 struct reg *reg = &(reg_list[i]);
836 struct arc_reg_desc *arc_reg = reg->arch_info;
837 if (!reg->valid && reg->exist) {
838 aux_addrs[aux_cnt] = arc_reg->arch_num;
843 /* Read data from target. */
845 retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
846 if (ERROR_OK != retval) {
847 LOG_ERROR("Attempt to read core registers failed.");
853 retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
854 if (ERROR_OK != retval) {
855 LOG_ERROR("Attempt to read aux registers failed.");
861 /* Parse core regs */
863 for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) {
864 struct reg *reg = &(reg_list[i]);
865 struct arc_reg_desc *arc_reg = reg->arch_info;
866 if (!reg->valid && reg->exist) {
867 target_buffer_set_u32(target, reg->value, core_values[core_cnt]);
871 LOG_DEBUG("Get core register regnum=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
872 i, arc_reg->name, core_values[core_cnt]);
878 for (i = arc->num_core_regs; i < regs_to_scan; i++) {
879 struct reg *reg = &(reg_list[i]);
880 struct arc_reg_desc *arc_reg = reg->arch_info;
881 if (!reg->valid && reg->exist) {
882 target_buffer_set_u32(target, reg->value, aux_values[aux_cnt]);
886 LOG_DEBUG("Get aux register regnum=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
887 i , arc_reg->name, aux_values[aux_cnt]);
900 static int arc_examine_debug_reason(struct target *target)
904 /* Only check for reason if don't know it already. */
905 /* BTW After singlestep at this point core is not marked as halted, so
906 * reading from memory to get current instruction wouldn't work anyway. */
907 if (target->debug_reason == DBG_REASON_DBGRQ ||
908 target->debug_reason == DBG_REASON_SINGLESTEP) {
912 CHECK_RETVAL(arc_reg_get_field(target, "debug", "bh",
916 /* DEBUG.BH is set if core halted due to BRK instruction. */
917 target->debug_reason = DBG_REASON_BREAKPOINT;
919 /* TODO: Add Actionpoint check when AP support will be introduced*/
920 LOG_WARNING("Unknown debug reason");
926 static int arc_debug_entry(struct target *target)
928 CHECK_RETVAL(arc_save_context(target));
930 /* TODO: reset internal indicators of caches states, otherwise D$/I$
931 * will not be flushed/invalidated when required. */
932 CHECK_RETVAL(arc_reset_caches_states(target));
933 CHECK_RETVAL(arc_examine_debug_reason(target));
938 static int arc_poll(struct target *target)
940 uint32_t status, value;
941 struct arc_common *arc = target_to_arc(target);
943 /* gdb calls continuously through this arc_poll() function */
944 CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
946 /* check for processor halted */
947 if (status & ARC_JTAG_STAT_RU) {
948 if (target->state != TARGET_RUNNING) {
949 LOG_WARNING("target is still running!");
950 target->state = TARGET_RUNNING;
954 /* In some cases JTAG status register indicates that
955 * processor is in halt mode, but processor is still running.
956 * We check halt bit of AUX STATUS32 register for setting correct state. */
957 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
958 CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
959 if (value & AUX_STATUS32_REG_HALT_BIT) {
960 LOG_DEBUG("ARC core in halt or reset state.");
961 /* Save context if target was not in reset state */
962 if (target->state == TARGET_RUNNING)
963 CHECK_RETVAL(arc_debug_entry(target));
964 target->state = TARGET_HALTED;
965 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
967 LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
968 "target is still running");
971 } else if (target->state == TARGET_DEBUG_RUNNING) {
973 target->state = TARGET_HALTED;
974 LOG_DEBUG("ARC core is in debug running mode");
976 CHECK_RETVAL(arc_debug_entry(target));
978 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED));
984 static int arc_assert_reset(struct target *target)
986 struct arc_common *arc = target_to_arc(target);
987 enum reset_types jtag_reset_config = jtag_get_reset_config();
988 bool srst_asserted = false;
990 LOG_DEBUG("target->state: %s", target_state_name(target));
992 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
993 /* allow scripts to override the reset event */
995 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
996 register_cache_invalidate(arc->core_and_aux_cache);
997 /* An ARC target might be in halt state after reset, so
998 * if script requested processor to resume, then it must
999 * be manually started to ensure that this request
1001 if (target->state == TARGET_HALTED && !target->reset_halt) {
1002 /* Resume the target and continue from the current
1003 * PC register value. */
1004 LOG_DEBUG("Starting CPU execution after reset");
1005 CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
1007 target->state = TARGET_RESET;
1012 /* some cores support connecting while srst is asserted
1013 * use that mode if it has been configured */
1014 if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
1015 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1016 jtag_add_reset(0, 1);
1017 srst_asserted = true;
1020 if (jtag_reset_config & RESET_HAS_SRST) {
1021 /* should issue a srst only, but we may have to assert trst as well */
1022 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1023 jtag_add_reset(1, 1);
1024 else if (!srst_asserted)
1025 jtag_add_reset(0, 1);
1028 target->state = TARGET_RESET;
1029 jtag_add_sleep(50000);
1031 register_cache_invalidate(arc->core_and_aux_cache);
1033 if (target->reset_halt)
1034 CHECK_RETVAL(target_halt(target));
1039 static int arc_deassert_reset(struct target *target)
1041 LOG_DEBUG("target->state: %s", target_state_name(target));
1043 /* deassert reset lines */
1044 jtag_add_reset(0, 0);
1049 static int arc_arch_state(struct target *target)
1053 if (debug_level < LOG_LVL_DEBUG)
1056 CHECK_RETVAL(arc_get_register_value(target, "pc", &pc_value));
1058 LOG_DEBUG("target state: %s; PC at: 0x%08" PRIx32,
1059 target_state_name(target),
1066 * See arc_save_context() for reason why we want to dump all regs at once.
1067 * This however means that if there are dependencies between registers they
1068 * will not be observable until target will be resumed.
1070 static int arc_restore_context(struct target *target)
1072 int retval = ERROR_OK;
1074 struct arc_common *arc = target_to_arc(target);
1075 struct reg *reg_list = arc->core_and_aux_cache->reg_list;
1077 LOG_DEBUG("Restoring registers values");
1080 const uint32_t core_regs_size = arc->num_core_regs * sizeof(uint32_t);
1081 const uint32_t aux_regs_size = arc->num_aux_regs * sizeof(uint32_t);
1082 uint32_t *core_values = malloc(core_regs_size);
1083 uint32_t *aux_values = malloc(aux_regs_size);
1084 uint32_t *core_addrs = malloc(core_regs_size);
1085 uint32_t *aux_addrs = malloc(aux_regs_size);
1086 unsigned int core_cnt = 0;
1087 unsigned int aux_cnt = 0;
1089 if (!core_values || !core_addrs || !aux_values || !aux_addrs) {
1090 LOG_ERROR("Unable to allocate memory");
1091 retval = ERROR_FAIL;
1095 memset(core_values, 0xff, core_regs_size);
1096 memset(core_addrs, 0xff, core_regs_size);
1097 memset(aux_values, 0xff, aux_regs_size);
1098 memset(aux_addrs, 0xff, aux_regs_size);
1100 for (i = 0; i < arc->num_core_regs; i++) {
1101 struct reg *reg = &(reg_list[i]);
1102 struct arc_reg_desc *arc_reg = reg->arch_info;
1103 if (reg->valid && reg->exist && reg->dirty) {
1104 LOG_DEBUG("Will write regnum=%u", i);
1105 core_addrs[core_cnt] = arc_reg->arch_num;
1106 core_values[core_cnt] = target_buffer_get_u32(target, reg->value);
1111 for (i = 0; i < arc->num_aux_regs; i++) {
1112 struct reg *reg = &(reg_list[arc->num_core_regs + i]);
1113 struct arc_reg_desc *arc_reg = reg->arch_info;
1114 if (reg->valid && reg->exist && reg->dirty) {
1115 LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i);
1116 aux_addrs[aux_cnt] = arc_reg->arch_num;
1117 aux_values[aux_cnt] = target_buffer_get_u32(target, reg->value);
1122 /* Write data to target.
1123 * Check before write, if aux and core count is greater than 0. */
1125 retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
1126 if (ERROR_OK != retval) {
1127 LOG_ERROR("Attempt to write to core registers failed.");
1128 retval = ERROR_FAIL;
1134 retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
1135 if (ERROR_OK != retval) {
1136 LOG_ERROR("Attempt to write to aux registers failed.");
1137 retval = ERROR_FAIL;
1151 static int arc_enable_interrupts(struct target *target, int enable)
1155 struct arc_common *arc = target_to_arc(target);
1157 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
1160 /* enable interrupts */
1161 value |= SET_CORE_ENABLE_INTERRUPTS;
1162 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1163 LOG_DEBUG("interrupts enabled");
1165 /* disable interrupts */
1166 value &= ~SET_CORE_ENABLE_INTERRUPTS;
1167 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1168 LOG_DEBUG("interrupts disabled");
1174 static int arc_resume(struct target *target, int current, target_addr_t address,
1175 int handle_breakpoints, int debug_execution)
1177 struct arc_common *arc = target_to_arc(target);
1178 uint32_t resume_pc = 0;
1180 struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache];
1182 LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints(not supported yet):%i,"
1183 " debug_execution:%i", current, address, handle_breakpoints, debug_execution);
1185 /* We need to reset ARC cache variables so caches
1186 * would be invalidated and actual data
1187 * would be fetched from memory. */
1188 CHECK_RETVAL(arc_reset_caches_states(target));
1190 if (target->state != TARGET_HALTED) {
1191 LOG_WARNING("target not halted");
1192 return ERROR_TARGET_NOT_HALTED;
1195 /* current = 1: continue on current PC, otherwise continue at <address> */
1197 target_buffer_set_u32(target, pc->value, address);
1200 LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
1204 resume_pc = address;
1206 resume_pc = target_buffer_get_u32(target, pc->value);
1208 CHECK_RETVAL(arc_restore_context(target));
1210 LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
1211 resume_pc, pc->dirty, pc->valid);
1213 /* check if GDB tells to set our PC where to continue from */
1214 if ((pc->valid == 1) && (resume_pc == target_buffer_get_u32(target, pc->value))) {
1215 value = target_buffer_get_u32(target, pc->value);
1216 LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
1217 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
1220 /* Restore IRQ state if not in debug_execution*/
1221 if (!debug_execution)
1222 CHECK_RETVAL(arc_enable_interrupts(target, arc->irq_state));
1224 CHECK_RETVAL(arc_enable_interrupts(target, !debug_execution));
1226 target->debug_reason = DBG_REASON_NOTHALTED;
1228 /* ready to get us going again */
1229 target->state = TARGET_RUNNING;
1230 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
1231 value &= ~SET_CORE_HALT_BIT; /* clear the HALT bit */
1232 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1233 LOG_DEBUG("Core started to run");
1235 /* registers are now invalid */
1236 register_cache_invalidate(arc->core_and_aux_cache);
1238 if (!debug_execution) {
1239 target->state = TARGET_RUNNING;
1240 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
1241 LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc);
1243 target->state = TARGET_DEBUG_RUNNING;
1244 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED));
1245 LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc);
1251 static int arc_init_target(struct command_context *cmd_ctx, struct target *target)
1253 CHECK_RETVAL(arc_build_reg_cache(target));
1254 CHECK_RETVAL(arc_build_bcr_reg_cache(target));
1255 target->debug_reason = DBG_REASON_DBGRQ;
1259 static void arc_free_reg_cache(struct reg_cache *cache)
1261 free(cache->reg_list);
1265 static void arc_deinit_target(struct target *target)
1267 struct arc_common *arc = target_to_arc(target);
1269 LOG_DEBUG("deinitialization of target");
1270 if (arc->core_aux_cache_built)
1271 arc_free_reg_cache(arc->core_and_aux_cache);
1272 if (arc->bcr_cache_built)
1273 arc_free_reg_cache(arc->bcr_cache);
1275 struct arc_reg_data_type *type, *n;
1276 struct arc_reg_desc *desc, *k;
1278 /* Free arc-specific reg_data_types allocations*/
1279 list_for_each_entry_safe_reverse(type, n, &arc->reg_data_types, list) {
1280 if (type->data_type.type_class == REG_TYPE_CLASS_STRUCT) {
1281 free(type->reg_type_struct_field);
1282 free(type->bitfields);
1284 } else if (type->data_type.type_class == REG_TYPE_CLASS_FLAGS) {
1285 free(type->reg_type_flags_field);
1286 free(type->bitfields);
1291 /* Free standard_gdb_types reg_data_types allocations */
1292 type = list_first_entry(&arc->reg_data_types, struct arc_reg_data_type, list);
1295 list_for_each_entry_safe(desc, k, &arc->aux_reg_descriptions, list)
1296 free_reg_desc(desc);
1298 list_for_each_entry_safe(desc, k, &arc->core_reg_descriptions, list)
1299 free_reg_desc(desc);
1301 list_for_each_entry_safe(desc, k, &arc->bcr_reg_descriptions, list)
1302 free_reg_desc(desc);
1308 static int arc_target_create(struct target *target, Jim_Interp *interp)
1310 struct arc_common *arc = calloc(1, sizeof(*arc));
1313 LOG_ERROR("Unable to allocate memory");
1317 LOG_DEBUG("Entering");
1318 CHECK_RETVAL(arc_init_arch_info(target, arc, target->tap));
1324 * Write 4-byte instruction to memory. This is like target_write_u32, however
1325 * in case of little endian ARC instructions are in middle endian format, not
1326 * little endian, so different type of conversion should be done.
1327 * Middle endinan: instruction "aabbccdd", stored as "bbaaddcc"
1329 int arc_write_instruction_u32(struct target *target, uint32_t address,
1332 uint8_t value_buf[4];
1333 if (!target_was_examined(target)) {
1334 LOG_ERROR("Target not examined yet");
1338 LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
1341 if (target->endianness == TARGET_LITTLE_ENDIAN)
1342 arc_h_u32_to_me(value_buf, instr);
1344 h_u32_to_be(value_buf, instr);
1346 CHECK_RETVAL(target_write_buffer(target, address, 4, value_buf));
1352 * Read 32-bit instruction from memory. It is like target_read_u32, however in
1353 * case of little endian ARC instructions are in middle endian format, so
1354 * different type of conversion should be done.
1356 int arc_read_instruction_u32(struct target *target, uint32_t address,
1359 uint8_t value_buf[4];
1361 if (!target_was_examined(target)) {
1362 LOG_ERROR("Target not examined yet");
1367 CHECK_RETVAL(target_read_buffer(target, address, 4, value_buf));
1369 if (target->endianness == TARGET_LITTLE_ENDIAN)
1370 *value = arc_me_to_h_u32(value_buf);
1372 *value = be_to_h_u32(value_buf);
1374 LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
1380 static int arc_set_breakpoint(struct target *target,
1381 struct breakpoint *breakpoint)
1384 if (breakpoint->set) {
1385 LOG_WARNING("breakpoint already set");
1389 if (breakpoint->type == BKPT_SOFT) {
1390 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
1392 if (breakpoint->length == 4) {
1393 uint32_t verify = 0xffffffff;
1395 CHECK_RETVAL(target_read_buffer(target, breakpoint->address, breakpoint->length,
1396 breakpoint->orig_instr));
1398 CHECK_RETVAL(arc_write_instruction_u32(target, breakpoint->address,
1401 CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &verify));
1403 if (verify != ARC_SDBBP_32) {
1404 LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
1405 " - check that memory is read/writable", breakpoint->address);
1408 } else if (breakpoint->length == 2) {
1409 uint16_t verify = 0xffff;
1411 CHECK_RETVAL(target_read_buffer(target, breakpoint->address, breakpoint->length,
1412 breakpoint->orig_instr));
1413 CHECK_RETVAL(target_write_u16(target, breakpoint->address, ARC_SDBBP_16));
1415 CHECK_RETVAL(target_read_u16(target, breakpoint->address, &verify));
1416 if (verify != ARC_SDBBP_16) {
1417 LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
1418 " - check that memory is read/writable", breakpoint->address);
1422 LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1423 return ERROR_COMMAND_ARGUMENT_INVALID;
1426 breakpoint->set = 64; /* Any nice value but 0 */
1427 } else if (breakpoint->type == BKPT_HARD) {
1428 LOG_DEBUG("Hardware breakpoints are not supported yet!");
1431 LOG_DEBUG("ERROR: setting unknown breakpoint type");
1435 /* core instruction cache is now invalid. */
1436 CHECK_RETVAL(arc_cache_invalidate(target));
1441 static int arc_unset_breakpoint(struct target *target,
1442 struct breakpoint *breakpoint)
1444 int retval = ERROR_OK;
1446 if (!breakpoint->set) {
1447 LOG_WARNING("breakpoint not set");
1451 if (breakpoint->type == BKPT_SOFT) {
1452 /* restore original instruction (kept in target endianness) */
1453 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
1454 if (breakpoint->length == 4) {
1455 uint32_t current_instr;
1457 /* check that user program has not modified breakpoint instruction */
1458 CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, ¤t_instr));
1460 if (current_instr == ARC_SDBBP_32) {
1461 retval = target_write_buffer(target, breakpoint->address,
1462 breakpoint->length, breakpoint->orig_instr);
1463 if (retval != ERROR_OK)
1466 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1467 " has been overwritten outside of debugger."
1468 "Expected: @0x%" PRIx32 ", got: @0x%" PRIx32,
1469 breakpoint->address, ARC_SDBBP_32, current_instr);
1471 } else if (breakpoint->length == 2) {
1472 uint16_t current_instr;
1474 /* check that user program has not modified breakpoint instruction */
1475 CHECK_RETVAL(target_read_u16(target, breakpoint->address, ¤t_instr));
1476 if (current_instr == ARC_SDBBP_16) {
1477 retval = target_write_buffer(target, breakpoint->address,
1478 breakpoint->length, breakpoint->orig_instr);
1479 if (retval != ERROR_OK)
1482 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1483 " has been overwritten outside of debugger. "
1484 "Expected: 0x%04x, got: 0x%04" PRIx16,
1485 breakpoint->address, ARC_SDBBP_16, current_instr);
1488 LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1489 return ERROR_COMMAND_ARGUMENT_INVALID;
1491 breakpoint->set = 0;
1493 } else if (breakpoint->type == BKPT_HARD) {
1494 LOG_WARNING("Hardware breakpoints are not supported yet!");
1497 LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
1501 /* core instruction cache is now invalid. */
1502 CHECK_RETVAL(arc_cache_invalidate(target));
1508 static int arc_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1510 if (target->state == TARGET_HALTED) {
1511 return arc_set_breakpoint(target, breakpoint);
1514 LOG_WARNING(" > core was not halted, please try again.");
1515 return ERROR_TARGET_NOT_HALTED;
1519 static int arc_remove_breakpoint(struct target *target,
1520 struct breakpoint *breakpoint)
1522 if (target->state == TARGET_HALTED) {
1523 if (breakpoint->set)
1524 CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
1526 LOG_WARNING("target not halted");
1527 return ERROR_TARGET_NOT_HALTED;
1533 /* Helper function which swiches core to single_step mode by
1534 * doing aux r/w operations. */
1535 int arc_config_step(struct target *target, int enable_step)
1539 struct arc_common *arc = target_to_arc(target);
1541 /* enable core debug step mode */
1543 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
1545 value &= ~SET_CORE_AE_BIT; /* clear the AE bit */
1546 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
1548 LOG_DEBUG(" [status32:0x%08" PRIx32 "]", value);
1550 /* Doing read-modify-write, because DEBUG might contain manually set
1551 * bits like UB or ED, which should be preserved. */
1552 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info,
1553 AUX_DEBUG_REG, &value));
1554 value |= SET_CORE_SINGLE_INSTR_STEP; /* set the IS bit */
1555 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
1557 LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
1559 } else { /* disable core debug step mode */
1560 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
1562 value &= ~SET_CORE_SINGLE_INSTR_STEP; /* clear the IS bit */
1563 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
1565 LOG_DEBUG("core debug step mode disabled");
1571 int arc_step(struct target *target, int current, target_addr_t address,
1572 int handle_breakpoints)
1574 /* get pointers to arch-specific information */
1575 struct arc_common *arc = target_to_arc(target);
1576 struct breakpoint *breakpoint = NULL;
1577 struct reg *pc = &(arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache]);
1579 if (target->state != TARGET_HALTED) {
1580 LOG_WARNING("target not halted");
1581 return ERROR_TARGET_NOT_HALTED;
1584 /* current = 1: continue on current pc, otherwise continue at <address> */
1586 buf_set_u32(pc->value, 0, 32, address);
1591 LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32,
1592 buf_get_u32(pc->value, 0, 32));
1594 /* the front-end may request us not to handle breakpoints */
1595 if (handle_breakpoints) {
1596 breakpoint = breakpoint_find(target, buf_get_u32(pc->value, 0, 32));
1598 CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
1601 /* restore context */
1602 CHECK_RETVAL(arc_restore_context(target));
1604 target->debug_reason = DBG_REASON_SINGLESTEP;
1606 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
1608 /* disable interrupts while stepping */
1609 CHECK_RETVAL(arc_enable_interrupts(target, 0));
1611 /* do a single step */
1612 CHECK_RETVAL(arc_config_step(target, 1));
1614 /* make sure we done our step */
1617 /* registers are now invalid */
1618 register_cache_invalidate(arc->core_and_aux_cache);
1621 CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
1623 LOG_DEBUG("target stepped ");
1625 target->state = TARGET_HALTED;
1627 /* Saving context */
1628 CHECK_RETVAL(arc_debug_entry(target));
1629 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1635 /* This function invalidates icache. */
1636 static int arc_icache_invalidate(struct target *target)
1640 struct arc_common *arc = target_to_arc(target);
1642 /* Don't waste time if already done. */
1643 if (!arc->has_icache || arc->icache_invalidated)
1646 LOG_DEBUG("Invalidating I$.");
1648 value = IC_IVIC_INVALIDATE; /* invalidate I$ */
1649 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value));
1651 arc->icache_invalidated = true;
1656 /* This function invalidates dcache */
1657 static int arc_dcache_invalidate(struct target *target)
1659 uint32_t value, dc_ctrl_value;
1661 struct arc_common *arc = target_to_arc(target);
1663 if (!arc->has_dcache || arc->dcache_invalidated)
1666 LOG_DEBUG("Invalidating D$.");
1668 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value));
1669 dc_ctrl_value = value;
1670 value &= ~DC_CTRL_IM;
1672 /* set DC_CTRL invalidate mode to invalidate-only (no flushing!!) */
1673 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
1674 value = DC_IVDC_INVALIDATE; /* invalidate D$ */
1675 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
1677 /* restore DC_CTRL invalidate mode */
1678 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
1680 arc->dcache_invalidated = true;
1685 /* This function invalidates l2 cache. */
1686 static int arc_l2cache_invalidate(struct target *target)
1688 uint32_t value, slc_ctrl_value;
1690 struct arc_common *arc = target_to_arc(target);
1692 if (!arc->has_l2cache || arc->l2cache_invalidated)
1695 LOG_DEBUG("Invalidating L2$.");
1697 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
1698 slc_ctrl_value = value;
1699 value &= ~L2_CTRL_IM;
1701 /* set L2_CTRL invalidate mode to invalidate-only (no flushing!!) */
1702 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, value));
1703 /* invalidate L2$ */
1704 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_INV, L2_INV_IV));
1706 /* Wait until invalidate operation ends */
1708 LOG_DEBUG("Waiting for invalidation end.");
1709 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
1710 } while (value & L2_CTRL_BS);
1712 /* restore L2_CTRL invalidate mode */
1713 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, slc_ctrl_value));
1715 arc->l2cache_invalidated = true;
1721 int arc_cache_invalidate(struct target *target)
1723 CHECK_RETVAL(arc_icache_invalidate(target));
1724 CHECK_RETVAL(arc_dcache_invalidate(target));
1725 CHECK_RETVAL(arc_l2cache_invalidate(target));
1730 /* Flush data cache. This function is cheap to call and return quickly if D$
1731 * already has been flushed since target had been halted. JTAG debugger reads
1732 * values directly from memory, bypassing cache, so if there are unflushed
1733 * lines debugger will read invalid values, which will cause a lot of troubles.
1735 int arc_dcache_flush(struct target *target)
1737 uint32_t value, dc_ctrl_value;
1738 bool has_to_set_dc_ctrl_im;
1740 struct arc_common *arc = target_to_arc(target);
1742 /* Don't waste time if already done. */
1743 if (!arc->has_dcache || arc->dcache_flushed)
1746 LOG_DEBUG("Flushing D$.");
1748 /* Store current value of DC_CTRL */
1749 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value));
1751 /* Set DC_CTRL invalidate mode to flush (if not already set) */
1752 has_to_set_dc_ctrl_im = (dc_ctrl_value & DC_CTRL_IM) == 0;
1753 if (has_to_set_dc_ctrl_im) {
1754 value = dc_ctrl_value | DC_CTRL_IM;
1755 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
1759 value = DC_IVDC_INVALIDATE;
1760 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
1762 /* Restore DC_CTRL invalidate mode (even of flush failed) */
1763 if (has_to_set_dc_ctrl_im)
1764 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
1766 arc->dcache_flushed = true;
1771 /* This function flushes l2cache. */
1772 static int arc_l2cache_flush(struct target *target)
1776 struct arc_common *arc = target_to_arc(target);
1778 /* Don't waste time if already done. */
1779 if (!arc->has_l2cache || arc->l2cache_flushed)
1782 LOG_DEBUG("Flushing L2$.");
1784 /* Flush L2 cache */
1785 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL));
1787 /* Wait until flush operation ends */
1789 LOG_DEBUG("Waiting for flushing end.");
1790 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
1791 } while (value & L2_CTRL_BS);
1793 arc->l2cache_flushed = true;
1798 int arc_cache_flush(struct target *target)
1800 CHECK_RETVAL(arc_dcache_flush(target));
1801 CHECK_RETVAL(arc_l2cache_flush(target));
1807 struct target_type arcv2_target = {
1812 .arch_state = arc_arch_state,
1814 /* TODO That seems like something similiar to metaware hostlink, so perhaps
1815 * we can exploit this in the future. */
1816 .target_request_data = NULL,
1819 .resume = arc_resume,
1822 .assert_reset = arc_assert_reset,
1823 .deassert_reset = arc_deassert_reset,
1825 /* TODO Implement soft_reset_halt */
1826 .soft_reset_halt = NULL,
1828 .get_gdb_reg_list = arc_get_gdb_reg_list,
1830 .read_memory = arc_mem_read,
1831 .write_memory = arc_mem_write,
1832 .checksum_memory = NULL,
1833 .blank_check_memory = NULL,
1835 .add_breakpoint = arc_add_breakpoint,
1836 .add_context_breakpoint = NULL,
1837 .add_hybrid_breakpoint = NULL,
1838 .remove_breakpoint = arc_remove_breakpoint,
1839 .add_watchpoint = NULL,
1840 .remove_watchpoint = NULL,
1841 .hit_watchpoint = NULL,
1843 .run_algorithm = NULL,
1844 .start_algorithm = NULL,
1845 .wait_algorithm = NULL,
1847 .commands = arc_monitor_command_handlers,
1849 .target_create = arc_target_create,
1850 .init_target = arc_init_target,
1851 .deinit_target = arc_deinit_target,
1852 .examine = arc_examine,
1855 .read_phys_memory = NULL,
1856 .write_phys_memory = NULL,