1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 ***************************************************************************/
23 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
24 * link protocol used in cases where JTAG is not wanted. This is coupled to
25 * recent versions of ARM's "CoreSight" debug framework. This specific code
26 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
27 * understanding operation semantics, shared with the JTAG transport.
29 * Single-DAP support only.
31 * for details, see "ARM IHI 0031A"
32 * ARM Debug Interface v5 Architecture Specification
33 * especially section 5.3 for SWD protocol
35 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
36 * to JTAG. Boards may support one or both. There are also SWD-only chips,
37 * (using SW-DP not SWJ-DP).
39 * Even boards that also support JTAG can benefit from SWD support, because
40 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
41 * That is, trace access may require SWD support.
50 #include "arm_adi_v5.h"
51 #include <helper/time_support.h>
53 #include <transport/transport.h>
54 #include <jtag/interface.h>
58 /* YUK! - but this is currently a global.... */
59 extern struct jtag_interface *jtag_interface;
62 static void swd_finish_read(struct adiv5_dap *dap)
64 const struct swd_driver *swd = jtag_interface->swd;
65 if (dap->last_read != NULL) {
66 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
67 dap->last_read = NULL;
71 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
73 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
76 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
78 const struct swd_driver *swd = jtag_interface->swd;
81 swd->write_reg(swd_cmd(false, false, DP_ABORT),
82 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
85 static int swd_run_inner(struct adiv5_dap *dap)
87 const struct swd_driver *swd = jtag_interface->swd;
92 if (retval != ERROR_OK) {
94 dap->do_reconnect = true;
100 static int swd_connect(struct adiv5_dap *dap)
105 /* FIXME validate transport config ... is the
106 * configured DAP present (check IDCODE)?
107 * Is *only* one DAP configured?
112 /* Note, debugport_init() does setup too */
113 jtag_interface->swd->switch_seq(JTAG_TO_SWD);
115 /* Clear link state, including the SELECT cache. */
116 dap->do_reconnect = false;
117 dap->select = DP_SELECT_INVALID;
119 swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
121 /* force clear all sticky faults */
122 swd_clear_sticky_errors(dap);
124 status = swd_run_inner(dap);
126 if (status == ERROR_OK) {
127 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
128 dap->do_reconnect = false;
130 dap->do_reconnect = true;
135 static inline int check_sync(struct adiv5_dap *dap)
137 return do_sync ? swd_run_inner(dap) : ERROR_OK;
140 static int swd_check_reconnect(struct adiv5_dap *dap)
142 if (dap->do_reconnect)
143 return swd_connect(dap);
148 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
150 const struct swd_driver *swd = jtag_interface->swd;
153 swd->write_reg(swd_cmd(false, false, DP_ABORT),
154 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
155 return check_sync(dap);
158 /** Select the DP register bank matching bits 7:4 of reg. */
159 static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
161 /* Only register address 4 is banked. */
162 if ((reg & 0xf) != 4)
165 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
166 uint32_t sel = select_dp_bank
167 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
169 if (sel == dap->select)
174 swd_queue_dp_write(dap, DP_SELECT, sel);
177 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
180 const struct swd_driver *swd = jtag_interface->swd;
183 int retval = swd_check_reconnect(dap);
184 if (retval != ERROR_OK)
187 swd_queue_dp_bankselect(dap, reg);
188 swd->read_reg(swd_cmd(true, false, reg), data, 0);
190 return check_sync(dap);
193 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
196 const struct swd_driver *swd = jtag_interface->swd;
199 int retval = swd_check_reconnect(dap);
200 if (retval != ERROR_OK)
203 swd_finish_read(dap);
204 swd_queue_dp_bankselect(dap, reg);
205 swd->write_reg(swd_cmd(false, false, reg), data, 0);
207 return check_sync(dap);
210 /** Select the AP register bank matching bits 7:4 of reg. */
211 static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
213 struct adiv5_dap *dap = ap->dap;
214 uint32_t sel = ((uint32_t)ap->ap_num << 24)
216 | (dap->select & DP_SELECT_DPBANK);
218 if (sel == dap->select)
223 swd_queue_dp_write(dap, DP_SELECT, sel);
226 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
229 const struct swd_driver *swd = jtag_interface->swd;
232 struct adiv5_dap *dap = ap->dap;
234 int retval = swd_check_reconnect(dap);
235 if (retval != ERROR_OK)
238 swd_queue_ap_bankselect(ap, reg);
239 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
240 dap->last_read = data;
242 return check_sync(dap);
245 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
248 const struct swd_driver *swd = jtag_interface->swd;
251 struct adiv5_dap *dap = ap->dap;
253 int retval = swd_check_reconnect(dap);
254 if (retval != ERROR_OK)
257 swd_finish_read(dap);
258 swd_queue_ap_bankselect(ap, reg);
259 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
261 return check_sync(dap);
264 /** Executes all queued DAP operations. */
265 static int swd_run(struct adiv5_dap *dap)
267 swd_finish_read(dap);
268 return swd_run_inner(dap);
271 const struct dap_ops swd_dap_ops = {
272 .queue_dp_read = swd_queue_dp_read,
273 .queue_dp_write = swd_queue_dp_write,
274 .queue_ap_read = swd_queue_ap_read,
275 .queue_ap_write = swd_queue_ap_write,
276 .queue_ap_abort = swd_queue_ap_abort,
281 * This represents the bits which must be sent out on TMS/SWDIO to
282 * switch a DAP implemented using an SWJ-DP module into SWD mode.
283 * These bits are stored (and transmitted) LSB-first.
285 * See the DAP-Lite specification, section 2.2.5 for information
286 * about making the debug link select SWD or JTAG. (Similar info
287 * is in a few other ARM documents.)
289 static const uint8_t jtag2swd_bitseq[] = {
290 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
291 * putting both JTAG and SWD logic into reset state.
293 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
294 /* Switching sequence enables SWD and disables JTAG
295 * NOTE: bits in the DP's IDCODE may expose the need for
296 * an old/obsolete/deprecated sequence (0xb6 0xed).
299 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
300 * putting both JTAG and SWD logic into reset state.
302 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
306 * Put the debug link into SWD mode, if the target supports it.
307 * The link's initial mode may be either JTAG (for example,
308 * with SWJ-DP after reset) or SWD.
310 * @param target Enters SWD mode (if possible).
312 * Note that targets using the JTAG-DP do not support SWD, and that
313 * some targets which could otherwise support it may have have been
314 * configured to disable SWD signaling
316 * @return ERROR_OK or else a fault code.
318 int dap_to_swd(struct target *target)
320 struct arm *arm = target_to_arm(target);
324 LOG_ERROR("SWD mode is not available");
328 LOG_DEBUG("Enter SWD mode");
330 /* REVISIT it's ugly to need to make calls to a "jtag"
331 * subsystem if the link may not be in JTAG mode...
334 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
335 jtag2swd_bitseq, TAP_INVALID);
336 if (retval == ERROR_OK)
337 retval = jtag_execute_queue();
339 /* set up the DAP's ops vector for SWD mode. */
340 arm->dap->ops = &swd_dap_ops;
345 static const struct command_registration swd_commands[] = {
348 * Set up SWD and JTAG targets identically, unless/until
349 * infrastructure improves ... meanwhile, ignore all
350 * JTAG-specific stuff like IR length for SWD.
352 * REVISIT can we verify "just one SWD DAP" here/early?
355 .jim_handler = jim_jtag_newtap,
356 .mode = COMMAND_CONFIG,
357 .help = "declare a new SWD DAP"
359 COMMAND_REGISTRATION_DONE
362 static const struct command_registration swd_handlers[] = {
366 .help = "SWD command group",
367 .chain = swd_commands,
369 COMMAND_REGISTRATION_DONE
372 static int swd_select(struct command_context *ctx)
376 retval = register_commands(ctx, NULL, swd_handlers);
378 if (retval != ERROR_OK)
381 const struct swd_driver *swd = jtag_interface->swd;
383 /* be sure driver is in SWD mode; start
384 * with hardware default TRN (1), it can be changed later
386 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
387 LOG_DEBUG("no SWD driver?");
391 retval = swd->init();
392 if (retval != ERROR_OK) {
393 LOG_DEBUG("can't init SWD driver");
397 /* force DAP into SWD mode (not JTAG) */
398 /*retval = dap_to_swd(target);*/
400 if (ctx->current_target) {
401 /* force DAP into SWD mode (not JTAG) */
402 struct target *target = get_current_target(ctx);
403 retval = dap_to_swd(target);
409 static int swd_init(struct command_context *ctx)
411 struct target *target = get_current_target(ctx);
412 struct arm *arm = target_to_arm(target);
413 struct adiv5_dap *dap = arm->dap;
414 /* Force the DAP's ops vector for SWD mode.
415 * messy - is there a better way? */
416 arm->dap->ops = &swd_dap_ops;
418 return swd_connect(dap);
421 static struct transport swd_transport = {
423 .select = swd_select,
427 static void swd_constructor(void) __attribute__((constructor));
428 static void swd_constructor(void)
430 transport_register(&swd_transport);
433 /** Returns true if the current debug session
434 * is using SWD as its transport.
436 bool transport_is_swd(void)
438 return get_current_transport() == &swd_transport;