1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 ***************************************************************************/
21 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
22 * link protocol used in cases where JTAG is not wanted. This is coupled to
23 * recent versions of ARM's "CoreSight" debug framework. This specific code
24 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
25 * understanding operation semantics, shared with the JTAG transport.
27 * Single-DAP support only.
29 * for details, see "ARM IHI 0031A"
30 * ARM Debug Interface v5 Architecture Specification
31 * especially section 5.3 for SWD protocol
33 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
34 * to JTAG. Boards may support one or both. There are also SWD-only chips,
35 * (using SW-DP not SWJ-DP).
37 * Even boards that also support JTAG can benefit from SWD support, because
38 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
39 * That is, trace access may require SWD support.
48 #include "arm_adi_v5.h"
49 #include <helper/time_support.h>
51 #include <transport/transport.h>
52 #include <jtag/interface.h>
58 static void swd_finish_read(struct adiv5_dap *dap)
60 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
61 if (dap->last_read != NULL) {
62 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
63 dap->last_read = NULL;
67 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
69 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
72 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
74 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
77 swd->write_reg(swd_cmd(false, false, DP_ABORT),
78 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
81 static int swd_run_inner(struct adiv5_dap *dap)
83 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
88 if (retval != ERROR_OK) {
90 dap->do_reconnect = true;
96 static int swd_connect(struct adiv5_dap *dap)
98 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
99 uint32_t dpidr = 0xdeadbeef;
102 /* FIXME validate transport config ... is the
103 * configured DAP present (check IDCODE)?
104 * Is *only* one DAP configured?
109 /* Check if we should reset srst already when connecting, but not if reconnecting. */
110 if (!dap->do_reconnect) {
111 enum reset_types jtag_reset_config = jtag_get_reset_config();
113 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
114 if (jtag_reset_config & RESET_SRST_NO_GATING)
115 adapter_assert_reset();
117 LOG_WARNING("\'srst_nogate\' reset_config option is required");
122 int64_t timeout = timeval_ms() + 500;
125 /* Note, debugport_init() does setup too */
126 swd->switch_seq(JTAG_TO_SWD);
128 /* Clear link state, including the SELECT cache. */
129 dap->do_reconnect = false;
130 dap_invalidate_cache(dap);
132 status = swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
133 if (status == ERROR_OK) {
134 status = swd_run_inner(dap);
135 if (status == ERROR_OK)
141 } while (timeval_ms() < timeout);
143 if (status != ERROR_OK) {
144 LOG_ERROR("Error connecting DP: cannot read IDR");
148 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
151 dap->do_reconnect = false;
153 /* force clear all sticky faults */
154 swd_clear_sticky_errors(dap);
156 status = swd_run_inner(dap);
157 if (status != ERROR_WAIT)
162 } while (timeval_ms() < timeout);
165 * "A WAIT response must not be issued to the ...
166 * ... writes to the ABORT register"
167 * swd_clear_sticky_errors() writes to the ABORT register only.
169 * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
170 * in a corner case. Just try if ABORT resolves the problem.
172 if (status == ERROR_WAIT) {
173 LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
175 dap->do_reconnect = false;
177 swd->write_reg(swd_cmd(false, false, DP_ABORT),
178 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
179 status = swd_run_inner(dap);
182 if (status == ERROR_OK)
183 status = dap_dp_init(dap);
188 static int swd_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
190 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
193 return swd->switch_seq(seq);
196 static inline int check_sync(struct adiv5_dap *dap)
198 return do_sync ? swd_run_inner(dap) : ERROR_OK;
201 static int swd_check_reconnect(struct adiv5_dap *dap)
203 if (dap->do_reconnect)
204 return swd_connect(dap);
209 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
211 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
214 swd->write_reg(swd_cmd(false, false, DP_ABORT),
215 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
216 return check_sync(dap);
219 /** Select the DP register bank matching bits 7:4 of reg. */
220 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
222 /* Only register address 4 is banked. */
223 if ((reg & 0xf) != 4)
226 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
227 uint32_t sel = select_dp_bank
228 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
230 if (sel == dap->select)
235 int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
236 if (retval != ERROR_OK)
237 dap->select = DP_SELECT_INVALID;
242 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
245 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
248 int retval = swd_check_reconnect(dap);
249 if (retval != ERROR_OK)
252 retval = swd_queue_dp_bankselect(dap, reg);
253 if (retval != ERROR_OK)
256 swd->read_reg(swd_cmd(true, false, reg), data, 0);
258 return check_sync(dap);
261 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
264 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
267 int retval = swd_check_reconnect(dap);
268 if (retval != ERROR_OK)
271 swd_finish_read(dap);
272 if (reg == DP_SELECT) {
273 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
275 swd->write_reg(swd_cmd(false, false, reg), data, 0);
277 retval = check_sync(dap);
278 if (retval != ERROR_OK)
279 dap->select = DP_SELECT_INVALID;
284 retval = swd_queue_dp_bankselect(dap, reg);
285 if (retval != ERROR_OK)
288 swd->write_reg(swd_cmd(false, false, reg), data, 0);
290 return check_sync(dap);
293 /** Select the AP register bank matching bits 7:4 of reg. */
294 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
296 struct adiv5_dap *dap = ap->dap;
297 uint32_t sel = ((uint32_t)ap->ap_num << 24)
299 | (dap->select & DP_SELECT_DPBANK);
301 if (sel == dap->select)
306 int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
307 if (retval != ERROR_OK)
308 dap->select = DP_SELECT_INVALID;
313 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
316 struct adiv5_dap *dap = ap->dap;
317 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
320 int retval = swd_check_reconnect(dap);
321 if (retval != ERROR_OK)
324 retval = swd_queue_ap_bankselect(ap, reg);
325 if (retval != ERROR_OK)
328 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
329 dap->last_read = data;
331 return check_sync(dap);
334 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
337 struct adiv5_dap *dap = ap->dap;
338 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
341 int retval = swd_check_reconnect(dap);
342 if (retval != ERROR_OK)
345 swd_finish_read(dap);
346 retval = swd_queue_ap_bankselect(ap, reg);
347 if (retval != ERROR_OK)
350 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
352 return check_sync(dap);
355 /** Executes all queued DAP operations. */
356 static int swd_run(struct adiv5_dap *dap)
358 swd_finish_read(dap);
359 return swd_run_inner(dap);
362 /** Put the SWJ-DP back to JTAG mode */
363 static void swd_quit(struct adiv5_dap *dap)
365 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
367 swd->switch_seq(SWD_TO_JTAG);
368 /* flush the queue before exit */
372 const struct dap_ops swd_dap_ops = {
373 .connect = swd_connect,
374 .send_sequence = swd_send_sequence,
375 .queue_dp_read = swd_queue_dp_read,
376 .queue_dp_write = swd_queue_dp_write,
377 .queue_ap_read = swd_queue_ap_read,
378 .queue_ap_write = swd_queue_ap_write,
379 .queue_ap_abort = swd_queue_ap_abort,
384 static const struct command_registration swd_commands[] = {
387 * Set up SWD and JTAG targets identically, unless/until
388 * infrastructure improves ... meanwhile, ignore all
389 * JTAG-specific stuff like IR length for SWD.
391 * REVISIT can we verify "just one SWD DAP" here/early?
394 .jim_handler = jim_jtag_newtap,
395 .mode = COMMAND_CONFIG,
396 .help = "declare a new SWD DAP"
398 COMMAND_REGISTRATION_DONE
401 static const struct command_registration swd_handlers[] = {
405 .help = "SWD command group",
406 .chain = swd_commands,
409 COMMAND_REGISTRATION_DONE
412 static int swd_select(struct command_context *ctx)
414 /* FIXME: only place where global 'adapter_driver' is still needed */
415 extern struct adapter_driver *adapter_driver;
416 const struct swd_driver *swd = adapter_driver->swd_ops;
419 retval = register_commands(ctx, NULL, swd_handlers);
420 if (retval != ERROR_OK)
423 /* be sure driver is in SWD mode; start
424 * with hardware default TRN (1), it can be changed later
426 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
427 LOG_DEBUG("no SWD driver?");
431 retval = swd->init();
432 if (retval != ERROR_OK) {
433 LOG_DEBUG("can't init SWD driver");
440 static int swd_init(struct command_context *ctx)
442 /* nothing done here, SWD is initialized
443 * together with the DAP */
447 static struct transport swd_transport = {
449 .select = swd_select,
453 static void swd_constructor(void) __attribute__((constructor));
454 static void swd_constructor(void)
456 transport_register(&swd_transport);
459 /** Returns true if the current debug session
460 * is using SWD as its transport.
462 bool transport_is_swd(void)
464 return get_current_transport() == &swd_transport;