1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 ***************************************************************************/
21 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
22 * link protocol used in cases where JTAG is not wanted. This is coupled to
23 * recent versions of ARM's "CoreSight" debug framework. This specific code
24 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
25 * understanding operation semantics, shared with the JTAG transport.
27 * Single-DAP support only.
29 * for details, see "ARM IHI 0031A"
30 * ARM Debug Interface v5 Architecture Specification
31 * especially section 5.3 for SWD protocol
33 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
34 * to JTAG. Boards may support one or both. There are also SWD-only chips,
35 * (using SW-DP not SWJ-DP).
37 * Even boards that also support JTAG can benefit from SWD support, because
38 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
39 * That is, trace access may require SWD support.
48 #include "arm_adi_v5.h"
49 #include <helper/time_support.h>
51 #include <transport/transport.h>
52 #include <jtag/interface.h>
58 static void swd_finish_read(struct adiv5_dap *dap)
60 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
61 if (dap->last_read != NULL) {
62 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
63 dap->last_read = NULL;
67 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
69 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
72 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
74 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
77 swd->write_reg(swd_cmd(false, false, DP_ABORT),
78 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
81 static int swd_run_inner(struct adiv5_dap *dap)
83 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
88 if (retval != ERROR_OK) {
90 dap->do_reconnect = true;
96 static int swd_connect(struct adiv5_dap *dap)
98 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
99 uint32_t dpidr = 0xdeadbeef;
102 /* FIXME validate transport config ... is the
103 * configured DAP present (check IDCODE)?
104 * Is *only* one DAP configured?
109 /* Check if we should reset srst already when connecting, but not if reconnecting. */
110 if (!dap->do_reconnect) {
111 enum reset_types jtag_reset_config = jtag_get_reset_config();
113 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
114 if (jtag_reset_config & RESET_SRST_NO_GATING)
115 adapter_assert_reset();
117 LOG_WARNING("\'srst_nogate\' reset_config option is required");
121 /* Note, debugport_init() does setup too */
122 swd->switch_seq(JTAG_TO_SWD);
124 /* Clear link state, including the SELECT cache. */
125 dap->do_reconnect = false;
126 dap_invalidate_cache(dap);
128 swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
130 /* force clear all sticky faults */
131 swd_clear_sticky_errors(dap);
133 status = swd_run_inner(dap);
135 if (status == ERROR_OK) {
136 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
137 dap->do_reconnect = false;
138 status = dap_dp_init(dap);
140 dap->do_reconnect = true;
145 static int swd_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
147 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
150 return swd->switch_seq(seq);
153 static inline int check_sync(struct adiv5_dap *dap)
155 return do_sync ? swd_run_inner(dap) : ERROR_OK;
158 static int swd_check_reconnect(struct adiv5_dap *dap)
160 if (dap->do_reconnect)
161 return swd_connect(dap);
166 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
168 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
171 swd->write_reg(swd_cmd(false, false, DP_ABORT),
172 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
173 return check_sync(dap);
176 /** Select the DP register bank matching bits 7:4 of reg. */
177 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
179 /* Only register address 4 is banked. */
180 if ((reg & 0xf) != 4)
183 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
184 uint32_t sel = select_dp_bank
185 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
187 if (sel == dap->select)
192 int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
193 if (retval != ERROR_OK)
194 dap->select = DP_SELECT_INVALID;
199 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
202 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
205 int retval = swd_check_reconnect(dap);
206 if (retval != ERROR_OK)
209 retval = swd_queue_dp_bankselect(dap, reg);
210 if (retval != ERROR_OK)
213 swd->read_reg(swd_cmd(true, false, reg), data, 0);
215 return check_sync(dap);
218 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
221 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
224 int retval = swd_check_reconnect(dap);
225 if (retval != ERROR_OK)
228 swd_finish_read(dap);
229 if (reg == DP_SELECT) {
230 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
232 swd->write_reg(swd_cmd(false, false, reg), data, 0);
234 retval = check_sync(dap);
235 if (retval != ERROR_OK)
236 dap->select = DP_SELECT_INVALID;
241 retval = swd_queue_dp_bankselect(dap, reg);
242 if (retval != ERROR_OK)
245 swd->write_reg(swd_cmd(false, false, reg), data, 0);
247 return check_sync(dap);
250 /** Select the AP register bank matching bits 7:4 of reg. */
251 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
253 struct adiv5_dap *dap = ap->dap;
254 uint32_t sel = ((uint32_t)ap->ap_num << 24)
256 | (dap->select & DP_SELECT_DPBANK);
258 if (sel == dap->select)
263 int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
264 if (retval != ERROR_OK)
265 dap->select = DP_SELECT_INVALID;
270 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
273 struct adiv5_dap *dap = ap->dap;
274 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
277 int retval = swd_check_reconnect(dap);
278 if (retval != ERROR_OK)
281 retval = swd_queue_ap_bankselect(ap, reg);
282 if (retval != ERROR_OK)
285 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
286 dap->last_read = data;
288 return check_sync(dap);
291 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
294 struct adiv5_dap *dap = ap->dap;
295 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
298 int retval = swd_check_reconnect(dap);
299 if (retval != ERROR_OK)
302 swd_finish_read(dap);
303 retval = swd_queue_ap_bankselect(ap, reg);
304 if (retval != ERROR_OK)
307 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
309 return check_sync(dap);
312 /** Executes all queued DAP operations. */
313 static int swd_run(struct adiv5_dap *dap)
315 swd_finish_read(dap);
316 return swd_run_inner(dap);
319 /** Put the SWJ-DP back to JTAG mode */
320 static void swd_quit(struct adiv5_dap *dap)
322 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
324 swd->switch_seq(SWD_TO_JTAG);
325 /* flush the queue before exit */
329 const struct dap_ops swd_dap_ops = {
330 .connect = swd_connect,
331 .send_sequence = swd_send_sequence,
332 .queue_dp_read = swd_queue_dp_read,
333 .queue_dp_write = swd_queue_dp_write,
334 .queue_ap_read = swd_queue_ap_read,
335 .queue_ap_write = swd_queue_ap_write,
336 .queue_ap_abort = swd_queue_ap_abort,
341 static const struct command_registration swd_commands[] = {
344 * Set up SWD and JTAG targets identically, unless/until
345 * infrastructure improves ... meanwhile, ignore all
346 * JTAG-specific stuff like IR length for SWD.
348 * REVISIT can we verify "just one SWD DAP" here/early?
351 .jim_handler = jim_jtag_newtap,
352 .mode = COMMAND_CONFIG,
353 .help = "declare a new SWD DAP"
355 COMMAND_REGISTRATION_DONE
358 static const struct command_registration swd_handlers[] = {
362 .help = "SWD command group",
363 .chain = swd_commands,
366 COMMAND_REGISTRATION_DONE
369 static int swd_select(struct command_context *ctx)
371 /* FIXME: only place where global 'adapter_driver' is still needed */
372 extern struct adapter_driver *adapter_driver;
373 const struct swd_driver *swd = adapter_driver->swd_ops;
376 retval = register_commands(ctx, NULL, swd_handlers);
377 if (retval != ERROR_OK)
380 /* be sure driver is in SWD mode; start
381 * with hardware default TRN (1), it can be changed later
383 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
384 LOG_DEBUG("no SWD driver?");
388 retval = swd->init();
389 if (retval != ERROR_OK) {
390 LOG_DEBUG("can't init SWD driver");
397 static int swd_init(struct command_context *ctx)
399 /* nothing done here, SWD is initialized
400 * together with the DAP */
404 static struct transport swd_transport = {
406 .select = swd_select,
410 static void swd_constructor(void) __attribute__((constructor));
411 static void swd_constructor(void)
413 transport_register(&swd_transport);
416 /** Returns true if the current debug session
417 * is using SWD as its transport.
419 bool transport_is_swd(void)
421 return get_current_transport() == &swd_transport;