1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 ***************************************************************************/
23 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
24 * link protocol used in cases where JTAG is not wanted. This is coupled to
25 * recent versions of ARM's "CoreSight" debug framework. This specific code
26 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
27 * understanding operation semantics, shared with the JTAG transport.
29 * Single-DAP support only.
31 * for details, see "ARM IHI 0031A"
32 * ARM Debug Interface v5 Architecture Specification
33 * especially section 5.3 for SWD protocol
35 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
36 * to JTAG. Boards may support one or both. There are also SWD-only chips,
37 * (using SW-DP not SWJ-DP).
39 * Even boards that also support JTAG can benefit from SWD support, because
40 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
41 * That is, trace access may require SWD support.
50 #include "arm_adi_v5.h"
51 #include <helper/time_support.h>
53 #include <transport/transport.h>
54 #include <jtag/interface.h>
58 /* YUK! - but this is currently a global.... */
59 extern struct jtag_interface *jtag_interface;
61 static int swd_finish_read(struct adiv5_dap *dap)
63 const struct swd_driver *swd = jtag_interface->swd;
64 int retval = ERROR_OK;
65 if (dap->last_read != NULL) {
66 retval = swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read);
67 dap->last_read = NULL;
72 static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
75 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
77 const struct swd_driver *swd = jtag_interface->swd;
80 return swd->write_reg(swd_cmd(false, false, DP_ABORT),
81 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
84 /** Select the DP register bank matching bits 7:4 of reg. */
85 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
87 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
92 if (select_dp_bank == dap->dp_bank_value)
95 dap->dp_bank_value = select_dp_bank;
96 select_dp_bank |= dap->ap_current | dap->ap_bank_value;
98 return swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
101 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
105 /* REVISIT status return vs ack ... */
106 const struct swd_driver *swd = jtag_interface->swd;
109 retval = swd_queue_dp_bankselect(dap, reg);
110 if (retval != ERROR_OK)
113 retval = swd->read_reg(swd_cmd(true, false, reg), data);
115 if (retval != ERROR_OK) {
117 uint8_t ack = retval & 0xff;
118 swd_queue_ap_abort(dap, &ack);
124 static int swd_queue_idcode_read(struct adiv5_dap *dap,
125 uint8_t *ack, uint32_t *data)
127 int status = swd_queue_dp_read(dap, DP_IDCODE, data);
135 static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
139 /* REVISIT status return vs ack ... */
140 const struct swd_driver *swd = jtag_interface->swd;
143 retval = swd_finish_read(dap);
144 if (retval != ERROR_OK)
147 retval = swd_queue_dp_bankselect(dap, reg);
148 if (retval != ERROR_OK)
151 retval = swd->write_reg(swd_cmd(false, false, reg), data);
153 if (retval != ERROR_OK) {
155 uint8_t ack = retval & 0xff;
156 swd_queue_ap_abort(dap, &ack);
162 /** Select the AP register bank matching bits 7:4 of reg. */
163 static int swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
165 uint32_t select_ap_bank = reg & 0x000000F0;
167 if (select_ap_bank == dap->ap_bank_value)
170 dap->ap_bank_value = select_ap_bank;
171 select_ap_bank |= dap->ap_current | dap->dp_bank_value;
173 return swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
176 static int (swd_queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
179 /* REVISIT status return ... */
180 const struct swd_driver *swd = jtag_interface->swd;
183 int retval = swd_queue_ap_bankselect(dap, reg);
184 if (retval != ERROR_OK)
187 retval = swd->read_reg(swd_cmd(true, true, reg), dap->last_read);
188 dap->last_read = data;
190 if (retval != ERROR_OK) {
192 uint8_t ack = retval & 0xff;
193 swd_queue_ap_abort(dap, &ack);
200 static int (swd_queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
203 /* REVISIT status return ... */
204 const struct swd_driver *swd = jtag_interface->swd;
208 retval = swd_finish_read(dap);
209 if (retval != ERROR_OK)
212 retval = swd_queue_ap_bankselect(dap, reg);
213 if (retval != ERROR_OK)
216 retval = swd->write_reg(swd_cmd(false, true, reg), data);
218 if (retval != ERROR_OK) {
220 uint8_t ack = retval & 0xff;
221 swd_queue_ap_abort(dap, &ack);
227 /** Executes all queued DAP operations. */
228 static int swd_run(struct adiv5_dap *dap)
230 /* for now the SWD interface hard-wires a zero-size queue. */
232 int retval = swd_finish_read(dap);
234 /* FIXME but we still need to check and scrub
235 * any hardware errors ...
240 const struct dap_ops swd_dap_ops = {
243 .queue_idcode_read = swd_queue_idcode_read,
244 .queue_dp_read = swd_queue_dp_read,
245 .queue_dp_write = swd_queue_dp_write,
246 .queue_ap_read = swd_queue_ap_read,
247 .queue_ap_write = swd_queue_ap_write,
248 .queue_ap_abort = swd_queue_ap_abort,
253 * This represents the bits which must be sent out on TMS/SWDIO to
254 * switch a DAP implemented using an SWJ-DP module into SWD mode.
255 * These bits are stored (and transmitted) LSB-first.
257 * See the DAP-Lite specification, section 2.2.5 for information
258 * about making the debug link select SWD or JTAG. (Similar info
259 * is in a few other ARM documents.)
261 static const uint8_t jtag2swd_bitseq[] = {
262 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
263 * putting both JTAG and SWD logic into reset state.
265 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
266 /* Switching sequence enables SWD and disables JTAG
267 * NOTE: bits in the DP's IDCODE may expose the need for
268 * an old/obsolete/deprecated sequence (0xb6 0xed).
271 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
272 * putting both JTAG and SWD logic into reset state.
274 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
278 * Put the debug link into SWD mode, if the target supports it.
279 * The link's initial mode may be either JTAG (for example,
280 * with SWJ-DP after reset) or SWD.
282 * @param target Enters SWD mode (if possible).
284 * Note that targets using the JTAG-DP do not support SWD, and that
285 * some targets which could otherwise support it may have have been
286 * configured to disable SWD signaling
288 * @return ERROR_OK or else a fault code.
290 int dap_to_swd(struct target *target)
292 struct arm *arm = target_to_arm(target);
295 LOG_DEBUG("Enter SWD mode");
297 /* REVISIT it's ugly to need to make calls to a "jtag"
298 * subsystem if the link may not be in JTAG mode...
301 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
302 jtag2swd_bitseq, TAP_INVALID);
303 if (retval == ERROR_OK)
304 retval = jtag_execute_queue();
306 /* set up the DAP's ops vector for SWD mode. */
307 arm->dap->ops = &swd_dap_ops;
312 COMMAND_HANDLER(handle_swd_wcr)
315 struct target *target = get_current_target(CMD_CTX);
316 struct arm *arm = target_to_arm(target);
317 struct adiv5_dap *dap = arm->dap;
319 unsigned trn, scale = 0;
322 /* no-args: just dump state */
324 /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
325 retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
326 if (retval == ERROR_OK)
328 if (retval != ERROR_OK) {
329 LOG_ERROR("can't read WCR?");
333 command_print(CMD_CTX,
334 "turnaround=%" PRIu32 ", prescale=%" PRIu32,
336 WCR_TO_PRESCALE(wcr));
339 case 2: /* TRN and prescale */
340 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], scale);
342 LOG_ERROR("prescale %d is too big", scale);
347 case 1: /* TRN only */
348 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], trn);
349 if (trn < 1 || trn > 4) {
350 LOG_ERROR("turnaround %d is invalid", trn);
354 wcr = ((trn - 1) << 8) | scale;
357 * then, re-init adapter with new TRN
359 LOG_ERROR("can't yet modify WCR");
362 default: /* too many arguments */
363 return ERROR_COMMAND_SYNTAX_ERROR;
367 static const struct command_registration swd_commands[] = {
370 * Set up SWD and JTAG targets identically, unless/until
371 * infrastructure improves ... meanwhile, ignore all
372 * JTAG-specific stuff like IR length for SWD.
374 * REVISIT can we verify "just one SWD DAP" here/early?
377 .jim_handler = jim_jtag_newtap,
378 .mode = COMMAND_CONFIG,
379 .help = "declare a new SWD DAP"
383 .handler = handle_swd_wcr,
385 .help = "display or update DAP's WCR register",
386 .usage = "turnaround (1..4), prescale (0..7)",
389 /* REVISIT -- add a command for SWV trace on/off */
390 COMMAND_REGISTRATION_DONE
393 static const struct command_registration swd_handlers[] = {
397 .help = "SWD command group",
398 .chain = swd_commands,
400 COMMAND_REGISTRATION_DONE
403 static int swd_select(struct command_context *ctx)
407 retval = register_commands(ctx, NULL, swd_handlers);
409 if (retval != ERROR_OK)
412 const struct swd_driver *swd = jtag_interface->swd;
414 /* be sure driver is in SWD mode; start
415 * with hardware default TRN (1), it can be changed later
417 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
418 LOG_DEBUG("no SWD driver?");
422 retval = swd->init(1);
423 if (retval != ERROR_OK) {
424 LOG_DEBUG("can't init SWD driver");
428 /* force DAP into SWD mode (not JTAG) */
429 /*retval = dap_to_swd(target);*/
431 if (ctx->current_target) {
432 /* force DAP into SWD mode (not JTAG) */
433 struct target *target = get_current_target(ctx);
434 retval = dap_to_swd(target);
440 static int swd_init(struct command_context *ctx)
442 struct target *target = get_current_target(ctx);
443 struct arm *arm = target_to_arm(target);
444 struct adiv5_dap *dap = arm->dap;
448 /* Force the DAP's ops vector for SWD mode.
449 * messy - is there a better way? */
450 arm->dap->ops = &swd_dap_ops;
452 /* FIXME validate transport config ... is the
453 * configured DAP present (check IDCODE)?
454 * Is *only* one DAP configured?
459 /* Note, debugport_init() does setup too */
463 status = swd_queue_idcode_read(dap, &ack, &idcode);
465 if (status == ERROR_OK)
466 LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
468 /* force clear all sticky faults */
469 swd_queue_ap_abort(dap, &ack);
471 /* this is a workaround to get polling working */
472 jtag_add_reset(0, 0);
477 static struct transport swd_transport = {
479 .select = swd_select,
483 static void swd_constructor(void) __attribute__((constructor));
484 static void swd_constructor(void)
486 transport_register(&swd_transport);
489 /** Returns true if the current debug session
490 * is using SWD as its transport.
492 bool transport_is_swd(void)
494 return get_current_transport() == &swd_transport;