git.gag.com Git - fw/openocd/blob - src/target/adi_v5_swd.c

   1 /***************************************************************************
   2  *
   3  *   Copyright (C) 2010 by David Brownell
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  ***************************************************************************/
  18
  19 /**
  20  * @file
  21  * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
  22  * link protocol used in cases where JTAG is not wanted.  This is coupled to
  23  * recent versions of ARM's "CoreSight" debug framework.  This specific code
  24  * is a transport level interface, with "target/arm_adi_v5.[hc]" code
  25  * understanding operation semantics, shared with the JTAG transport.
  26  *
  27  * Single-DAP support only.
  28  *
  29  * for details, see "ARM IHI 0031A"
  30  * ARM Debug Interface v5 Architecture Specification
  31  * especially section 5.3 for SWD protocol
  32  *
  33  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  34  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
  35  * (using SW-DP not SWJ-DP).
  36  *
  37  * Even boards that also support JTAG can benefit from SWD support, because
  38  * usually there's no way to access the SWO trace view mechanism in JTAG mode.
  39  * That is, trace access may require SWD support.
  40  *
  41  */
  42
  43 #ifdef HAVE_CONFIG_H
  44 #include "config.h"
  45 #endif
  46
  47 #include "arm.h"
  48 #include "arm_adi_v5.h"
  49 #include <helper/time_support.h>
  50
  51 #include <transport/transport.h>
  52 #include <jtag/interface.h>
  53
  54 #include <jtag/swd.h>
  55
  56 /* for debug, set do_sync to true to force synchronous transfers */
  57 static bool do_sync;
  58
  59 static struct adiv5_dap *swd_multidrop_selected_dap;
  60
  61
  62 static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
  63                 uint32_t data);
  64
  65
  66 static int swd_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
  67 {
  68         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  69         assert(swd);
  70
  71         return swd->switch_seq(seq);
  72 }
  73
  74 static void swd_finish_read(struct adiv5_dap *dap)
  75 {
  76         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  77         if (dap->last_read) {
  78                 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
  79                 dap->last_read = NULL;
  80         }
  81 }
  82
  83 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
  84 {
  85         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  86         assert(swd);
  87
  88         swd->write_reg(swd_cmd(false, false, DP_ABORT),
  89                 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
  90 }
  91
  92 static int swd_run_inner(struct adiv5_dap *dap)
  93 {
  94         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  95         int retval;
  96
  97         retval = swd->run();
  98
  99         if (retval != ERROR_OK) {
 100                 /* fault response */
 101                 dap->do_reconnect = true;
 102         }
 103
 104         return retval;
 105 }
 106
 107 static inline int check_sync(struct adiv5_dap *dap)
 108 {
 109         return do_sync ? swd_run_inner(dap) : ERROR_OK;
 110 }
 111
 112 /** Select the DP register bank matching bits 7:4 of reg. */
 113 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned int reg)
 114 {
 115         /* Only register address 4 is banked. */
 116         if ((reg & 0xf) != 4)
 117                 return ERROR_OK;
 118
 119         uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
 120         uint32_t sel = select_dp_bank
 121                         | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
 122
 123         if (sel == dap->select)
 124                 return ERROR_OK;
 125
 126         dap->select = sel;
 127
 128         int retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel);
 129         if (retval != ERROR_OK)
 130                 dap->select = DP_SELECT_INVALID;
 131
 132         return retval;
 133 }
 134
 135 static int swd_queue_dp_read_inner(struct adiv5_dap *dap, unsigned int reg,
 136                 uint32_t *data)
 137 {
 138         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 139         assert(swd);
 140
 141         int retval = swd_queue_dp_bankselect(dap, reg);
 142         if (retval != ERROR_OK)
 143                 return retval;
 144
 145         swd->read_reg(swd_cmd(true, false, reg), data, 0);
 146
 147         return check_sync(dap);
 148 }
 149
 150 static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
 151                 uint32_t data)
 152 {
 153         int retval;
 154         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 155         assert(swd);
 156
 157         swd_finish_read(dap);
 158
 159         if (reg == DP_SELECT) {
 160                 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
 161
 162                 swd->write_reg(swd_cmd(false, false, reg), data, 0);
 163
 164                 retval = check_sync(dap);
 165                 if (retval != ERROR_OK)
 166                         dap->select = DP_SELECT_INVALID;
 167
 168                 return retval;
 169         }
 170
 171         retval = swd_queue_dp_bankselect(dap, reg);
 172         if (retval != ERROR_OK)
 173                 return retval;
 174
 175         swd->write_reg(swd_cmd(false, false, reg), data, 0);
 176
 177         return check_sync(dap);
 178 }
 179
 180
 181 static int swd_multidrop_select_inner(struct adiv5_dap *dap, uint32_t *dpidr_ptr,
 182                 uint32_t *dlpidr_ptr, bool clear_sticky)
 183 {
 184         int retval;
 185         uint32_t dpidr, dlpidr;
 186
 187         assert(dap_is_multidrop(dap));
 188
 189         swd_send_sequence(dap, LINE_RESET);
 190
 191         retval = swd_queue_dp_write_inner(dap, DP_TARGETSEL, dap->multidrop_targetsel);
 192         if (retval != ERROR_OK)
 193                 return retval;
 194
 195         retval = swd_queue_dp_read_inner(dap, DP_DPIDR, &dpidr);
 196         if (retval != ERROR_OK)
 197                 return retval;
 198
 199         if (clear_sticky) {
 200                 /* Clear all sticky errors (including ORUN) */
 201                 swd_clear_sticky_errors(dap);
 202         } else {
 203                 /* Ideally just clear ORUN flag which is set by reset */
 204                 retval = swd_queue_dp_write_inner(dap, DP_ABORT, ORUNERRCLR);
 205                 if (retval != ERROR_OK)
 206                         return retval;
 207         }
 208
 209         retval = swd_queue_dp_read_inner(dap, DP_DLPIDR, &dlpidr);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212
 213         retval = swd_run_inner(dap);
 214         if (retval != ERROR_OK)
 215                 return retval;
 216
 217         if ((dpidr & DP_DPIDR_VERSION_MASK) < (2UL << DP_DPIDR_VERSION_SHIFT)) {
 218                 LOG_INFO("Read DPIDR 0x%08" PRIx32
 219                                  " has version < 2. A non multidrop capable device connected?",
 220                                  dpidr);
 221                 return ERROR_FAIL;
 222         }
 223
 224         /* TODO: check TARGETID if DLIPDR is same for more than one DP */
 225         uint32_t expected_dlpidr = DP_DLPIDR_PROTVSN |
 226                         (dap->multidrop_targetsel & DP_TARGETSEL_INSTANCEID_MASK);
 227         if (dlpidr != expected_dlpidr) {
 228                 LOG_INFO("Read incorrect DLPIDR 0x%08" PRIx32
 229                                  " (possibly CTRL/STAT value)",
 230                                  dlpidr);
 231                 return ERROR_FAIL;
 232         }
 233
 234         LOG_DEBUG_IO("Selected DP_TARGETSEL 0x%08" PRIx32, dap->multidrop_targetsel);
 235         swd_multidrop_selected_dap = dap;
 236
 237         if (dpidr_ptr)
 238                 *dpidr_ptr = dpidr;
 239
 240         if (dlpidr_ptr)
 241                 *dlpidr_ptr = dlpidr;
 242
 243         return retval;
 244 }
 245
 246 static int swd_multidrop_select(struct adiv5_dap *dap)
 247 {
 248         if (!dap_is_multidrop(dap))
 249                 return ERROR_OK;
 250
 251         if (swd_multidrop_selected_dap == dap)
 252                 return ERROR_OK;
 253
 254         int retval = ERROR_OK;
 255         for (unsigned int retry = 0; ; retry++) {
 256                 bool clear_sticky = retry > 0;
 257
 258                 retval = swd_multidrop_select_inner(dap, NULL, NULL, clear_sticky);
 259                 if (retval == ERROR_OK)
 260                         break;
 261
 262                 swd_multidrop_selected_dap = NULL;
 263                 if (retry > 3) {
 264                         LOG_ERROR("Failed to select multidrop %s", adiv5_dap_name(dap));
 265                         return retval;
 266                 }
 267
 268                 LOG_DEBUG("Failed to select multidrop %s, retrying...",
 269                                   adiv5_dap_name(dap));
 270         }
 271
 272         return retval;
 273 }
 274
 275 static int swd_connect_multidrop(struct adiv5_dap *dap)
 276 {
 277         int retval;
 278         uint32_t dpidr = 0xdeadbeef;
 279         uint32_t dlpidr = 0xdeadbeef;
 280         int64_t timeout = timeval_ms() + 500;
 281
 282         do {
 283                 swd_send_sequence(dap, JTAG_TO_DORMANT);
 284                 swd_send_sequence(dap, DORMANT_TO_SWD);
 285
 286                 /* Clear link state, including the SELECT cache. */
 287                 dap->do_reconnect = false;
 288                 dap_invalidate_cache(dap);
 289                 swd_multidrop_selected_dap = NULL;
 290
 291                 retval = swd_multidrop_select_inner(dap, &dpidr, &dlpidr, true);
 292                 if (retval == ERROR_OK)
 293                         break;
 294
 295                 alive_sleep(1);
 296
 297         } while (timeval_ms() < timeout);
 298
 299         if (retval != ERROR_OK) {
 300                 swd_multidrop_selected_dap = NULL;
 301                 LOG_ERROR("Failed to connect multidrop %s", adiv5_dap_name(dap));
 302                 return retval;
 303         }
 304
 305         LOG_INFO("SWD DPIDR 0x%08" PRIx32 ", DLPIDR 0x%08" PRIx32,
 306                           dpidr, dlpidr);
 307
 308         return retval;
 309 }
 310
 311 static int swd_connect_single(struct adiv5_dap *dap)
 312 {
 313         int retval;
 314         uint32_t dpidr = 0xdeadbeef;
 315         int64_t timeout = timeval_ms() + 500;
 316
 317         do {
 318                 if (dap->switch_through_dormant) {
 319                         swd_send_sequence(dap, JTAG_TO_DORMANT);
 320                         swd_send_sequence(dap, DORMANT_TO_SWD);
 321                 } else {
 322                         swd_send_sequence(dap, JTAG_TO_SWD);
 323                 }
 324
 325                 /* Clear link state, including the SELECT cache. */
 326                 dap->do_reconnect = false;
 327                 dap_invalidate_cache(dap);
 328
 329                 retval = swd_queue_dp_read_inner(dap, DP_DPIDR, &dpidr);
 330                 if (retval == ERROR_OK) {
 331                         retval = swd_run_inner(dap);
 332                         if (retval == ERROR_OK)
 333                                 break;
 334                 }
 335
 336                 alive_sleep(1);
 337
 338                 dap->switch_through_dormant = !dap->switch_through_dormant;
 339         } while (timeval_ms() < timeout);
 340
 341         if (retval != ERROR_OK) {
 342                 LOG_ERROR("Error connecting DP: cannot read IDR");
 343                 return retval;
 344         }
 345
 346         LOG_INFO("SWD DPIDR 0x%08" PRIx32, dpidr);
 347
 348         do {
 349                 dap->do_reconnect = false;
 350
 351                 /* force clear all sticky faults */
 352                 swd_clear_sticky_errors(dap);
 353
 354                 retval = swd_run_inner(dap);
 355                 if (retval != ERROR_WAIT)
 356                         break;
 357
 358                 alive_sleep(10);
 359
 360         } while (timeval_ms() < timeout);
 361
 362         return retval;
 363 }
 364
 365 static int swd_connect(struct adiv5_dap *dap)
 366 {
 367         int status;
 368
 369         /* FIXME validate transport config ... is the
 370          * configured DAP present (check IDCODE)?
 371          */
 372
 373         /* Check if we should reset srst already when connecting, but not if reconnecting. */
 374         if (!dap->do_reconnect) {
 375                 enum reset_types jtag_reset_config = jtag_get_reset_config();
 376
 377                 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
 378                         if (jtag_reset_config & RESET_SRST_NO_GATING)
 379                                 adapter_assert_reset();
 380                         else
 381                                 LOG_WARNING("\'srst_nogate\' reset_config option is required");
 382                 }
 383         }
 384
 385         if (dap_is_multidrop(dap))
 386                 status = swd_connect_multidrop(dap);
 387         else
 388                 status = swd_connect_single(dap);
 389
 390         /* IHI 0031E B4.3.2:
 391          * "A WAIT response must not be issued to the ...
 392          * ... writes to the ABORT register"
 393          * swd_clear_sticky_errors() writes to the ABORT register only.
 394          *
 395          * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
 396          * in a corner case. Just try if ABORT resolves the problem.
 397          */
 398         if (status == ERROR_WAIT) {
 399                 LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
 400
 401                 dap->do_reconnect = false;
 402
 403                 status = swd_queue_dp_write_inner(dap, DP_ABORT,
 404                         DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
 405
 406                 if (status == ERROR_OK)
 407                         status = swd_run_inner(dap);
 408         }
 409
 410         if (status == ERROR_OK)
 411                 status = dap_dp_init(dap);
 412
 413         return status;
 414 }
 415
 416 static int swd_check_reconnect(struct adiv5_dap *dap)
 417 {
 418         if (dap->do_reconnect)
 419                 return swd_connect(dap);
 420
 421         return ERROR_OK;
 422 }
 423
 424 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 425 {
 426         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 427         assert(swd);
 428
 429         /* TODO: Send DAPABORT in swd_multidrop_select_inner()
 430          * in the case the multidrop dap is not selected?
 431          * swd_queue_ap_abort() is not currently used anyway...
 432          */
 433         int retval = swd_multidrop_select(dap);
 434         if (retval != ERROR_OK)
 435                 return retval;
 436
 437         swd->write_reg(swd_cmd(false, false, DP_ABORT),
 438                 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
 439         return check_sync(dap);
 440 }
 441
 442 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 443                 uint32_t *data)
 444 {
 445         int retval = swd_check_reconnect(dap);
 446         if (retval != ERROR_OK)
 447                 return retval;
 448
 449         retval = swd_multidrop_select(dap);
 450         if (retval != ERROR_OK)
 451                 return retval;
 452
 453         return swd_queue_dp_read_inner(dap, reg, data);
 454 }
 455
 456 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 457                 uint32_t data)
 458 {
 459         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 460         assert(swd);
 461
 462         int retval = swd_check_reconnect(dap);
 463         if (retval != ERROR_OK)
 464                 return retval;
 465
 466         retval = swd_multidrop_select(dap);
 467         if (retval != ERROR_OK)
 468                 return retval;
 469
 470         return swd_queue_dp_write_inner(dap, reg, data);
 471 }
 472
 473 /** Select the AP register bank matching bits 7:4 of reg. */
 474 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 475 {
 476         struct adiv5_dap *dap = ap->dap;
 477         uint32_t sel = ((uint32_t)ap->ap_num << 24)
 478                         | (reg & 0x000000F0)
 479                         | (dap->select & DP_SELECT_DPBANK);
 480
 481         if (sel == dap->select)
 482                 return ERROR_OK;
 483
 484         dap->select = sel;
 485
 486         int retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel);
 487         if (retval != ERROR_OK)
 488                 dap->select = DP_SELECT_INVALID;
 489
 490         return retval;
 491 }
 492
 493 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
 494                 uint32_t *data)
 495 {
 496         struct adiv5_dap *dap = ap->dap;
 497         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 498         assert(swd);
 499
 500         int retval = swd_check_reconnect(dap);
 501         if (retval != ERROR_OK)
 502                 return retval;
 503
 504         retval = swd_multidrop_select(dap);
 505         if (retval != ERROR_OK)
 506                 return retval;
 507
 508         retval = swd_queue_ap_bankselect(ap, reg);
 509         if (retval != ERROR_OK)
 510                 return retval;
 511
 512         swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
 513         dap->last_read = data;
 514
 515         return check_sync(dap);
 516 }
 517
 518 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
 519                 uint32_t data)
 520 {
 521         struct adiv5_dap *dap = ap->dap;
 522         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 523         assert(swd);
 524
 525         int retval = swd_check_reconnect(dap);
 526         if (retval != ERROR_OK)
 527                 return retval;
 528
 529         retval = swd_multidrop_select(dap);
 530         if (retval != ERROR_OK)
 531                 return retval;
 532
 533         swd_finish_read(dap);
 534
 535         retval = swd_queue_ap_bankselect(ap, reg);
 536         if (retval != ERROR_OK)
 537                 return retval;
 538
 539         swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
 540
 541         return check_sync(dap);
 542 }
 543
 544 /** Executes all queued DAP operations. */
 545 static int swd_run(struct adiv5_dap *dap)
 546 {
 547         int retval = swd_multidrop_select(dap);
 548         if (retval != ERROR_OK)
 549                 return retval;
 550
 551         swd_finish_read(dap);
 552
 553         return swd_run_inner(dap);
 554 }
 555
 556 /** Put the SWJ-DP back to JTAG mode */
 557 static void swd_quit(struct adiv5_dap *dap)
 558 {
 559         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 560         static bool done;
 561
 562         /* There is no difference if the sequence is sent at the last
 563          * or the first swd_quit() call, send it just once */
 564         if (done)
 565                 return;
 566
 567         done = true;
 568         if (dap_is_multidrop(dap)) {
 569                 swd->switch_seq(SWD_TO_DORMANT);
 570                 /* Revisit!
 571                  * Leaving DPs in dormant state was tested and offers some safety
 572                  * against DPs mismatch in case of unintentional use of non-multidrop SWD.
 573                  * To put SWJ-DPs to power-on state issue
 574                  * swd->switch_seq(DORMANT_TO_JTAG);
 575                  */
 576         } else {
 577                 if (dap->switch_through_dormant) {
 578                         swd->switch_seq(SWD_TO_DORMANT);
 579                         swd->switch_seq(DORMANT_TO_JTAG);
 580                 } else {
 581                         swd->switch_seq(SWD_TO_JTAG);
 582                 }
 583         }
 584
 585         /* flush the queue to shift out the sequence before exit */
 586         swd->run();
 587 }
 588
 589 const struct dap_ops swd_dap_ops = {
 590         .connect = swd_connect,
 591         .send_sequence = swd_send_sequence,
 592         .queue_dp_read = swd_queue_dp_read,
 593         .queue_dp_write = swd_queue_dp_write,
 594         .queue_ap_read = swd_queue_ap_read,
 595         .queue_ap_write = swd_queue_ap_write,
 596         .queue_ap_abort = swd_queue_ap_abort,
 597         .run = swd_run,
 598         .quit = swd_quit,
 599 };
 600
 601 static const struct command_registration swd_commands[] = {
 602         {
 603                 /*
 604                  * Set up SWD and JTAG targets identically, unless/until
 605                  * infrastructure improves ...  meanwhile, ignore all
 606                  * JTAG-specific stuff like IR length for SWD.
 607                  *
 608                  * REVISIT can we verify "just one SWD DAP" here/early?
 609                  */
 610                 .name = "newdap",
 611                 .jim_handler = jim_jtag_newtap,
 612                 .mode = COMMAND_CONFIG,
 613                 .help = "declare a new SWD DAP"
 614         },
 615         COMMAND_REGISTRATION_DONE
 616 };
 617
 618 static const struct command_registration swd_handlers[] = {
 619         {
 620                 .name = "swd",
 621                 .mode = COMMAND_ANY,
 622                 .help = "SWD command group",
 623                 .chain = swd_commands,
 624                 .usage = "",
 625         },
 626         COMMAND_REGISTRATION_DONE
 627 };
 628
 629 static int swd_select(struct command_context *ctx)
 630 {
 631         /* FIXME: only place where global 'adapter_driver' is still needed */
 632         extern struct adapter_driver *adapter_driver;
 633         const struct swd_driver *swd = adapter_driver->swd_ops;
 634         int retval;
 635
 636         retval = register_commands(ctx, NULL, swd_handlers);
 637         if (retval != ERROR_OK)
 638                 return retval;
 639
 640          /* be sure driver is in SWD mode; start
 641           * with hardware default TRN (1), it can be changed later
 642           */
 643         if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
 644                 LOG_DEBUG("no SWD driver?");
 645                 return ERROR_FAIL;
 646         }
 647
 648         retval = swd->init();
 649         if (retval != ERROR_OK) {
 650                 LOG_DEBUG("can't init SWD driver");
 651                 return retval;
 652         }
 653
 654         return retval;
 655 }
 656
 657 static int swd_init(struct command_context *ctx)
 658 {
 659         /* nothing done here, SWD is initialized
 660          * together with the DAP */
 661         return ERROR_OK;
 662 }
 663
 664 static struct transport swd_transport = {
 665         .name = "swd",
 666         .select = swd_select,
 667         .init = swd_init,
 668 };
 669
 670 static void swd_constructor(void) __attribute__((constructor));
 671 static void swd_constructor(void)
 672 {
 673         transport_register(&swd_transport);
 674 }
 675
 676 /** Returns true if the current debug session
 677  * is using SWD as its transport.
 678  */
 679 bool transport_is_swd(void)
 680 {
 681         return get_current_transport() == &swd_transport;
 682 }