1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 ***************************************************************************/
21 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
22 * link protocol used in cases where JTAG is not wanted. This is coupled to
23 * recent versions of ARM's "CoreSight" debug framework. This specific code
24 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
25 * understanding operation semantics, shared with the JTAG transport.
27 * Single-DAP support only.
29 * for details, see "ARM IHI 0031A"
30 * ARM Debug Interface v5 Architecture Specification
31 * especially section 5.3 for SWD protocol
33 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
34 * to JTAG. Boards may support one or both. There are also SWD-only chips,
35 * (using SW-DP not SWJ-DP).
37 * Even boards that also support JTAG can benefit from SWD support, because
38 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
39 * That is, trace access may require SWD support.
48 #include "arm_adi_v5.h"
49 #include <helper/time_support.h>
51 #include <transport/transport.h>
52 #include <jtag/interface.h>
56 /* YUK! - but this is currently a global.... */
57 extern struct jtag_interface *jtag_interface;
60 static void swd_finish_read(struct adiv5_dap *dap)
62 const struct swd_driver *swd = jtag_interface->swd;
63 if (dap->last_read != NULL) {
64 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
65 dap->last_read = NULL;
69 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
71 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
74 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
76 const struct swd_driver *swd = jtag_interface->swd;
79 swd->write_reg(swd_cmd(false, false, DP_ABORT),
80 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
83 static int swd_run_inner(struct adiv5_dap *dap)
85 const struct swd_driver *swd = jtag_interface->swd;
90 if (retval != ERROR_OK) {
92 dap->do_reconnect = true;
98 static int swd_connect(struct adiv5_dap *dap)
103 /* FIXME validate transport config ... is the
104 * configured DAP present (check IDCODE)?
105 * Is *only* one DAP configured?
110 /* Note, debugport_init() does setup too */
111 jtag_interface->swd->switch_seq(JTAG_TO_SWD);
113 /* Clear link state, including the SELECT cache. */
114 dap->do_reconnect = false;
115 dap->select = DP_SELECT_INVALID;
117 swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
119 /* force clear all sticky faults */
120 swd_clear_sticky_errors(dap);
122 status = swd_run_inner(dap);
124 if (status == ERROR_OK) {
125 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
126 dap->do_reconnect = false;
128 dap->do_reconnect = true;
133 static inline int check_sync(struct adiv5_dap *dap)
135 return do_sync ? swd_run_inner(dap) : ERROR_OK;
138 static int swd_check_reconnect(struct adiv5_dap *dap)
140 if (dap->do_reconnect)
141 return swd_connect(dap);
146 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
148 const struct swd_driver *swd = jtag_interface->swd;
151 swd->write_reg(swd_cmd(false, false, DP_ABORT),
152 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
153 return check_sync(dap);
156 /** Select the DP register bank matching bits 7:4 of reg. */
157 static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
159 /* Only register address 4 is banked. */
160 if ((reg & 0xf) != 4)
163 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
164 uint32_t sel = select_dp_bank
165 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
167 if (sel == dap->select)
172 swd_queue_dp_write(dap, DP_SELECT, sel);
175 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
178 const struct swd_driver *swd = jtag_interface->swd;
181 int retval = swd_check_reconnect(dap);
182 if (retval != ERROR_OK)
185 swd_queue_dp_bankselect(dap, reg);
186 swd->read_reg(swd_cmd(true, false, reg), data, 0);
188 return check_sync(dap);
191 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
194 const struct swd_driver *swd = jtag_interface->swd;
197 int retval = swd_check_reconnect(dap);
198 if (retval != ERROR_OK)
201 swd_finish_read(dap);
202 swd_queue_dp_bankselect(dap, reg);
203 swd->write_reg(swd_cmd(false, false, reg), data, 0);
205 return check_sync(dap);
208 /** Select the AP register bank matching bits 7:4 of reg. */
209 static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
211 struct adiv5_dap *dap = ap->dap;
212 uint32_t sel = ((uint32_t)ap->ap_num << 24)
214 | (dap->select & DP_SELECT_DPBANK);
216 if (sel == dap->select)
221 swd_queue_dp_write(dap, DP_SELECT, sel);
224 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
227 const struct swd_driver *swd = jtag_interface->swd;
230 struct adiv5_dap *dap = ap->dap;
232 int retval = swd_check_reconnect(dap);
233 if (retval != ERROR_OK)
236 swd_queue_ap_bankselect(ap, reg);
237 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
238 dap->last_read = data;
240 return check_sync(dap);
243 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
246 const struct swd_driver *swd = jtag_interface->swd;
249 struct adiv5_dap *dap = ap->dap;
251 int retval = swd_check_reconnect(dap);
252 if (retval != ERROR_OK)
255 swd_finish_read(dap);
256 swd_queue_ap_bankselect(ap, reg);
257 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
259 return check_sync(dap);
262 /** Executes all queued DAP operations. */
263 static int swd_run(struct adiv5_dap *dap)
265 swd_finish_read(dap);
266 return swd_run_inner(dap);
269 const struct dap_ops swd_dap_ops = {
270 .queue_dp_read = swd_queue_dp_read,
271 .queue_dp_write = swd_queue_dp_write,
272 .queue_ap_read = swd_queue_ap_read,
273 .queue_ap_write = swd_queue_ap_write,
274 .queue_ap_abort = swd_queue_ap_abort,
279 * This represents the bits which must be sent out on TMS/SWDIO to
280 * switch a DAP implemented using an SWJ-DP module into SWD mode.
281 * These bits are stored (and transmitted) LSB-first.
283 * See the DAP-Lite specification, section 2.2.5 for information
284 * about making the debug link select SWD or JTAG. (Similar info
285 * is in a few other ARM documents.)
287 static const uint8_t jtag2swd_bitseq[] = {
288 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
289 * putting both JTAG and SWD logic into reset state.
291 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
292 /* Switching sequence enables SWD and disables JTAG
293 * NOTE: bits in the DP's IDCODE may expose the need for
294 * an old/obsolete/deprecated sequence (0xb6 0xed).
297 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
298 * putting both JTAG and SWD logic into reset state.
300 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
304 * Put the debug link into SWD mode, if the target supports it.
305 * The link's initial mode may be either JTAG (for example,
306 * with SWJ-DP after reset) or SWD.
308 * @param target Enters SWD mode (if possible).
310 * Note that targets using the JTAG-DP do not support SWD, and that
311 * some targets which could otherwise support it may have have been
312 * configured to disable SWD signaling
314 * @return ERROR_OK or else a fault code.
316 int dap_to_swd(struct target *target)
318 struct arm *arm = target_to_arm(target);
322 LOG_ERROR("SWD mode is not available");
326 LOG_DEBUG("Enter SWD mode");
328 /* REVISIT it's ugly to need to make calls to a "jtag"
329 * subsystem if the link may not be in JTAG mode...
332 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
333 jtag2swd_bitseq, TAP_INVALID);
334 if (retval == ERROR_OK)
335 retval = jtag_execute_queue();
337 /* set up the DAP's ops vector for SWD mode. */
338 arm->dap->ops = &swd_dap_ops;
343 static const struct command_registration swd_commands[] = {
346 * Set up SWD and JTAG targets identically, unless/until
347 * infrastructure improves ... meanwhile, ignore all
348 * JTAG-specific stuff like IR length for SWD.
350 * REVISIT can we verify "just one SWD DAP" here/early?
353 .jim_handler = jim_jtag_newtap,
354 .mode = COMMAND_CONFIG,
355 .help = "declare a new SWD DAP"
357 COMMAND_REGISTRATION_DONE
360 static const struct command_registration swd_handlers[] = {
364 .help = "SWD command group",
365 .chain = swd_commands,
367 COMMAND_REGISTRATION_DONE
370 static int swd_select(struct command_context *ctx)
374 retval = register_commands(ctx, NULL, swd_handlers);
376 if (retval != ERROR_OK)
379 const struct swd_driver *swd = jtag_interface->swd;
381 /* be sure driver is in SWD mode; start
382 * with hardware default TRN (1), it can be changed later
384 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
385 LOG_DEBUG("no SWD driver?");
389 retval = swd->init();
390 if (retval != ERROR_OK) {
391 LOG_DEBUG("can't init SWD driver");
395 /* force DAP into SWD mode (not JTAG) */
396 /*retval = dap_to_swd(target);*/
398 if (ctx->current_target) {
399 /* force DAP into SWD mode (not JTAG) */
400 struct target *target = get_current_target(ctx);
401 retval = dap_to_swd(target);
407 static int swd_init(struct command_context *ctx)
409 struct target *target = get_current_target(ctx);
410 struct arm *arm = target_to_arm(target);
411 struct adiv5_dap *dap = arm->dap;
412 /* Force the DAP's ops vector for SWD mode.
413 * messy - is there a better way? */
414 arm->dap->ops = &swd_dap_ops;
416 return swd_connect(dap);
419 static struct transport swd_transport = {
421 .select = swd_select,
425 static void swd_constructor(void) __attribute__((constructor));
426 static void swd_constructor(void)
428 transport_register(&swd_transport);
431 /** Returns true if the current debug session
432 * is using SWD as its transport.
434 bool transport_is_swd(void)
436 return get_current_transport() == &swd_transport;