1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 ***************************************************************************/
21 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
22 * link protocol used in cases where JTAG is not wanted. This is coupled to
23 * recent versions of ARM's "CoreSight" debug framework. This specific code
24 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
25 * understanding operation semantics, shared with the JTAG transport.
27 * Single-DAP support only.
29 * for details, see "ARM IHI 0031A"
30 * ARM Debug Interface v5 Architecture Specification
31 * especially section 5.3 for SWD protocol
33 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
34 * to JTAG. Boards may support one or both. There are also SWD-only chips,
35 * (using SW-DP not SWJ-DP).
37 * Even boards that also support JTAG can benefit from SWD support, because
38 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
39 * That is, trace access may require SWD support.
48 #include "arm_adi_v5.h"
49 #include <helper/time_support.h>
51 #include <transport/transport.h>
52 #include <jtag/interface.h>
56 /* for debug, set do_sync to true to force synchronous transfers */
59 static void swd_finish_read(struct adiv5_dap *dap)
61 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
63 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
64 dap->last_read = NULL;
68 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
70 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
73 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
75 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
78 swd->write_reg(swd_cmd(false, false, DP_ABORT),
79 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
82 static int swd_run_inner(struct adiv5_dap *dap)
84 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
89 if (retval != ERROR_OK) {
91 dap->do_reconnect = true;
97 static int swd_connect(struct adiv5_dap *dap)
99 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
100 uint32_t dpidr = 0xdeadbeef;
103 /* FIXME validate transport config ... is the
104 * configured DAP present (check IDCODE)?
105 * Is *only* one DAP configured?
110 /* Check if we should reset srst already when connecting, but not if reconnecting. */
111 if (!dap->do_reconnect) {
112 enum reset_types jtag_reset_config = jtag_get_reset_config();
114 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
115 if (jtag_reset_config & RESET_SRST_NO_GATING)
116 adapter_assert_reset();
118 LOG_WARNING("\'srst_nogate\' reset_config option is required");
123 int64_t timeout = timeval_ms() + 500;
126 /* Note, debugport_init() does setup too */
127 swd->switch_seq(JTAG_TO_SWD);
129 /* Clear link state, including the SELECT cache. */
130 dap->do_reconnect = false;
131 dap_invalidate_cache(dap);
133 status = swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
134 if (status == ERROR_OK) {
135 status = swd_run_inner(dap);
136 if (status == ERROR_OK)
142 } while (timeval_ms() < timeout);
144 if (status != ERROR_OK) {
145 LOG_ERROR("Error connecting DP: cannot read IDR");
149 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
152 dap->do_reconnect = false;
154 /* force clear all sticky faults */
155 swd_clear_sticky_errors(dap);
157 status = swd_run_inner(dap);
158 if (status != ERROR_WAIT)
163 } while (timeval_ms() < timeout);
166 * "A WAIT response must not be issued to the ...
167 * ... writes to the ABORT register"
168 * swd_clear_sticky_errors() writes to the ABORT register only.
170 * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
171 * in a corner case. Just try if ABORT resolves the problem.
173 if (status == ERROR_WAIT) {
174 LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
176 dap->do_reconnect = false;
178 swd->write_reg(swd_cmd(false, false, DP_ABORT),
179 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
180 status = swd_run_inner(dap);
183 if (status == ERROR_OK)
184 status = dap_dp_init(dap);
189 static int swd_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
191 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
194 return swd->switch_seq(seq);
197 static inline int check_sync(struct adiv5_dap *dap)
199 return do_sync ? swd_run_inner(dap) : ERROR_OK;
202 static int swd_check_reconnect(struct adiv5_dap *dap)
204 if (dap->do_reconnect)
205 return swd_connect(dap);
210 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
212 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
215 swd->write_reg(swd_cmd(false, false, DP_ABORT),
216 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
217 return check_sync(dap);
220 /** Select the DP register bank matching bits 7:4 of reg. */
221 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
223 /* Only register address 4 is banked. */
224 if ((reg & 0xf) != 4)
227 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
228 uint32_t sel = select_dp_bank
229 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
231 if (sel == dap->select)
236 int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
237 if (retval != ERROR_OK)
238 dap->select = DP_SELECT_INVALID;
243 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
246 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
249 int retval = swd_check_reconnect(dap);
250 if (retval != ERROR_OK)
253 retval = swd_queue_dp_bankselect(dap, reg);
254 if (retval != ERROR_OK)
257 swd->read_reg(swd_cmd(true, false, reg), data, 0);
259 return check_sync(dap);
262 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
265 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
268 int retval = swd_check_reconnect(dap);
269 if (retval != ERROR_OK)
272 swd_finish_read(dap);
273 if (reg == DP_SELECT) {
274 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
276 swd->write_reg(swd_cmd(false, false, reg), data, 0);
278 retval = check_sync(dap);
279 if (retval != ERROR_OK)
280 dap->select = DP_SELECT_INVALID;
285 retval = swd_queue_dp_bankselect(dap, reg);
286 if (retval != ERROR_OK)
289 swd->write_reg(swd_cmd(false, false, reg), data, 0);
291 return check_sync(dap);
294 /** Select the AP register bank matching bits 7:4 of reg. */
295 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
297 struct adiv5_dap *dap = ap->dap;
298 uint32_t sel = ((uint32_t)ap->ap_num << 24)
300 | (dap->select & DP_SELECT_DPBANK);
302 if (sel == dap->select)
307 int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
308 if (retval != ERROR_OK)
309 dap->select = DP_SELECT_INVALID;
314 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
317 struct adiv5_dap *dap = ap->dap;
318 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
321 int retval = swd_check_reconnect(dap);
322 if (retval != ERROR_OK)
325 retval = swd_queue_ap_bankselect(ap, reg);
326 if (retval != ERROR_OK)
329 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
330 dap->last_read = data;
332 return check_sync(dap);
335 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
338 struct adiv5_dap *dap = ap->dap;
339 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
342 int retval = swd_check_reconnect(dap);
343 if (retval != ERROR_OK)
346 swd_finish_read(dap);
347 retval = swd_queue_ap_bankselect(ap, reg);
348 if (retval != ERROR_OK)
351 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
353 return check_sync(dap);
356 /** Executes all queued DAP operations. */
357 static int swd_run(struct adiv5_dap *dap)
359 swd_finish_read(dap);
360 return swd_run_inner(dap);
363 /** Put the SWJ-DP back to JTAG mode */
364 static void swd_quit(struct adiv5_dap *dap)
366 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
368 swd->switch_seq(SWD_TO_JTAG);
369 /* flush the queue before exit */
373 const struct dap_ops swd_dap_ops = {
374 .connect = swd_connect,
375 .send_sequence = swd_send_sequence,
376 .queue_dp_read = swd_queue_dp_read,
377 .queue_dp_write = swd_queue_dp_write,
378 .queue_ap_read = swd_queue_ap_read,
379 .queue_ap_write = swd_queue_ap_write,
380 .queue_ap_abort = swd_queue_ap_abort,
385 static const struct command_registration swd_commands[] = {
388 * Set up SWD and JTAG targets identically, unless/until
389 * infrastructure improves ... meanwhile, ignore all
390 * JTAG-specific stuff like IR length for SWD.
392 * REVISIT can we verify "just one SWD DAP" here/early?
395 .jim_handler = jim_jtag_newtap,
396 .mode = COMMAND_CONFIG,
397 .help = "declare a new SWD DAP"
399 COMMAND_REGISTRATION_DONE
402 static const struct command_registration swd_handlers[] = {
406 .help = "SWD command group",
407 .chain = swd_commands,
410 COMMAND_REGISTRATION_DONE
413 static int swd_select(struct command_context *ctx)
415 /* FIXME: only place where global 'adapter_driver' is still needed */
416 extern struct adapter_driver *adapter_driver;
417 const struct swd_driver *swd = adapter_driver->swd_ops;
420 retval = register_commands(ctx, NULL, swd_handlers);
421 if (retval != ERROR_OK)
424 /* be sure driver is in SWD mode; start
425 * with hardware default TRN (1), it can be changed later
427 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
428 LOG_DEBUG("no SWD driver?");
432 retval = swd->init();
433 if (retval != ERROR_OK) {
434 LOG_DEBUG("can't init SWD driver");
441 static int swd_init(struct command_context *ctx)
443 /* nothing done here, SWD is initialized
444 * together with the DAP */
448 static struct transport swd_transport = {
450 .select = swd_select,
454 static void swd_constructor(void) __attribute__((constructor));
455 static void swd_constructor(void)
457 transport_register(&swd_transport);
460 /** Returns true if the current debug session
461 * is using SWD as its transport.
463 bool transport_is_swd(void)
465 return get_current_transport() == &swd_transport;